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| author | Timur Tabi <timur@freescale.com> | 2010-07-21 16:56:19 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-07 09:49:47 -0500 |
| commit | a2d12f88129a0a1a7c18630b7a48ade22a48416e (patch) | |
| tree | acda8b16207894aabd2627f05119500eeee88c8c /doc | |
| parent | b6bde930901b1375264865b979507eb25806cb77 (diff) | |
| download | u-boot-a2d12f88129a0a1a7c18630b7a48ade22a48416e.tar.gz u-boot-a2d12f88129a0a1a7c18630b7a48ade22a48416e.tar.xz u-boot-a2d12f88129a0a1a7c18630b7a48ade22a48416e.zip | |
p1022ds: add audclk hwconfig setting to enable codec reference clock
The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference
clock for the audio codec, but by default both are disabled. Add a 'audclk'
hwconfig option that allows the user to choose which clock he wants.
The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48,
64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and
88200Hz.
Also configure a pin muxing to select some SSI signals, which will disable
I2C1.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.fsl-hwconfig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig new file mode 100644 index 0000000000..03fea74db3 --- /dev/null +++ b/doc/README.fsl-hwconfig @@ -0,0 +1,21 @@ +Freescale-specific 'hwconfig' options. + +This file documents Freescale-specific key:value pairs for the 'hwconfig' +option. See README.hwconfig for general information about 'hwconfig'. + +audclk + Specific to the P1022DS reference board. + + This option specifies which of the two oscillator frequencies should be + routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to + route either a 11.2896MHz or a 12.288MHz clock. The default is + 12.288MHz. This option has two effects. First, the MUX on the board + will be programmed accordingly. Second, the clock-frequency property + in the codec node in the device tree will be updated to the correct + value. + + 'audclk:11' + Select the 11.2896MHz clock + + 'audclk:12' + Select the 12.288MHz clock |