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| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /doc/README.mpc85xxads | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.gz u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.xz u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.zip | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'doc/README.mpc85xxads')
| -rw-r--r-- | doc/README.mpc85xxads | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index c488f2a56b..08d6831fb6 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -143,6 +143,7 @@ Updated 13-July-2004 Jon Loeliger CONFIG_DDR_ECC only for ECC DDR module CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability. + CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. Other than the above definitions, the rest in the config files are straightforward. @@ -190,10 +191,10 @@ straightforward. 4.4 Reflash U-boot Image using U-boot - => tftp 10000 u-boot.bin - => protect off fff80000 ffffffff - => erase fff80000 ffffffff - => cp.b 10000 fff80000 80000 + tftp 10000 u-boot.bin + protect off fff80000 ffffffff + erase fff80000 ffffffff + cp.b 10000 fff80000 80000 4.5 Reflash U-Boot with a BDI-2000 |