Merge branch 'master' of git://git.denx.de/u-boot-coldfire

15 files changed, 1119 insertions, 269 deletions

diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
index d0e9b4550f..44f93850e2 100644
--- a/cpu/mcf5227x/Makefile
+++ b/cpu/mcf5227x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c
index 765aec639a..d9f5f43c3c 100644
--- a/cpu/mcf5227x/cpu.c
+++ b/cpu/mcf5227x/cpu.c
@@ -65,12 +65,12 @@ int checkcpu(void)
 		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
 		       ver);
 		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
-		       strmhz(buf1, gd->cpu_clk)),
-		       strmhz(buf2, gd->bus_clk)),
-		       strmhz(buf3, gd->flb_clk)));
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk),
+		       strmhz(buf3, gd->flb_clk));
 		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
-		       strmhz(buf1, gd->inp_clk)),
-		       strmhz(buf2, gd->vco_clk)));
+		       strmhz(buf1, gd->inp_clk),
+		       strmhz(buf2, gd->vco_clk));
 	}
 
 	return 0;
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index 0f1dd1f125..8945ef3160 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -45,6 +45,7 @@ void cpu_init_f(void)
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
 
+#if !defined(CONFIG_CF_SBF)
 	/* Workaround, must place before fbcs */
 	pll->psr = 0x12;
 
@@ -58,37 +59,44 @@ void cpu_init_f(void)
 	scm1->pacrg = 0;
 	scm1->pacri = 0;
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
 	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
 	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
+#endif				/* CONFIG_CF_SBF */
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
 	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
 	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
 	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
 	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
 	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
 	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
 	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
 	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
 	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
 	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
 	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
 	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
 	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
 	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c
new file mode 100644
index 0000000000..7f48f91844
--- /dev/null
+++ b/cpu/mcf5227x/dspi.c
@@ -0,0 +1,261 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+
+void dspi_init(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	gpio->par_dspi =
+	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+
+	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
+#endif
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x000000F0) == 0) ;
+
+	return (dspi->drfr & 0xFFFF);
+}
+
+#if defined(CONFIG_CMD_SPI)
+void spi_init_f(void)
+{
+}
+
+void spi_init_r(void)
+{
+}
+
+void spi_init(void)
+{
+	dspi_init();
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct spi_slave *slave;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		break;
+	}
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	switch (slave->cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		break;
+	}
+
+	free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	static int bWrite = 0;
+	u8 *spi_rd, *spi_wr;
+	int len = bitlen >> 3;
+
+	spi_rd = (u8 *) din;
+	spi_wr = (u8 *) dout;
+
+	/* command handling */
+	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
+		switch (*spi_wr) {
+		case 0x02:	/* Page Prog */
+			bWrite = 1;
+			dspi_tx(slave->cs, 0x80, spi_wr[0]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[1]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[2]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[3]);
+			dspi_rx();
+			return 0;
+		case 0x05:	/* Read Status */
+			if (len == 4)
+				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
+				    && (spi_wr[3] == 0xFF)) {
+					dspi_tx(slave->cs, 0x80, *spi_wr);
+					dspi_rx();
+				}
+			return 0;
+		case 0x06:	/* WREN */
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0x0B:	/* Fast read */
+			if ((len == 5) && (spi_wr[4] == 0)) {
+				dspi_tx(slave->cs, 0x80, spi_wr[0]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[1]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[2]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[3]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[4]);
+				dspi_rx();
+			}
+			return 0;
+		case 0x9F:	/* RDID */
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0xD8:	/* Sector erase */
+			if (len == 4)
+				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
+					dspi_tx(slave->cs, 0x80, spi_wr[0]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[1]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[2]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x00, spi_wr[3]);
+					dspi_rx();
+				}
+			return 0;
+		}
+	}
+
+	if (bWrite)
+		len--;
+
+	while (len--) {
+		if (dout != NULL) {
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			spi_wr++;
+		}
+
+		if (din != NULL) {
+			dspi_tx(slave->cs, 0x80, 0);
+			*spi_rd = dspi_rx();
+			spi_rd++;
+		}
+	}
+
+	if (flags == SPI_XFER_END) {
+		if (bWrite) {
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			bWrite = 0;
+		} else {
+			dspi_tx(slave->cs, 0x00, 0);
+			dspi_rx();
+		}
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_SPI */
+
+#endif				/* CONFIG_CF_DSPI */
diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c
index 74b9059d3d..7e385d3998 100644
--- a/cpu/mcf5227x/speed.c
+++ b/cpu/mcf5227x/speed.c
@@ -90,17 +90,33 @@ int get_clocks(void)
 	int vco, temp, pcrvalue, pfdr;
 	u8 bootmode;
 
-	bootmode = (ccm->ccr & 0x000C) >> 2;
-
 	pcrvalue = pll->pcr & 0xFF0F0FFF;
 	pfdr = pcrvalue >> 24;
 
-	if (pfdr != 0x1E) {
+	if (pfdr == 0x1E)
+		bootmode = 0;	/* Normal Mode */
+
+#ifdef CONFIG_CF_SBF
+	bootmode = 3;		/* Serial Mode */
+#endif
+
+	if (bootmode == 0) {
+		/* Normal mode */
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* Default value */
+			pcrvalue = (pll->pcr & 0x00FFFFFF);
+			pcrvalue |= 0x1E << 24;
+			pll->pcr = pcrvalue;
+			vco =
+			    ((pll->pcr & 0xFF000000) >> 24) *
+			    CONFIG_SYS_INPUT_CLKSRC;
+		}
+		gd->vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 3) {
 		/* serial mode */
-	} else {
-		/* Normal Mode */
-		vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
-		gd->vco_clk = vco;
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		gd->vco_clk = vco;	/* Vco clock */
 	}
 
 	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index becaab7c25..93872507b1 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -46,6 +46,11 @@
 	addl	#60,%sp;		/* space for 15 regs */ \
 	rte;
 
+#if defined(CONFIG_CF_SBF)
+#define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
 .text
 /*
  *	Vector table. This is used for initial platform startup.
@@ -53,8 +58,14 @@
  */
 _vectors:
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC		*/
+#if defined(CONFIG_CF_SBF)
+INITSP:		.long	0		/* Initial SP	*/
+INITPC:		.long	ASM_DRAMINIT	/* Initial PC 	*/
+#else
+INITSP:		.long	0	/* Initial SP	*/
+INITPC:		.long	_START	/* Initial PC 		*/
+#endif
+
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
@@ -83,6 +94,7 @@ vector1D:	.long	_FAULT	/* Autovector Level 5	*/
 vector1E:	.long	_FAULT	/* Autovector Level 6	*/
 vector1F:	.long	_FAULT	/* Autovector Level 7	*/
 
+#if !defined(CONFIG_CF_SBF)
 /* TRAP #0 - #15 */
 vector20_2F:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -122,9 +134,231 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
 
-	.text
+#if defined(CONFIG_CF_SBF)
+	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+	.long	0x00000000	/* checksum, not yet implemented */
+	.long	0x00020000	/* image length */
+	.long	TEXT_BASE	/* image to be relocated at */
+
+asm_dram_init:
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1	/* init Rambar */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/*
+	 * Dram Initialization
+	 * a1, a2, and d0
+	 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
 
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+	nop
+
+	move.l	#1000, %d0
+wait1000:
+	nop
+	subq.l	#1, %d0
+	bne	wait1000
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
+	and.l	#0x7FFFFFFF, %d0
+	or.l	#0x10000c00, %d0
+	move.l	%d0, (%a2)
+	nop
+
+	/*
+	 * DSPI Initialization
+	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
+	 * a1 - dspi status
+	 * a2 - dtfr
+	 * a3 - drfr
+	 * a4 - Dst addr
+	 */
+
+	/* Enable pins for DSPI mode - chip-selects are enabled later */
+	move.l	#0xFC0A4036, %a0
+	move.b	#0x3F, %d0
+	move.b	%d0, (%a0)
+
+	/* DSPI CS */
+#ifdef CONFIG_SYS_DSPI_CS0
+	move.b	(%a0), %d0
+	or.l	#0xC0, %d0
+	move.b	%d0, (%a0)
+#endif
+#ifdef CONFIG_SYS_DSPI_CS2
+	move.l	#0xFC0A4037, %a0
+	move.b	(%a0), %d0
+	or.l	#0x10, %d0
+	move.b	%d0, (%a0)
+#endif
+	nop
+
+	/* Configure DSPI module */
+	move.l	#0xFC05C000, %a0
+	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
+
+	move.l	#0xFC05C00C, %a0
+	move.l	#0x3E000011, (%a0)
+
+	move.l	#0xFC05C034, %a2	/* dtfr */
+	move.l	#0xFC05C03B, %a3	/* drfr */
+
+	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
+	move.l	(%a1)+, %d5
+	move.l	(%a1), %a4
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+	move.l	#0xFC05C02C, %a1	/* dspi status */
+
+	/* Issue commands and address */
+	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 2 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 1 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 0 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a0)		/* read, copy to dst */
+
+	add.l	#1, %a0			/* inc dst by 1 */
+	sub.l	#1, %d4			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop1
+
+	/* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a4)		/* read, copy to dst */
+
+	add.l	#1, %a4			/* inc dst by 1 */
+	sub.l	#1, %d5			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop2
+
+	move.l	#0x00040000, %d2	/* Terminate */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* jump to memory and execute */
+	move.l	#(TEXT_BASE + 0x400), %a0
+	move.l	%a0, (%a1)
+	jmp	(%a0)
+
+asm_dspi_wr_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x0000F000, %d0
+	cmp.l	#0x00003000, %d0
+	bgt	asm_dspi_wr_status
+
+	move.l	%d2, (%a2)
+	rts
+
+asm_dspi_rd_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x000000F0, %d0
+	lsr.l	#4, %d0
+	cmp.l	#0, %d0
+	beq	asm_dspi_rd_status
+
+	move.b	(%a3), %d1
+	rts
+#endif			/* CONFIG_CF_SBF */
+
+	.text
+	. = 0x400
 	.globl	_start
 _start:
 	nop
@@ -132,11 +366,16 @@ _start:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
+#if defined(CONFIG_CF_SBF)
+	move.l	#TEXT_BASE, %d0
+	movec	%d0, %VBR
+#else
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
+#endif
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c
index b9e48aa433..a1a51336c2 100644
--- a/cpu/mcf523x/cpu.c
+++ b/cpu/mcf523x/cpu.c
@@ -65,8 +65,8 @@ int checkcpu(void)
 		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
 		       ver);
 		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
-		       strmhz(buf1, gd->cpu_clk)),
-		       strmhz(buf2, gd->bus_clk)));
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk));
 	}
 
 	return 0;
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c
index 652094485e..3c04fd4134 100644
--- a/cpu/mcf523x/cpu_init.c
+++ b/cpu/mcf523x/cpu_init.c
@@ -27,9 +27,14 @@
 
 #include <common.h>
 #include <watchdog.h>
-
 #include <asm/immap.h>
 
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -143,3 +148,20 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+	} else {
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+	}
+
+	return 0;
+}
+#endif
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 7bb358e63f..18308c8a7a 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -36,6 +36,71 @@
 #include <watchdog.h>
 #include <asm/immap.h>
 
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+     && defined(CONFIG_SYS_CS6_CTRL))
+	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+     && defined(CONFIG_SYS_CS7_CTRL))
+	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+#endif
+}
+#endif
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
@@ -66,22 +131,14 @@ void cpu_init_f(void)
 	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
 	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 
-	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
-
-	/*
-	 *  Setup chip selects...
-	 */
-
-	mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
-	mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
-	mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
+	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
 
-	mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
-	mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
-	mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
+	/* FlexBus Chipselect */
+	init_fbcs();
 
 #ifdef CONFIG_FSL_I2C
-	CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+	CONFIG_SYS_I2C_PINMUX_REG =
+	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
@@ -121,6 +178,9 @@ void cpu_init_f(void)
 	mbar_writeShort(MCF_WTM_WCR, 0);
 #endif
 
+	/* FlexBus Chipselect */
+	init_fbcs();
+
 	/* Set clockspeed to 100MHz */
 	mbar_writeShort(MCF_FMPLL_SYNCR,
 			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@@ -153,6 +213,19 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	if (setclear) {
+		/* Enable Ethernet pins */
+		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+	} else {
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
 #endif
 
 #if defined(CONFIG_M5272)
@@ -255,6 +328,22 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+	} else {
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
 #endif				/* #if defined(CONFIG_M5272) */
 
 #if defined(CONFIG_M5275)
@@ -268,66 +357,20 @@ void uart_port_conf(void)
  */
 void cpu_init_f(void)
 {
-	/* if we come from RAM we assume the CPU is
+	/*
+	 * if we come from RAM we assume the CPU is
 	 * already initialized.
 	 */
 
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
-	volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 
 	/* Kill watchdog so we can initialize the PLL */
 	wdog_reg->wcr = 0;
 
-	/* Memory Controller: */
-	/* Flash */
-	csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
-	csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
-	csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
-
-#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
-	csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
-	csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
-	csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
-	csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
-	csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
-	csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
-	csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
-	csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
-	csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
-	csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
-	csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
-	csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
-	csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
-	csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
-	csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
-	csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
-	csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
-	csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
-	csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
-	csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
-	csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
-#endif
-
+	/* FlexBus Chipselect */
+	init_fbcs();
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 
 #ifdef CONFIG_FSL_I2C
@@ -349,7 +392,7 @@ int cpu_init_r(void)
 
 void uart_port_conf(void)
 {
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (CONFIG_SYS_UART_PORT) {
@@ -364,6 +407,35 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	if (setclear) {
+		/* Enable Ethernet pins */
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			gpio->par_feci2c |= 0x0F00;
+			gpio->par_fec0hl |= 0xC0;
+		} else {
+			gpio->par_feci2c |= 0x00A0;
+			gpio->par_fec1hl |= 0xC0;
+		}
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			gpio->par_feci2c &= ~0x0F00;
+			gpio->par_fec0hl &= ~0xC0;
+		} else {
+			gpio->par_feci2c &= ~0x00A0;
+			gpio->par_fec1hl &= ~0xC0;
+		}
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
 #endif				/* #if defined(CONFIG_M5275) */
 
 #if defined(CONFIG_M5282)
@@ -384,7 +456,8 @@ void cpu_init_f(void)
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 	/* Set speed /PLL */
 	MCFCLOCK_SYNCR =
-	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 
 	MCFGPIO_PBCDPAR = 0xc0;
@@ -425,119 +498,8 @@ void cpu_init_f(void)
 	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 #endif
 
-	/* This is probably a bad place to setup chip selects, but everyone
-	   else is doing it! */
-
-#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
-    defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
-
-	MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS0_WIDTH == 8)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS0_WIDTH == 16)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS0_WIDTH == 32)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
-#endif
-	MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
-	    | CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS0_RO != 0)
-	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 0 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
-    defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
-
-	MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS1_WIDTH == 8)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS1_WIDTH == 16)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS1_WIDTH == 32)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
-#endif
-	MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
-	    | CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS1_RO != 0)
-	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 1 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
-    defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
-
-	MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS2_WIDTH == 8)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS2_WIDTH == 16)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS2_WIDTH == 32)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
-#endif
-	MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
-	    | CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS2_RO != 0)
-	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 2 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
-    defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
-
-	MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS3_WIDTH == 8)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS3_WIDTH == 16)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS3_WIDTH == 32)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
-#endif
-	MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
-	    | CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS3_RO != 0)
-	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 3 are not initialized/used"
-#endif
+	/* FlexBus Chipselect */
+	init_fbcs();
 
 #endif				/* CONFIG_MONITOR_IS_IN_RAM */
 
@@ -571,6 +533,20 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	if (setclear) {
+		MCFGPIO_PASPAR |= 0x0F00;
+		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+	} else {
+		MCFGPIO_PASPAR &= 0xF0FF;
+		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+	}
+	return 0;
+}
+#endif			/* CONFIG_CMD_NET */
 #endif
 
 #if defined(CONFIG_M5249)
@@ -632,17 +608,8 @@ void cpu_init_f(void)
 	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 
-	/*
-	 *  Setup chip selects...
-	 */
-
-	mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
-	mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
-	mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
-
-	mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
-	mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
-	mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
+	/* FlexBus Chipselect */
+	init_fbcs();
 
 	/* enable instruction cache now */
 	icache_enable();
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index fd77939f24..331cc15da4 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -56,6 +56,24 @@ int checkcpu(void)
 	msk = (ccm->cir >> 6);
 	ver = (ccm->cir & 0x003f);
 	switch (msk) {
+#ifdef CONFIG_MCF5301x
+	case 0x78:
+		id = 53010;
+		break;
+	case 0x77:
+		id = 53012;
+		break;
+	case 0x76:
+		id = 53015;
+		break;
+	case 0x74:
+		id = 53011;
+		break;
+	case 0x73:
+		id = 53013;
+		break;
+#endif
+#ifdef CONFIG_MCF532x
 	case 0x54:
 		id = 5329;
 		break;
@@ -77,6 +95,7 @@ int checkcpu(void)
 	case 0x6B:
 		id = 5372;
 		break;
+#endif
 	}
 
 	if (id) {
@@ -85,8 +104,8 @@ int checkcpu(void)
 		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
 		       ver);
 		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
-		       strmhz(buf1, gd->cpu_clk)),
-		       strmhz(buf2, gd->bus_clk)));
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk));
 	}
 
 	return 0;
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index d348e29a1f..687c7e42ec 100644
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,16 +27,188 @@
 
 #include <common.h>
 #include <watchdog.h>
-
 #include <asm/immap.h>
 
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifdef CONFIG_MCF5301x
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	/* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+	/*wdog->cr = 0; */
+#endif
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+	scm1->pacrg = 0;
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	gpio->par_cs |= GPIO_PAR_CS0_CS0;
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	gpio->par_cs |= GPIO_PAR_CS1_CS1;
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	gpio->par_cs |= GPIO_PAR_CS4;
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	gpio->par_cs |= GPIO_PAR_CS5;
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+	gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+#endif
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFFEC
+	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+#endif
+#ifdef CONFIG_MCFRTC
+	volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+	volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+
+	rtcex->gocu = CONFIG_SYS_RTC_CNT;
+	rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+
+#endif
+#ifdef CONFIG_MCFFEC
+	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+		ccm->misccr |= CCM_MISCCR_FECM;
+	else
+		ccm->misccr &= ~CCM_MISCCR_FECM;
+#endif
+
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CONFIG_SYS_UART_PORT) {
+	case 0:
+		gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+#ifdef CONFIG_SYS_UART1_ALT1_GPIO
+		gpio->par_simp1h &=
+		    ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+		gpio->par_simp1h |=
+		    (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
+		gpio->par_ssih &=
+		    ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+		gpio->par_ssih |=
+		    (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+#endif
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		gpio->par_dspih &=
+		    ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+		gpio->par_dspih |=
+		    (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			gpio->par_fec |=
+			    GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
+			gpio->par_feci2c |=
+			    GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+		} else {
+			gpio->par_fec |=
+			    GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
+			gpio->par_feci2c |=
+			    GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+		}
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			gpio->par_fec &=
+			    ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+		} else {
+			gpio->par_fec &=
+			    ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+		}
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_MCF5301x */
+
+#ifdef CONFIG_MCF532x
 void cpu_init_f(void)
 {
 	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
@@ -63,13 +235,15 @@ void cpu_init_f(void)
 	/* Port configuration */
 	gpio->par_cs = 0;
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
 	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
 	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
 	/* Latch chipselect */
 	gpio->par_cs |= GPIO_PAR_CS1;
 	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
@@ -77,28 +251,32 @@ void cpu_init_f(void)
 	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
 	gpio->par_cs |= GPIO_PAR_CS2;
 	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
 	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
 	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
 	gpio->par_cs |= GPIO_PAR_CS3;
 	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
 	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
 	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
 	gpio->par_cs |= GPIO_PAR_CS4;
 	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
 	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
 	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
 	gpio->par_cs |= GPIO_PAR_CS5;
 	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
 	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
@@ -139,3 +317,22 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+	} else {
+		gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+	}
+	return 0;
+}
+#endif
+#endif				/* CONFIG_MCF532x */
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
index 1e40374d09..0d378e63d4 100644
--- a/cpu/mcf532x/speed.c
+++ b/cpu/mcf532x/speed.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MAX_FVCO	500000	/* KHz */
 #define MAX_FSYS	80000	/* KHz */
 #define MIN_FSYS	58333	/* KHz */
+
+#ifdef CONFIG_MCF5301x
+#define FREF		20000	/* KHz */
+#define MAX_MFD		63	/* Multiplier */
+#define MIN_MFD		0	/* Multiplier */
+#define USBDIV		8
+
+/* Low Power Divider specifications */
+#define MIN_LPD		(0)	/* Divider (not encoded) */
+#define MAX_LPD		(15)	/* Divider (not encoded) */
+#define DEFAULT_LPD	(0)	/* Divider (not encoded) */
+#endif
+
+#ifdef CONFIG_MCF532x
 #define FREF		16000	/* KHz */
 #define MAX_MFD		135	/* Multiplier */
 #define MIN_MFD		88	/* Multiplier */
-#define BUSDIV		6	/* Divider */
-/*
- * Low Power Divider specifications
- */
+
+/* Low Power Divider specifications */
 #define MIN_LPD		(1 << 0)	/* Divider (not encoded) */
 #define MAX_LPD		(1 << 15)	/* Divider (not encoded) */
 #define DEFAULT_LPD	(1 << 1)	/* Divider (not encoded) */
+#endif
 
-/*
- * Get the value of the current system clock
- *
- * Parameters:
- *  none
- *
- * Return Value:
- *  The current output system frequency
- */
+#define BUSDIV		6	/* Divider */
+
+/* Get the value of the current system clock */
 int get_sys_clock(void)
 {
 	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -65,9 +72,23 @@ int get_sys_clock(void)
 	/* Test to see if device is in LIMP mode */
 	if (ccm->misccr & CCM_MISCCR_LIMP) {
 		divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+#ifdef CONFIG_MCF5301x
+		return (FREF / (3 * (1 << divider)));
+#endif
+#ifdef CONFIG_MCF532x
 		return (FREF / (2 << divider));
+#endif
 	} else {
+#ifdef CONFIG_MCF5301x
+		u32 pfdr = (pll->pcr & 0x3F) + 1;
+		u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
+		u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+
+		return (((FREF * pfdr) / refdiv) / busdiv);
+#endif
+#ifdef CONFIG_MCF532x
 		return ((FREF * pll->pfdr) / (BUSDIV * 4));
+#endif
 	}
 }
 
@@ -92,7 +113,7 @@ int clock_limp(int div)
 		div = MAX_LPD;
 
 	/* Save of the current value of the SSIDIV so we don't overwrite the value */
-	temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+	temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
 
 	/* Apply the divider to the system clock */
 	ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
@@ -102,15 +123,7 @@ int clock_limp(int div)
 	return (FREF / (3 * (1 << div)));
 }
 
-/*
- * Exit low power LIMP mode
- *
- * Parameters:
- *  div     Desired system frequency divider
- *
- * Return Value:
- *  The resulting output system frequency
- */
+/* Exit low power LIMP mode */
 int clock_exit_limp(void)
 {
 	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -139,7 +152,10 @@ int clock_exit_limp(void)
  */
 int clock_pll(int fsys, int flags)
 {
+#ifdef CONFIG_MCF532x
 	volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+#endif
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
 	int fref, temp, fout, mfd;
 	u32 i;
@@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags)
 
 	if (fsys == 0) {
 		/* Return current PLL output */
+#ifdef CONFIG_MCF5301x
+		u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
+		mfd = (pll->pcr & 0x3F) + 1;
+
+		return (fref * mfd) / busdiv;
+#endif
+#ifdef CONFIG_MCF532x
 		mfd = pll->pfdr;
 
 		return (fref * mfd / (BUSDIV * 4));
+#endif
 	}
 
 	/* Check bounds of requested system clock */
@@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags)
 	if (fsys < MIN_FSYS)
 		fsys = MIN_FSYS;
 
-	/* Multiplying by 100 when calculating the temp value,
-	   and then dividing by 100 to calculate the mfd allows
-	   for exact values without needing to include floating
-	   point libraries. */
+	/*
+	 * Multiplying by 100 when calculating the temp value,
+	 * and then dividing by 100 to calculate the mfd allows
+	 * for exact values without needing to include floating
+	 * point libraries.
+	 */
 	temp = (100 * fsys) / fref;
+#ifdef CONFIG_MCF5301x
+	mfd = (BUSDIV * temp) / 100;
+
+	/* Determine the output frequency for selected values */
+	fout = ((fref * mfd) / BUSDIV);
+#endif
+#ifdef CONFIG_MCF532x
 	mfd = (4 * BUSDIV * temp) / 100;
 
 	/* Determine the output frequency for selected values */
 	fout = ((fref * mfd) / (BUSDIV * 4));
+#endif
 
 	/*
 	 * Check to see if the SDRAM has already been initialized.
 	 * If it has then the SDRAM needs to be put into self refresh
 	 * mode before reprogramming the PLL.
 	 */
+	if (sdram->ctrl & SDRAMC_SDCR_REF)
+		sdram->ctrl &= ~SDRAMC_SDCR_CKE;
 
 	/*
 	 * Initialize the PLL to generate the new system clock frequency.
@@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags)
 	/* Enter LIMP mode */
 	clock_limp(DEFAULT_LPD);
 
+#ifdef CONFIG_MCF5301x
+	pll->pdr =
+	    PLL_PDR_OUTDIV1((BUSDIV / 3) - 1)	|
+	    PLL_PDR_OUTDIV2(BUSDIV - 1)	|
+	    PLL_PDR_OUTDIV3((BUSDIV / 2) - 1)	|
+	    PLL_PDR_OUTDIV4(USBDIV - 1);
+
+	pll->pcr &= PLL_PCR_FBDIV_MASK;
+	pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+#endif
+#ifdef CONFIG_MCF532x
 	/* Reprogram PLL for desired fsys */
 	pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
 
 	pll->pfdr = mfd;
+#endif
 
 	/* Exit LIMP mode */
 	clock_exit_limp();
 
+	/* Return the SDRAM to normal operation if it is in use. */
+	if (sdram->ctrl & SDRAMC_SDCR_REF)
+		sdram->ctrl |= SDRAMC_SDCR_CKE;
+
+#ifdef CONFIG_MCF532x
 	/*
-	 * Return the SDRAM to normal operation if it is in use.
+	 * software workaround for SDRAM opeartion after exiting LIMP
+	 * mode errata
 	 */
-
-	/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
 	*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+#endif
 
 	/* wait for DQS logic to relock */
 	for (i = 0; i < 0x200; i++) ;
@@ -205,9 +258,7 @@ int clock_pll(int fsys, int flags)
 	return fout;
 }
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks(void)
 {
 	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 7a3eb5f98c..8fa605a644 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -2,6 +2,9 @@
  * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
  * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
  *
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -140,6 +143,14 @@ _start:
 	movec	%d0, %ACR0
 	movec	%d0, %ACR1
 
+#ifdef CONFIG_MCF5301x
+	move.l	#(0xFC0a0010), %a0
+	move.w	(%a0), %d0
+	and.l	%d0, 0xEFFF
+
+	move.w	%d0, (%a0)
+#endif
+
 	/* initialize general use internal ram */
 	move.l #0, %d0
 	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 50b4561f3f..7e04e32c70 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -27,10 +27,15 @@
 
 #include <common.h>
 #include <watchdog.h>
-
 #include <asm/immap.h>
 #include <asm/rtc.h>
 
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -139,3 +144,30 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+	if (setclear) {
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+		else
+			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+	} else {
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+		else
+			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+	}
+	return 0;
+}
+#endif
diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c
index 9a0e04083c..1ba57835e5 100644
--- a/cpu/mcf547x_8x/cpu_init.c
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -29,6 +29,12 @@
 #include <MCD_dma.h>
 #include <asm/immap.h>
 
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fsl_mcdmafec.h>
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -130,3 +136,24 @@ void uart_port_conf(void)
 
 	*pscsicr &= 0xF8;
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			gpio->par_feci2cirq |= 0xF000;
+		else
+			gpio->par_feci2cirq |= 0x0FC0;
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			gpio->par_feci2cirq &= 0x0FFF;
+		else
+			gpio->par_feci2cirq &= 0xF03F;
+	}
+	return 0;
+}
+#endif