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authorPeter Tyser <ptyser@xes-inc.com>2009-05-21 12:10:00 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-06-12 17:17:58 -0500
commit2f21ce4d546d31289ac49a680f78bcc9a792c6ec (patch)
tree2e2406630e454eb04883ed255e37dd547caa521f /cpu
parentb1f12650d332eadac1306a772cab6096abee6ddd (diff)
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fsl/85xx, 86xx: Sync up DMA code
The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/cpu.c8
-rw-r--r--cpu/mpc86xx/cpu.c14
2 files changed, 12 insertions, 10 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 331fcc09a4..d88c564620 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -269,9 +269,9 @@ void dma_init(void) {
volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr = 0x02c40000;
- dma->datr = 0x02c40000;
- dma->sr = 0xfffffff; /* clear any errors */
+ dma->satr = 0x00040000;
+ dma->datr = 0x00040000;
+ dma->sr = 0xffffffff; /* clear any errors */
asm("sync; isync; msync");
return;
}
@@ -286,7 +286,7 @@ uint dma_check(void) {
status = dma->sr;
}
- /* clear MR0[CS] channel start bit */
+ /* clear MR[CS] channel start bit */
dma->mr &= 0x00000001;
asm("sync;isync;msync");
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f35323ac67..d47cc5ef3a 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -182,20 +182,19 @@ watchdog_reset(void)
void
dma_init(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
dma->satr = 0x00040000;
dma->datr = 0x00040000;
+ dma->sr = 0xffffffff; /* clear any errors */
asm("sync; isync");
}
uint
dma_check(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
volatile uint status = dma->sr;
@@ -204,6 +203,10 @@ dma_check(void)
status = dma->sr;
}
+ /* clear MR[CS] channel start bit */
+ dma->mr &= 0x00000001;
+ asm("sync;isync");
+
if (status != 0) {
printf("DMA Error: status = %x\n", status);
}
@@ -213,8 +216,7 @@ dma_check(void)
int
dma_xfer(void *dest, uint count, void *src)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_dma_t *dma_base = &immap->im_dma;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
volatile fsl_dma_t *dma = &dma_base->dma[0];
dma->dar = (uint) dest;