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| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /cpu/mpc8220 | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
| download | u-boot-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.gz u-boot-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.xz u-boot-8ed44d91c8122d00368523b0b746691c895d3b3c.zip | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/mpc8220')
| -rw-r--r-- | cpu/mpc8220/i2cCore.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc8220/i2cCore.c b/cpu/mpc8220/i2cCore.c index accf43c102..b89ad034f4 100644 --- a/cpu/mpc8220/i2cCore.c +++ b/cpu/mpc8220/i2cCore.c @@ -440,7 +440,7 @@ STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb) return OK; } -/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls +/* FDR table base on 33MHz - more detail please refer to Odini2c_dividers.xls FDR FDR scl sda scl2tap2 510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5 000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0 |