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authorWolfgang Denk <wd@pollux.(none)>2005-09-25 01:48:28 +0200
committerWolfgang Denk <wd@pollux.(none)>2005-09-25 01:48:28 +0200
commit74f4304ee717d0f4b3a27e7fd4a64944749b8783 (patch)
tree806aadd6a2be863b9a0e4e9649858468b4641c96 /cpu/arm920t/cpu.c
parente2146b6aea0de16e55530cc5ff58fb626d9870cd (diff)
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Add ARM946E cpu and core module targets; remap memory to 0x00000000
Patch by Peter Pearse, 2 Feb 2005
Diffstat (limited to 'cpu/arm920t/cpu.c')
-rw-r--r--cpu/arm920t/cpu.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 718f253471..2f7963dcf6 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -39,7 +39,7 @@ static unsigned long read_p15_c1 (void)
unsigned long value;
__asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
: "=r" (value)
:
: "memory");
@@ -57,7 +57,7 @@ static void write_p15_c1 (unsigned long value)
printf ("write %08lx to p15/c1\n", value);
#endif
__asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
:
: "r" (value)
: "memory");
@@ -73,16 +73,17 @@ static void cp_delay (void)
for (i = 0; i < 100; i++);
}
-/* See also ARM Ref. Man. */
+/* See also ARM920T Technical reference Manual */
#define C1_MMU (1<<0) /* mmu off/on */
#define C1_ALIGN (1<<1) /* alignment faults off/on */
#define C1_DC (1<<2) /* dcache off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
#define C1_SYS_PROT (1<<8) /* system protection */
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_IC (1<<12) /* icache off/on */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
int cpu_init (void)
{
@@ -119,6 +120,7 @@ int cleanup_before_linux (void)
/* flush I/D-cache */
i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+
return (0);
}
@@ -134,7 +136,7 @@ void icache_enable (void)
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = read_p15_c1 (); /* get control reg. */
cp_delay ();
write_p15_c1 (reg | C1_IC);
}