Convert mcc200 to use common CFI flash driver

Patch by Stefan Roese, 28 Feb 2006

4 files changed, 48 insertions, 1211 deletions

diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 162734bb83..7fdc088e9c 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o
+OBJS	:= $(BOARD).o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
diff --git a/board/mcc200/flash.c b/board/mcc200/flash.c
deleted file mode 100644
index 8e1757acd4..0000000000
--- a/board/mcc200/flash.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <flash.h>
-
-//###CHD: gehört wieder raus ist vom PXA271 file!
-#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T ( 32M = 128K x 255 + 32k x 4) */
-#define FLASH_28F256L18B 0x00B1		/* Intel 28F256L18B ( 32M = 32k x 4 + 128K x 255)  */
-#define FLASH_28F256P30B 0x001C		/* Intel 28F256P30B ( 32M = 32k x 4 + 128K x 255)  */
-#define FLASH_28F256P30T 0x0019		/* Intel 28F256P30T ( 128K x 255 + 32M = 32k x 4 + */
-
-#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
-#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
-#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
-#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
-#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
-#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
-#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
-#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
-#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
-#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
-
-#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
-#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
-#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
-#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
-#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
-#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
-#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
-#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
-
-#define INTEL_ID_28F128J3   0x89188918	/*  16M = 8M x 16 x 128 */
-#define INTEL_ID_28F320J5   0x00140014	/*  32M = 128K x  32	*/
-#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64	*/
-#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
-#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
-#define INTEL_ID_28F256L18  0x88108810	/*  32M = 128K x 255	*/
-#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
-#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
-#define INTEL_ID_28F256L18B 0x88108810	/* 256M =  32k x 4   + 128K x 255 */
-#define INTEL_ID_28F256P30B 0x891C891C	/* 256M =  32k x 4   + 128K x 255 */
-#define INTEL_ID_28F256P30T 0x89198919	/* 256M =  128K x 255 + 32k x 4 */
-#define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
-#define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
-#define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
-
-#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
-#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
-
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)               		(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)               		(x)
-#endif
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT  0x00890089
-#define INTEL_ALT     0x00B000B0
-
-
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x00100010
-#define INTEL_ERASE   0x00200020
-#define INTEL_CLEAR   0x00500050
-#define INTEL_LOCKBIT 0x00600060
-#define INTEL_PROTECT 0x00010001
-#define INTEL_STATUS  0x00700070
-#define INTEL_READID  0x00900090
-#define INTEL_CONFIRM 0x00D000D0
-#define INTEL_RESET   0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x00800080
-#define INTEL_OK       0x00800080
-
-#define FPW	   FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-///###CHD: auch wieder raus! + switch anweisung für den P30iger!
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18B[] = {
-	{4, 0x8000},			/* 4 * 32kBytes sectors */
-	{255, 0x20000},			/* 255 * 128kBytes sectors */
-};
-
-OrgDef OrgIntel_28F256L18T[] = {
-	{255, 0x20000},			/* 255 * 128kBytes sectors */
-	{4, 0x8000}			/* 4 * 32kBytes sectors */
-};
-
-OrgDef OrgIntel_28F128J3A[] = {
-	{128, 0x20000},			/* 128 * 128kBytes sectors */
-};
-static unsigned int OrgSectTypeNum_28F256L18 = 2;
-static unsigned int OrgSectTypeNum_28F256J3 = 1;
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(ulong, ulong);
-	ulong flashbase = CFG_FLASH_BASE;
-
-	flash_preinit();
-
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			memset(&flash_info[i], 0, sizeof(flash_info_t));
-			flash_get_size ((FPW *) flashbase, &flash_info[i]);
-			flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
-			break;
-		default:
-			panic ("configured to many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-
-		/* get the h/w and s/w protection status in sync */
-		flash_sync_real_protect(&flash_info[i]);
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#ifndef CONFIG_BOOT_ROM
-	flash_protect ( FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE + monitor_flash_len - 1,
-			&flash_info[0] );
-#endif
-#endif
-
-#ifdef	CFG_ENV_IS_IN_FLASH
-	flash_protect ( FLAG_PROTECT_SET,
-			CFG_ENV_ADDR,
-			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
-#endif
-
-	flash_afterinit(flash_info[0].start[0], flash_info[0].size);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		printf ("28F128J3A\n");
-		break;
-
-	case FLASH_28F640J3A:
-		printf ("28F640J3A\n");
-		break;
-
-	case FLASH_28F320J3A:
-		printf ("28F320J3A\n");
-		break;
-
-	case FLASH_28F256P30T:
-		printf ("FLASH_28F256P30T\n");
-		break;
-
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	udelay(100);
-
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);			/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];			/* device ID        */
-
-	switch (value) {
-
-	case (FPW) INTEL_ID_28F128J3A:
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 128;
-		info->size = 0x02000000;
-		info->start[0] = CFG_FLASH_BASE;
-		break;				/* => 32 MB     */
-
-	case (FPW) INTEL_ID_28F640J3A:
-		info->flash_id += FLASH_28F640J3A;
-		info->sector_count = 64;
-		info->size = 0x01000000;
-		info->start[0] = CFG_FLASH_BASE + 0x01000000;
-		break;				/* => 16 MB     */
-
-	case (FPW) (INTEL_ID_28F256P30T):
-		info->flash_id += FLASH_28F256L18B;
-		info->sector_count = 128;//falsch!!!
-		info->size = 0x02000000;
-		info->start[0] = CFG_FLASH_BASE;
-		debug ("Intel StrataFlash 28F256P30T device initialized\n");
-		break;			/* => 32 MB	*/
-
-	case (FPW) INTEL_ID_28F320J3A:
-		info->flash_id += FLASH_28F320J3A;
-		info->sector_count = 32;
-		info->size = 0x800000;
-		info->start[0] = CFG_FLASH_BASE + 0x01800000;
-		break;				/* => 8 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
-
-	return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-
-	case FLASH_28F128J3A:
-	case FLASH_28F640J3A:
-	case FLASH_28F320J3A:
-		for (i = 0; i < info->sector_count; ++i) {
-			info->protect[i] = intel_sector_protected(info, i);
-		}
-		break;
-	default:
-		/* no h/w protect support */
-		break;
-	}
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
-	FPWV *addr;
-	FPWV *lock_conf_addr;
-	ulong start;
-	unsigned char ret;
-
-	/*
-	 * first, wait for the WSM to be finished. The rationale for
-	 * waiting for the WSM to become idle for at most
-	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
-	 * because of: (1) erase, (2) program or (3) lock bit
-	 * configuration. So we just wait for the longest timeout of
-	 * the (1)-(3), i.e. the erase timeout.
-	 */
-
-	/* wait at least 35ns (W12) before issuing Read Status Register */
-	udelay(1);
-	addr = (FPWV *) info->start[sector];
-	*addr = (FPW) INTEL_STATUS;
-
-	start = get_timer (0);
-	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
-			*addr = (FPW) INTEL_RESET; /* restore read mode */
-			printf("WSM busy too long, can't get prot status\n");
-			return 1;
-		}
-	}
-
-	/* issue the Read Identifier Codes command */
-	*addr = (FPW) INTEL_READID;
-
-	/* wait at least 35ns (W12) before reading */
-	udelay(1);
-
-	/* Intel example code uses offset of 2 for 16 bit flash */
-	lock_conf_addr = (FPWV *) info->start[sector] + 2;
-	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
-	/* put flash back in read mode */
-	*addr = (FPW) INTEL_RESET;
-
-	return ret;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	start = get_timer (0);
-	last = start;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer(0);
-
-			*addr = (FPW) 0x00500050;	/* clear status register */
-			*addr = (FPW) 0x00200020;	/* erase setup */
-			*addr = (FPW) 0x00D000D0;	/* erase confirm */
-
-			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
-					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
-					rcode = 1;
-					break;
-				}
-			}
-
-			*addr = 0x00500050;	/* clear status register cmd.   */
-			*addr = 0x00FF00FF;	/* resest to read mode          */
-
-			printf (" done\n");
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-
-	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (0);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
-	ulong start;
-	int i;
-	int rc = 0;
-	vu_long *addr = (vu_long *)(info->start[sector]);
-	int flag = disable_interrupts();
-
-	*addr = INTEL_CLEAR;	/* Clear status register */
-	if (prot) {			/* Set sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-		*addr = INTEL_PROTECT;	/* set */
-	}
-	else {				/* Clear sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
-		*addr = INTEL_CONFIRM;	/* clear */
-	}
-
-	start = get_timer(0);
-
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
-			printf("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
-		       (uint)addr, (uint)*addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 * WARNING: code below re-locks sectors only for one bank (info).
-	 * This causes problems on boards where several banks share
-	 * the same chip, as sectors in othere banks will be unlocked
-	 * but not re-locked. It works fine on pm520 though, as there
-	 * is only one chip and one bank.
-	 */
-	if (!prot)
-	{
-		for (i = 0; i < info->sector_count; i++)
-		{
-			if (info->protect[i])
-			{
-				start = get_timer(0);
-				addr = (vu_long *)(info->start[i]);
-				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-				*addr = INTEL_PROTECT;	/* set */
-				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
-				{
-					if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT)
-					{
-						printf("Flash lock bit operation timed out\n");
-						rc = 1;
-						break;
-					}
-				}
-			}
-		}
-		/*
-		 * get the s/w sector protection status in sync with the h/w,
-		 * in case something went wrong during the re-locking.
-		 */
-		flash_sync_real_protect(info); /* resets flash to read  mode */
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	*addr = INTEL_RESET;		/* Reset to read array mode */
-
-	return rc;
-}
diff --git a/board/mcc200/flash.h b/board/mcc200/flash.h
deleted file mode 100644
index 9dc5d04ff2..0000000000
--- a/board/mcc200/flash.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-8 * MA 02111-1307 USA
- */
-
-#ifndef _FLASH_H_
-#define _FLASH_H_
-
-#ifndef CFG_NO_FLASH
-/*-----------------------------------------------------------------------
- * FLASH Info: contains chip specific data, per FLASH bank
- */
-
-typedef struct {
-	ulong	size;			/* total bank size in bytes		*/
-	ushort	sector_count;		/* number of erase units		*/
-	ulong	flash_id;		/* combined device & manufacturer code	*/
-	ulong	start[CFG_MAX_FLASH_SECT];   /* physical sector start addresses */
-	uchar	protect[CFG_MAX_FLASH_SECT]; /* sector protection status	*/
-#ifdef CFG_FLASH_CFI
-	uchar	portwidth;		/* the width of the port		*/
-	uchar	chipwidth;		/* the width of the chip		*/
-	ushort	buffer_size;		/* # of bytes in write buffer		*/
-	ulong	erase_blk_tout;		/* maximum block erase timeout		*/
-	ulong	write_tout;		/* maximum write timeout		*/
-	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
-	ushort	vendor;			/* the primary vendor id		*/
-	ushort	cmd_reset;		/* Vendor specific reset command	*/
-	ushort	interface;		/* used for x8/x16 adjustments		*/
-#endif
-} flash_info_t;
-
-/*
- * Values for the width of the port
- */
-#define FLASH_CFI_8BIT		0x01
-#define FLASH_CFI_16BIT		0x02
-#define FLASH_CFI_32BIT		0x04
-#define FLASH_CFI_64BIT		0x08
-/*
- * Values for the width of the chip
- */
-#define FLASH_CFI_BY8		0x01
-#define FLASH_CFI_BY16		0x02
-#define FLASH_CFI_BY32		0x04
-#define FLASH_CFI_BY64		0x08
-/* convert between bit value and numeric value */
-#define CFI_FLASH_SHIFT_WIDTH	3
-/*
- * Values for the flash device interface
- */
-#define FLASH_CFI_X8		0x00
-#define FLASH_CFI_X16		0x01
-#define FLASH_CFI_X8X16		0x02
-
-/* convert between bit value and numeric value */
-#define CFI_FLASH_SHIFT_WIDTH	3
-/* Prototypes */
-
-extern unsigned long flash_init (void);
-extern void flash_print_info (flash_info_t *);
-extern int flash_erase	(flash_info_t *, int, int);
-extern int flash_sect_erase (ulong addr_first, ulong addr_last);
-extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
-
-/* common/flash.c */
-extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
-extern int flash_write (uchar *, ulong, ulong);
-extern flash_info_t *addr2info (ulong);
-extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
-
-/* board/?/flash.c */
-#if defined(CFG_FLASH_PROTECTION)
-extern int flash_real_protect(flash_info_t *info, long sector, int prot);
-extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
-extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
-#endif	/* CFG_FLASH_PROTECTION */
-
-/*-----------------------------------------------------------------------
- * return codes from flash_write():
- */
-#define ERR_OK				0
-#define ERR_TIMOUT			1
-#define ERR_NOT_ERASED			2
-#define ERR_PROTECTED			4
-#define ERR_INVAL			8
-#define ERR_ALIGN			16
-#define ERR_UNKNOWN_FLASH_VENDOR	32
-#define ERR_UNKNOWN_FLASH_TYPE		64
-#define ERR_PROG_ERROR			128
-
-/*-----------------------------------------------------------------------
- * Protection Flags for flash_protect():
- */
-#define FLAG_PROTECT_SET	0x01
-#define FLAG_PROTECT_CLEAR	0x02
-
-/*-----------------------------------------------------------------------
- * Device IDs
- */
-
-#define AMD_MANUFACT	0x00010001	/* AMD	   manuf. ID in D23..D16, D7..D0 */
-#define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
-#define ATM_MANUFACT	0x001F001F	/* ATMEL */
-#define STM_MANUFACT	0x00200020	/* STM (Thomson) manuf. ID in D23.. -"- */
-#define SST_MANUFACT	0x00BF00BF	/* SST	   manuf. ID in D23..D16, D7..D0 */
-#define MT_MANUFACT	0x00890089	/* MT	   manuf. ID in D23..D16, D7..D0 */
-#define INTEL_MANUFACT	0x00890089	/* INTEL   manuf. ID in D23..D16, D7..D0 */
-#define INTEL_ALT_MANU	0x00B000B0	/* alternate INTEL namufacturer ID	*/
-#define MX_MANUFACT	0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
-#define TOSH_MANUFACT	0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
-#define MT2_MANUFACT	0x002C002C	/* alternate MICRON manufacturer ID*/
-#define EXCEL_MANUFACT	0x004A004A	/* Excel Semiconductor                  */
-
-					/* Micron Technologies (INTEL compat.)	*/
-#define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
-#define MT_ID_28F400_B	0x44714471	/* 28F400B3 ID ( 4 M, bottom boot sect) */
-
-#define AMD_ID_LV040B	0x4F		/* 29LV040B ID				*/
-					/* 4 Mbit, 512K x 8,			*/
-					/* 8 64K x 8 uniform sectors		*/
-
-#define AMD_ID_F040B	0xA4		/* 29F040B ID				*/
-					/* 4 Mbit, 512K x 8,			*/
-					/* 8 64K x 8 uniform sectors		*/
-#define STM_ID_M29W040B 0xE3		/* M29W040B ID				*/
-					/* 4 Mbit, 512K x 8,			*/
-					/* 8 64K x 8 uniform sectors		*/
-#define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
-					/* 8 Mbit, 512K x 16,			*/
-					/* 8 64K x 16 uniform sectors		*/
-#define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
-#define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
-#define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
-#define AMD_ID_LV116DB  0x4C		/* 29LV116DB   ( 2 M x 8, bottom boot sect) */
-#define AMD_ID_LV016B	0xc8		/* 29LV016 ID  ( 2 M x 8)		*/
-
-#define AMD_ID_PL160CB  0x22452245      /* 29PL160CB ID (16 M, bottom boot sect */
-
-#define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
-#define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect) */
-
-#define AMD_ID_LV033C	0xA3		/* 29LV033C ID ( 4 M x 8)		*/
-#define AMD_ID_LV065D	0x93		/* 29LV065D ID ( 8 M x 8)		*/
-
-#define AMD_ID_LV800T	0x22DA22DA	/* 29LV800T ID ( 8 M, top boot sector)	*/
-#define AMD_ID_LV800B	0x225B225B	/* 29LV800B ID ( 8 M, bottom boot sect) */
-
-#define AMD_ID_LV160T	0x22C422C4	/* 29LV160T ID (16 M, top boot sector)	*/
-#define AMD_ID_LV160B	0x22492249	/* 29LV160B ID (16 M, bottom boot sect) */
-
-#define AMD_ID_DL163T	0x22282228	/* 29DL163T ID (16 M, top boot sector)	*/
-#define AMD_ID_DL163B	0x222B222B	/* 29DL163B ID (16 M, bottom boot sect)	*/
-
-#define AMD_ID_LV320T	0x22F622F6	/* 29LV320T ID (32 M, top boot sector)	*/
-#define MX_ID_LV320T	0x22A722A7	/* 29LV320T by Macronix, AMD compatible */
-#define AMD_ID_LV320B	0x22F922F9	/* 29LV320B ID (32 M, bottom boot sect) */
-#define MX_ID_LV320B	0x22A822A8	/* 29LV320B by Macronix, AMD compatible */
-
-#define AMD_ID_DL322T	0x22552255	/* 29DL322T ID (32 M, top boot sector)	*/
-#define AMD_ID_DL322B	0x22562256	/* 29DL322B ID (32 M, bottom boot sect) */
-#define AMD_ID_DL323T	0x22502250	/* 29DL323T ID (32 M, top boot sector)	*/
-#define AMD_ID_DL323B	0x22532253	/* 29DL323B ID (32 M, bottom boot sect) */
-#define AMD_ID_DL324T	0x225C225C	/* 29DL324T ID (32 M, top boot sector)	*/
-#define AMD_ID_DL324B	0x225F225F	/* 29DL324B ID (32 M, bottom boot sect) */
-
-#define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
-#define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
-#define AMD_ID_DL640G_2	0x22022202	/* 2nd ID word for AM29DL640G  at 0x38 */
-#define AMD_ID_DL640G_3	0x22012201	/* 3rd ID word for AM29DL640G  at 0x3c */
-#define AMD_ID_LV640U_2	0x220C220C	/* 2nd ID word for AM29LV640M  at 0x38 */
-#define AMD_ID_LV640U_3	0x22012201	/* 3rd ID word for AM29LV640M  at 0x3c */
-#define AMD_ID_LV640MT_2 0x22102210	/* 2nd ID word for AM29LV640MT at 0x38 */
-#define AMD_ID_LV640MT_3 0x22012201	/* 3rd ID word for AM29LV640MT at 0x3c */
-#define AMD_ID_LV640MB_2 0x22102210	/* 2nd ID word for AM29LV640MB at 0x38 */
-#define AMD_ID_LV640MB_3 0x22002200	/* 3rd ID word for AM29LV640MB at 0x3c */
-#define AMD_ID_LV128U_2 0x22122212	/* 2nd ID word for AM29LV128M  at 0x38 */
-#define AMD_ID_LV128U_3 0x22002200	/* 3rd ID word for AM29LV128M  at 0x3c */
-#define AMD_ID_LV256U_2 0x22122212	/* 2nd ID word for AM29LV256M  at 0x38 */
-#define AMD_ID_LV256U_3 0x22012201	/* 3rd ID word for AM29LV256M  at 0x3c */
-#define AMD_ID_GL064M_2 0x22132213	/* 2nd ID word for S29GL064M-R6 */
-#define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
-
-#define AMD_ID_LV320B_2	0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
-#define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
-
-#define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
-
-#define ATM_ID_BV1614	0x000000C0	/* 49BV1614  ID */
-#define ATM_ID_BV1614A	0x000000C8	/* 49BV1614A ID */
-#define ATM_ID_BV6416	0x000000D6	/* 49BV6416  ID */
-
-#define FUJI_ID_29F800BA  0x22582258	/* MBM29F800BA ID  (8M) */
-#define FUJI_ID_29F800TA  0x22D622D6	/* MBM29F800TA ID  (8M) */
-#define FUJI_ID_29LV650UE 0x22d722d7	/* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
-
-#define SST_ID_xF200A	0x27892789	/* 39xF200A ID ( 2M = 128K x 16 )	*/
-#define SST_ID_xF400A	0x27802780	/* 39xF400A ID ( 4M = 256K x 16 )	*/
-#define SST_ID_xF800A	0x27812781	/* 39xF800A ID ( 8M = 512K x 16 )	*/
-#define SST_ID_xF160A	0x27822782	/* 39xF800A ID (16M =	1M x 16 )	*/
-#define SST_ID_xF1601	0x234B234B	/* 39xF1601 ID (16M =	1M x 16 )	*/
-#define SST_ID_xF1602	0x234A234A	/* 39xF1602 ID (16M =	1M x 16 )	*/
-#define SST_ID_xF3201	0x235B235B	/* 39xF3201 ID (32M =	2M x 16 )	*/
-#define SST_ID_xF3202	0x235A235A	/* 39xF3202 ID (32M =	2M x 16 )	*/
-#define SST_ID_xF6401	0x236B236B	/* 39xF6401 ID (64M =	4M x 16 )	*/
-#define SST_ID_xF6402	0x236A236A	/* 39xF6402 ID (64M =	4M x 16 )	*/
-#define SST_ID_xF040	0xBFD7BFD7	/* 39xF040 ID (512KB = 4Mbit x 8)	*/
-
-#define STM_ID_F040B	0xE2		/* M29F040B ID ( 4M = 512K x 8	)	*/
-					/* 8 64K x 8 uniform sectors		*/
-
-#define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16 )	*/
-#define STM_ID_29W320DT 0x22CA22CA	/* M29W320DT ID (32 M, top boot sector) */
-#define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
-#define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
-
-#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
-#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
-#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
-#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
-#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
-#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
-#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
-#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
-#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
-#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
-
-#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
-#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
-#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
-#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
-#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
-#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
-#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
-#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
-
-#define INTEL_ID_28F128J3   0x89188918	/*  16M = 8M x 16 x 128 */
-#define INTEL_ID_28F320J5   0x00140014	/*  32M = 128K x  32	*/
-#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64	*/
-#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
-#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
-#define INTEL_ID_28F256L18  0x88108810	/*  32M = 128K x 255	*/
-#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
-#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
-#define INTEL_ID_28F256L18B 0x88108810	/* 256M =  32k x 4   + 128K x 255 */
-#define INTEL_ID_28F256P30B 0x891C891C	/* 256M =  32k x 4   + 128K x 255 */
-#define INTEL_ID_28F256P30T 0x89198919	/* 256M =  128K x 255 + 32k x 4 */
-#define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
-#define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
-#define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
-
-#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
-#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
-
-/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
-#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
-#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
-#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
-					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
-
-#define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
-#define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
-
-/*-----------------------------------------------------------------------
- * Internal FLASH identification codes
- *
- * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
- */
-
-#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B		*/
-					/* Bright Micro BM29F040		*/
-					/* Fujitsu MBM29F040A			*/
-					/* STM M29W040B				*/
-					/* SGS Thomson M29F040B			*/
-					/* 8 64K x 8 uniform sectors		*/
-#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
-#define FLASH_AM400B	0x0003
-#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
-#define FLASH_AM800B	0x0005
-#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
-#define FLASH_AM116DB	0x0027		/* AMD AM29LV116DB (2Mx8bit) */
-#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
-#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit ) */
-#define FLASH_AM160B	0x0007
-#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
-#define FLASH_AM320B	0x0009
-
-#define FLASH_AM080	0x000A		/* AMD Am29F080B			*/
-					/* 16 64K x 8 uniform sectors		*/
-
-#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
-#define FLASH_AMDL322B	0x0011
-#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
-#define FLASH_AMDL323B	0x0013
-#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
-#define FLASH_AMDL324B	0x0015
-
-#define FLASH_AMDLV033C	0x0018
-#define FLASH_AMDLV065D	0x001A
-
-#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
-#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
-#define FLASH_AMDL640MB	0x0019		/* AMD AM29LV640MB (64M, bottom boot sect)*/
-#define FLASH_AMDL640MT	0x001A		/* AMD AM29LV640MT (64M, top boot sect) */
-
-#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
-#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
-#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
-#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST320	0x0048		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST640	0x004A		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
-#define FLASH_SST040	0x000E		/* SST 39xF040 ID (512KB = 4Mbit x 8 )	*/
-
-#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
-#define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
-#define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
-#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
-#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
-#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
-
-#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
-#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
-
-#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
-#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
-#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
-#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
-#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
-#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
-#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
-#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
-
-#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
-#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
-#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
-#define FLASH_AM29F800B 0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
-#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
-#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
-#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
-#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
-#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
-#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
-#define FLASH_28F160F3B 0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
-
-#define FLASH_28F640J5	0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
-
-#define FLASH_28F800C3T 0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
-#define FLASH_28F800C3B 0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
-#define FLASH_28F160C3T 0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
-#define FLASH_28F160C3B 0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
-#define FLASH_28F320C3T 0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
-#define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
-#define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
-#define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M    ( 32M = 2M x 16 )	*/
-#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M    ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
-#define FLASH_AMLV320B  0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
-#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
-#define FLASH_AMLV256U	0x00AA		/* AMD 29LV256M	   ( 256M = 16M x 16 )	*/
-#define FLASH_MXLV320B  0x00AB		/* MX  29LV320MB   ( 32M = 2M x 16 )	*/
-#define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
-#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T ( 32M = 128K x 255 + 32k x 4) */
-#define FLASH_28F256L18B 0x00B1		/* Intel 28F256L18B ( 32M = 32k x 4 + 128K x 255)  */
-#define FLASH_28F256P30B 0x001C		/* Intel 28F256P30B ( 32M = 32k x 4 + 128K x 255)  */
-#define FLASH_28F256P30T 0x0019		/* Intel 28F256P30T ( 128K x 255 + 32M = 32k x 4 + */
-#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
-#define FLASH_AMDL163B	0x00B3
-#define FLASH_28F64K3	0x00B4		/* Intel 28F64K3   (  64M)		*/
-#define FLASH_28F128K3	0x00B6		/* Intel 28F128K3  ( 128M = 8M x 16 )   */
-#define FLASH_28F256K3	0x00B8		/* Intel 28F256K3  ( 256M = 16M x 16 )  */
-
-#define FLASH_28F320J3A 0x00C0		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
-#define FLASH_28F640J3A 0x00C2		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
-#define FLASH_28F128J3A 0x00C4		/* INTEL 28F128J3A (128M = 128K x 128)	*/
-
-#define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
-#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC 			*/
-#define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
-
-#define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
-
-
-/* manufacturer offsets
- */
-#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
-#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
-#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
-#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
-#define FLASH_MAN_STM	0x00040000
-#define FLASH_MAN_TOSH	0x00050000	/* Toshiba				*/
-#define FLASH_MAN_EXCEL 0x00060000      /* Excel Semiconductor                  */
-#define FLASH_MAN_SST	0x00100000
-#define FLASH_MAN_INTEL 0x00300000
-#define FLASH_MAN_MT	0x00400000
-#define FLASH_MAN_SHARP 0x00500000
-
-
-#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
-#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
-
-#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
-					/* with AMD, Fujitsu and SST		*/
-					/* (JEDEC standard commands ?)		*/
-
-#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
-
-/*-----------------------------------------------------------------------
- * Timeout constants:
- *
- * We can't find any specifications for maximum chip erase times,
- * so these values are guestimates.
- */
-#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
-#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
-
-#endif /* !CFG_NO_FLASH */
-
-#endif /* _FLASH_H_ */
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index d7f95c83d0..47073907e1 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -36,6 +36,8 @@
 #include "mt48lc8m32b2-6-7.h"
 #endif
 
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
 //###CHD: wenn RAMBOOT gehen wuerde, ....
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
@@ -244,46 +246,56 @@ int checkboard (void)
 	return 0;
 }
 
-void flash_preinit(void)
+int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
+	 * Adjust flash start and offset to detected values
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong start, ulong size)
-{
-#if defined(CONFIG_BOOT_ROM)
-	/* adjust mapping */
-	*(vu_long *)MPC5XXX_CS1_START =
-			START_REG(start);
-	*(vu_long *)MPC5XXX_CS1_STOP =
-			STOP_REG(start, size);
-#else
-	/* adjust mapping */
-	*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(start);
-	*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(start, size);
-#endif
-}
-
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
 
-extern flash_info_t flash_info[];	/* info for FLASH chips */
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
+		/* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(gd->bd->bi_flashstart);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       gd->bd->bi_flashstart, 0xffffffff,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR_REDUND,
+			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+	}
 
-int misc_init_r (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	/* adjust flash start */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
 	return (0);
 }