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| author | Wolfgang Denk <wd@denx.de> | 2008-09-13 02:23:05 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-09-13 02:23:05 +0200 |
| commit | f12e4549b6fb01cd2654348af95a3c7a6ac161e7 (patch) | |
| tree | 725ff6a5ad3b615b0e94c42bc2834a9e70f18d8e /board/samsung | |
| parent | 0c32565f536609d78feef35c88bbc39d3ac53a73 (diff) | |
| download | u-boot-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.tar.gz u-boot-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.tar.xz u-boot-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.zip | |
Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/samsung')
| -rw-r--r-- | board/samsung/smdk6400/lowlevel_init.S | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 034c810f7b..e0119a771c 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -2,7 +2,7 @@ * Memory Setup stuff - taken from blob memsetup.S * * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * * Modified for the Samsung SMDK2410 by * (C) Copyright 2002 @@ -73,8 +73,8 @@ lowlevel_init: ldr r1, [r0] str r1, [r0] - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 + ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 + ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 /* Disable all interrupts (VIC0 and VIC1) */ mvn r3, #0x0 @@ -107,11 +107,11 @@ lowlevel_init: bl mem_ctrl_asm_init /* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset + ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) + ldr r1, [r0] + bic r1, r1, #0xfffffff7 + cmp r1, #0x8 + beq wakeup_reset 1: mov lr, r12 @@ -124,10 +124,10 @@ wakeup_reset: ldr r1, [r0] str r1, [r0] - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] + /* LED test */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x3000 + str r1, [r0, #GPNDAT_OFFSET] /* Load return address and jump to kernel */ ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) @@ -201,7 +201,7 @@ wait_for_async: str r1, [r0, #MPLL_LOCK_OFFSET] /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] + ldr r1, [r0, #CLK_DIV0_OFFSET] bic r1, r1, #0x30000 bic r1, r1, #0xff00 bic r1, r1, #0xff @@ -252,7 +252,7 @@ uart_asm_init: /* set GPIO to enable UART */ ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] + str r1, [r0, #GPACON_OFFSET] mov pc, lr #endif @@ -265,11 +265,11 @@ nand_asm_init: ldr r1, [r0, #NFCONF_OFFSET] orr r1, r1, #0x70 orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] + str r1, [r0, #NFCONF_OFFSET] ldr r1, [r0, #NFCONT_OFFSET] orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] + str r1, [r0, #NFCONT_OFFSET] mov pc, lr #endif |