diff options
| author | Stefan Roese <sr@denx.de> | 2010-04-14 13:57:18 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-04-19 15:29:03 +0200 |
| commit | cf6eb6da433179674571f9370566b1ec8989a41a (patch) | |
| tree | fc0ad7161d7146154026fa789a97dd2c047c61a7 /board/netstal | |
| parent | 2a72e9ed18d2164eb7fe569119342eb631b568da (diff) | |
| download | u-boot-cf6eb6da433179674571f9370566b1ec8989a41a.tar.gz u-boot-cf6eb6da433179674571f9370566b1ec8989a41a.tar.xz u-boot-cf6eb6da433179674571f9370566b1ec8989a41a.zip | |
ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/netstal')
| -rw-r--r-- | board/netstal/hcu5/init.S | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index 05b5e389c2..45e63dd3d4 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -40,13 +40,13 @@ tlbtab: tlbtab_start /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /* TLB#2: TLB-entry for EBC */ - tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG) /* * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be @@ -54,7 +54,7 @@ tlbtab: * to enable SA_I */ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1, - AC_R|AC_W|AC_X|SA_G) + AC_RWX | SA_G) /* * TLB entries for SDRAM are not needed on this platform. @@ -64,43 +64,43 @@ tlbtab: /* TLB#4: */ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB#5: */ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB#6: */ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB-entry for Internal Registers & OCM */ /* TLB#7: */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /*TLB-entry PCI registers*/ /* TLB#8: */ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) /* TLB-entry for peripherals */ /* TLB#9: */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) /* CAN */ /* TLB#10: */ - tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG ) /* TLB#11: CPLD and IMC-Standard 32 MB */ - tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG ) /* TLB#12: */ tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /* IMC-Fast 32 MB */ /* TLB#13: */ - tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG ) /* TLB#14: */ tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) tlbtab_end |