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| author | Wolfgang Denk <wd@denx.de> | 2008-03-13 14:32:03 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-03-13 14:32:03 +0100 |
| commit | c6dc21c84de0f159a1752c5ebd33cff843f63609 (patch) | |
| tree | 3f794473f6093521eb5a3b8f09f25849df69515c /board/hmi1001 | |
| parent | 90f13dce7a7a9a84d5730576c9a24d0dbb07cb3a (diff) | |
| download | u-boot-c6dc21c84de0f159a1752c5ebd33cff843f63609.tar.gz u-boot-c6dc21c84de0f159a1752c5ebd33cff843f63609.tar.xz u-boot-c6dc21c84de0f159a1752c5ebd33cff843f63609.zip | |
HMI1001: add support for MPC5200 Rev. B processors.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/hmi1001')
| -rw-r--r-- | board/hmi1001/hmi1001.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 9fa0e747b9..3ecb74a0c8 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -147,6 +147,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + /* return dramsize + dramsize2; */ return dramsize; } |