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| author | John Rigby <jrigby@freescale.com> | 2008-08-28 13:17:07 -0600 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-08-28 13:36:43 -0600 |
| commit | 8a490422bed685c9491274ec997f62061d88620b (patch) | |
| tree | d5d8b3471cacd352bf419431c619b742f5aa8589 /board/ads5121 | |
| parent | 33aa4eac66b71c797bbc13b3afe432a2132947d4 (diff) | |
| download | u-boot-8a490422bed685c9491274ec997f62061d88620b.tar.gz u-boot-8a490422bed685c9491274ec997f62061d88620b.tar.xz u-boot-8a490422bed685c9491274ec997f62061d88620b.zip | |
ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.
The default is to assert CS together with ALE. The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
The default is wrong for the NOR flash and CPLD on the ADS5121.
This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'board/ads5121')
| -rw-r--r-- | board/ads5121/ads5121.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index ba3d7d2a0d..deaa292b9a 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -25,6 +25,7 @@ #include <mpc512x.h> #include <asm/bitops.h> #include <command.h> +#include <asm/processor.h> #include <fdt_support.h> #ifdef CONFIG_MISC_INIT_R #include <i2c.h> @@ -92,6 +93,9 @@ int board_early_init_f (void) * Configure Flash Speed */ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; + if (SVR_MJREV (im->sysconf.spridr) >= 2) { + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING; + } /* * Enable clocks */ |