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| author | David Jander <david@protonic.nl> | 2011-07-14 03:58:57 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2011-07-18 14:41:48 +0200 |
| commit | 6e25b6ce5d26c3c238c1dd947ef33dc38be003d8 (patch) | |
| tree | 58507e53f842f7df22f72ee53bb7064a8979730d /arch | |
| parent | 9f008bb47dd696d9e539fea2f045ae01b0c78a25 (diff) | |
| download | u-boot-6e25b6ce5d26c3c238c1dd947ef33dc38be003d8.tar.gz u-boot-6e25b6ce5d26c3c238c1dd947ef33dc38be003d8.tar.xz u-boot-6e25b6ce5d26c3c238c1dd947ef33dc38be003d8.zip | |
ARM: MX5: Fix broken leftover TO-2 errata workaround
This check was broken. r3 does not contain the silicon revision anymore, so
we need to reload it. Also, this errata only applies to i.MX51.
Signed-off-by: David Jander <david@protonic.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2345..94de9f1d61 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */ |