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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-02-18 05:40:54 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-28 22:09:24 -0500 |
| commit | 66412c6371cfd6e056679abedea7d6fafe6a0422 (patch) | |
| tree | 261d51ec7e7c2a22f0bd5db5fca43d4fc9910aeb /README | |
| parent | d90fdba6ca0b08c77cced6e914609e3696dd5909 (diff) | |
| download | u-boot-66412c6371cfd6e056679abedea7d6fafe6a0422.tar.gz u-boot-66412c6371cfd6e056679abedea7d6fafe6a0422.tar.xz u-boot-66412c6371cfd6e056679abedea7d6fafe6a0422.zip | |
powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -356,6 +356,13 @@ The following options need to be configured: Define this option if you want to enable the ICache only when Code runs from RAM. +- 85xx CPU Options: + CONFIG_SYS_FSL_TBCLK_DIV + + Defines the core time base clock divider ratio compared to the + system clock. On most PQ3 devices this is 8, on newer QorIQ + devices it can be 16 or 32. The ratio varies from SoC to Soc. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |