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| author | Wolfgang Denk <wd@denx.de> | 2011-04-30 22:45:55 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-04-30 22:45:55 +0200 |
| commit | aeabdeb7a33c9cff9ae0cd804521d0d691a7c341 (patch) | |
| tree | 2979428a02f5eebf256d18a3fb5839e063c3354a /README | |
| parent | f3c615b8abc098f5222b061b81c75f1363ff4d32 (diff) | |
| parent | a2879634c430df3d308f4a3badb37cddca0328f5 (diff) | |
| download | u-boot-aeabdeb7a33c9cff9ae0cd804521d0d691a7c341.tar.gz u-boot-aeabdeb7a33c9cff9ae0cd804521d0d691a7c341.tar.xz u-boot-aeabdeb7a33c9cff9ae0cd804521d0d691a7c341.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'README')
| -rw-r--r-- | README | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -356,6 +356,13 @@ The following options need to be configured: Define this option if you want to enable the ICache only when Code runs from RAM. +- 85xx CPU Options: + CONFIG_SYS_FSL_TBCLK_DIV + + Defines the core time base clock divider ratio compared to the + system clock. On most PQ3 devices this is 8, on newer QorIQ + devices it can be 16 or 32. The ratio varies from SoC to Soc. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |