Add PCI support for MPC8568MDS board

This patch is against u-boot-mpc85xx.git of www.denx.com

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>

4 files changed, 98 insertions, 38 deletions

diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S
index 0d879821e3..972a7d4299 100644
--- a/board/mpc8568mds/init.S
+++ b/board/mpc8568mds/init.S
@@ -143,54 +143,42 @@ tlb1_entry:
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLBe 2:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM
+	 * TLBe 2:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000 	512M	PCIe MEM
 	 */
 	.long TLB1_MAS0(1, 2, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLBe 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCIe Mem
-	 */
-	.long TLB1_MAS0(1, 3, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-	/*
-	 * TLBe 4:	Reserved for future usage
-	 */
-
-	/*
-	 * TLBe 5:	64M	Non-cacheable, guarded
+	 * TLBe 3:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	8M	PCI1 IO
 	 * 0xe280_0000	8M	PCIe IO
 	 */
-	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS0(1, 3, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLBe 6:	64M	Cacheable, non-guarded
+	 * TLBe 4:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS0(1, 4, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLBe 7:	256K	Non-cacheable, guarded
+	 * TLBe 5:	256K	Non-cacheable, guarded
 	 * 0xf8000000	32K BCSR
 	 * 0xf8008000	32K PIB (CS4)
 	 * 0xf8010000	32K PIB (CS5)
 	 */
-	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS0(1, 5, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
@@ -202,12 +190,12 @@ tlb1_entry:
  * LAW(Local Access Window) configuration:
  *
  *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
- *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                256MB
- *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                256MB
- *5)   0xc000_0000   0xdfff_ffff     SRIO                    256MB
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
  *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
  *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
- *4)   0xe280_0000   0xe2ff_ffff     PCIe I/0                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
  *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
  *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
  *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
@@ -226,20 +214,20 @@ tlb1_entry:
 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
 #define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 
 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 /* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c
index 9c7960d47e..23caaec72f 100644
--- a/board/mpc8568mds/mpc8568mds.c
+++ b/board/mpc8568mds/mpc8568mds.c
@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <spd.h>
+#include <i2c.h>
 
 #include "bcsr.h"
 
@@ -50,6 +51,15 @@ int board_early_init_f (void)
 	enable_8568mds_duart();
 	enable_8568mds_flash_write();
 
+#ifdef CFG_I2C2_OFFSET
+	/* Enable I2C2_SCL and I2C2_SDA */
+	volatile struct par_io *port_c;
+	port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+	port_c->cpdir2 |= 0x0f000000;
+	port_c->cppar2 &= ~0x0f000000;
+	port_c->cppar2 |= 0x0a000000;
+#endif
+
 	return 0;
 }
 
@@ -269,20 +279,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
 #endif
 
 static struct pci_controller hose[] = {
+	{
 #ifndef CONFIG_PCI_PNP
-	{ config_table: pci_mpc8568mds_config_table,},
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
+	config_table: pci_mpc8568mds_config_table,
 #endif
+	}
 };
 
 #endif	/* CONFIG_PCI */
 
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+	u8 val8, orig_i2c_bus;
+	/*
+	 * Assign PIB PMC2/3 to PCI bus
+	 */
+
+	/*switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0x00;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+	val8 = 0xf9;
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0x00;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	asm("eieio");
+}
+
 void
 pci_init_board(void)
 {
 #ifdef CONFIG_PCI
+	pib_init();
 	pci_mpc85xx_init(&hose);
 #endif
 }
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 77f885daa6..3d4816f3a9 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1522,6 +1522,17 @@ typedef struct ccsr_rio {
 	char	res58[60176];
 } ccsr_rio_t;
 
+/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
+typedef struct par_io {
+	uint	cpodr;		/* 0x100 */
+	uint	cpdat;		/* 0x104 */
+	uint	cpdir1;		/* 0x108 */
+	uint	cpdir2;		/* 0x10c */
+	uint	cppar1;		/* 0x110 */
+	uint	cppar2;		/* 0x114 */
+	char	res[8];
+}par_io_t;
+
 /*
  * Global Utilities Register Block(0xe_0000-0xf_ffff)
  */
@@ -1585,7 +1596,13 @@ typedef struct ccsr_gur {
 	uint	svr;		/* 0xe00a4 - System version register */
 	char	res10a[8];
 	uint	rstcr;		/* 0xe00b0 - Reset control register */
+#ifdef MPC8568
+	char	res10b[76];
+	par_io_t qe_par_io[7];  /* 0xe0100 - 0xe01bf */
+	char	res10c[3136];
+#else
 	char	res10b[3404];
+#endif
 	uint	clkocr;		/* 0xe0e00 - Clock out select register */
 	char	res11[12];
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index eef168c252..5bc953adc4 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC8568		1	/* MPC8568 specific */
 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
 
-#undef CONFIG_PCI
+#define CONFIG_PCI
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
@@ -306,11 +306,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_EEPROM_ADDR	0x52
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES        {0,0x69}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
 
 /*
  * General PCI
@@ -318,7 +321,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CFG_PCI1_IO_BASE	0x00000000
 #define CFG_PCI1_IO_PHYS	0xe2000000
 #define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */