* Patches by Travis Sawyer, 12 Mar 2004:

  - Fix Gigabit Ethernet support for 440GX
  - Add Gigabit Ethernet Support to MII PHY utilities

* Patch by Brad Kemp, 12 Mar 2004:
  Fixes for drivers/cfi_flash.c:
  - Better support for x8/x16 implementations
  - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
  - Added defines for AMD command and address constants

* Patch by Leon Kukovec, 12 Mar 2004:
  Fix get_dentfromdir() to correctly handle deleted dentries

* Patch by George G. Davis, 11 Mar 2004:
  Remove hard coded network settings in TI OMAP1610 H2
  default board config

* Patch by George G. Davis, 11 Mar 2004:
  add support for ADS GraphicsClient+ board.

17 files changed, 1076 insertions, 108 deletions

diff --git a/CHANGELOG b/CHANGELOG
index e43806969a..fb6cebb548 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,26 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
 
+* Patches by Travis Sawyer, 12 Mar 2004:
+  - Fix Gigabit Ethernet support for 440GX
+  - Add Gigabit Ethernet Support to MII PHY utilities
+
+* Patch by Brad Kemp, 12 Mar 2004:
+  Fixes for drivers/cfi_flash.c:
+  - Better support for x8/x16 implementations
+  - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
+  - Added defines for AMD command and address constants
+
+* Patch by Leon Kukovec, 12 Mar 2004:
+  Fix get_dentfromdir() to correctly handle deleted dentries
+  
+* Patch by George G. Davis, 11 Mar 2004:
+  Remove hard coded network settings in TI OMAP1610 H2
+  default board config
+
+* Patch by George G. Davis, 11 Mar 2004:
+  add support for ADS GraphicsClient+ board.
+
 * Patch by  Pierre Aubert, 11 Mar 2004:
   - add bitmap command and splash screen support in cfb console
   - add [optional] origin in the bitmap display command
diff --git a/MAKEALL b/MAKEALL
index 797c6c6412..e058ad0e34 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -122,7 +122,7 @@ LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="dnp1110 lart shannon"
+LIST_SA="dnp1110 gcplus lart shannon"
 
 #########################################################################
 ## ARM7 Systems
diff --git a/Makefile b/Makefile
index e7505fb418..1f13c77354 100644
--- a/Makefile
+++ b/Makefile
@@ -908,12 +908,15 @@ ZUMA_config:	unconfig
 at91rm9200dk_config	:	unconfig
 	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
 
-lart_config	:	unconfig
-	@./mkconfig $(@:_config=) arm sa1100 lart
-
 dnp1110_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 dnp1110
 
+gcplus_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 gcplus
+
+lart_config	:	unconfig
+	@./mkconfig $(@:_config=) arm sa1100 lart
+
 shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 
diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile
new file mode 100644
index 0000000000..d0f7d1cffa
--- /dev/null
+++ b/board/gcplus/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2003 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= gcplus.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/gcplus/config.mk b/board/gcplus/config.mk
new file mode 100644
index 0000000000..57326b8547
--- /dev/null
+++ b/board/gcplus/config.mk
@@ -0,0 +1,13 @@
+#
+# ADS GCPlus board with SA1110 cpu
+#
+# The ADS GCPlus has 2 banks of 16 MiB SDRAM
+#
+# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM
+# at c020'0000 and then move ourself to c8f0'0000. Basically, just
+# install the U-Boot binary as you would the Linux zImage and then
+# reap the benfits of more convenient Linux development cycles, i.e.
+# bootp;tftp;bootm, repeat, etc.,.
+#
+
+TEXT_BASE = 0xc8f00000
diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c
new file mode 100644
index 0000000000..5455656d12
--- /dev/null
+++ b/board/gcplus/flash.c
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)				__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)				__swab32(x)
+#endif
+
+#define FPW				FLASH_PORT_WIDTH
+#define FPWV				FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPW * addr, flash_info_t * info);
+static int write_data(flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+void inline spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init(void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf("28F128J3A\n");
+		break;
+	case FLASH_28F640J5:
+		printf("28F640J5\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong
+flash_get_size(FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb();
+	value = addr[1];	/* device ID            */
+	switch (value) {
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+	case (FPW) INTEL_ID_28F640J5:
+		info->flash_id += FLASH_28F640J5;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf(" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data(flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c
new file mode 100644
index 0000000000..06b6098a3c
--- /dev/null
+++ b/board/gcplus/gcplus.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = 29;	/* ADS GraphicsClientPlus Board */
+
+	gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
+
+	/* Most of the ADS GCPlus I/O is connected to Static nCS2.
+	 * So I'm brute forcing nCS2 timiming here for worst case.
+	 */
+	MSC1 &= ~0xFFFF;
+	MSC1 |= 0x8649;
+
+	/* Nothing is connected to Static nCS4 or nCS5. But I'm using
+	 * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high
+	 * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm
+	 * paranoid and lack decent tools to alleviate my fear. I sure
+	 * do wish I had a logic analyzer. : (
+	 */
+
+	MSC2 =  0xfff9fff9;
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
diff --git a/board/gcplus/memsetup.S b/board/gcplus/memsetup.S
new file mode 100644
index 0000000000..02f5685824
--- /dev/null
+++ b/board/gcplus/memsetup.S
@@ -0,0 +1,77 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+	.globl	memsetup
+memsetup:
+	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
+	 * However the darn thing leaves the MMU enabled before handing control
+	 * over to us. So we need to disable the MMU and we use memsetup
+	 * to do it.
+	 */
+
+@ The following code segment was borrowed with gratitude from:
+@	linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
+
+	@ Data cache might be active.
+	@ Be sure to flush kernel binary out of the cache,
+	@ whatever state it is, before it is turned off.
+	@ This is done by fetching through currently executed
+	@ memory to be sure we hit the same cache.
+	bic	r2, pc, #0x1f
+	add	r3, r2, #0x4000		@ 16 kb is quite enough...
+1:	ldr	r0, [r2], #32
+	teq	r2, r3
+	bne	1b
+	mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+	mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+	@ disabling MMU and caches
+	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+	bic	r0, r0, #0x0d		@ clear WB, DC, MMU
+	bic	r0, r0, #0x1000		@ clear Icache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	b	2f
+2:
+	nop
+	nop
+	nop
+	nop
+	nop
+
+
+	mov	pc, lr
diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds
new file mode 100644
index 0000000000..f625b48c3a
--- /dev/null
+++ b/board/gcplus/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index abbdaa2be3..cbad7dbb32 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -103,7 +103,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 					"Rev = 0x%02X, "
 					"%3dbaseT, %s\n",
 					j, oui, model, rev,
-					miiphy_speed (j) == _100BASET ? 100 : 10,
+					miiphy_speed (j),
 					miiphy_duplex (j) == FULL ? "FDX" : "HDX");
 			}
 		}
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 03964da81f..b45ab06157 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -135,11 +135,20 @@ int miiphy_speed (unsigned char addr)
 {
 	unsigned short reg;
 
+	if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+		printf ("PHY 1000BT Status read failed\n");
+	} else {
+		if (reg != 0xFFFF) {
+			if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
+				return (_1000BASET);
+			}
+		}
+	}
+
 	if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
 		printf ("PHY speed1 read failed, assuming 10bT\n");
 		return (_10BASET);
 	}
-
 	if ((reg & PHY_ANLPAR_100) != 0) {
 		return (_100BASET);
 	} else {
@@ -156,6 +165,20 @@ int miiphy_duplex (unsigned char addr)
 {
 	unsigned short reg;
 
+
+	if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+		printf ("PHY 1000BT Status read failed\n");
+	} else {
+		if ( (reg != 0xFFFF) &&
+		     (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
+			if ((reg & PHY_1000BTSR_1000FD) !=0) {
+				return (FULL);
+			} else {
+				return (HALF);
+			}
+		}
+	}
+
 	if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
 		printf ("PHY duplex read failed, assuming half duplex\n");
 		return (HALF);
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
index ba7418a971..91cf240ac6 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -175,6 +175,100 @@ static void ppc_440x_eth_halt (struct eth_device *dev)
 extern int phy_setup_aneg (unsigned char addr);
 extern int miiphy_reset (unsigned char addr);
 
+#if defined (CONFIG_440_GX)
+int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long pfc1;
+	unsigned long zmiifer;
+	unsigned long rmiifer;
+
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
+
+	zmiifer = 0;
+	rmiifer = 0;
+
+	switch (pfc1) {
+	case 1:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 2:
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 3:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 4:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 5:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 6:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 0:
+	default:
+		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+
+	out32 (ZMII_FER, zmiifer);
+	out32 (RGMII_FER, rmiifer);
+
+	return ((int)pfc1);
+
+}
+#endif
+
 static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 {
 	int i;
@@ -187,11 +281,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	unsigned short devnum;
 	unsigned short reg_short;
 	sys_info_t sysinfo;
-#if defined (CONFIG_440_GX)
-	unsigned long pfc1;
-	unsigned long zmiifer;
-	unsigned long rmiifer;
-#endif
+	int ethgroup;
 
 	EMAC_440GX_HW_PST hw_p = dev->priv;
 
@@ -269,66 +359,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	udelay (100);
 
 #if defined(CONFIG_440_GX)
-	mfsdr(sdr_pfc1, pfc1);
-	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
-	switch (pfc1) {
-	case 1:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	case 2:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	case 3:
-		if (devnum == 0) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = 0x0;
-		} else if (devnum == 2) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		} else { /* invalid case */
-			zmiifer = 0x0;
-			rmiifer = 0x0;
-		}
-		break;
-	case 4:
-		if ((devnum == 0) || (devnum == 1)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else { /* ((devnum == 2) || (devnum == 3)) */
-			zmiifer = (ZMII_FER_MDI/* | ZMII_FER_RMII */) << ZMII_FER_V (devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V (devnum);
-		}
-		break;
-	case 5:
-		if ((devnum == 0) || (devnum == 1) || (devnum == 2)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		}
-		break;
-	case 6:
-		if ((devnum == 0) || (devnum == 1)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		}
-		break;
-	case 0:
-	default:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_MII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	}
-
-	out32 (ZMII_FER, zmiifer);
-	out32 (RGMII_FER, rmiifer);
+	ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
 #else
 	if ((devnum == 0) || (devnum == 1)) {
 		out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
@@ -338,6 +369,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
 				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
 	}
+
 #endif
 	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
 	__asm__ volatile ("eieio");
@@ -397,16 +429,17 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	/* Reset the phy */
 	miiphy_reset (reg);
 
+#if defined(CONFIG_440_GX)
 #if defined(CONFIG_CIS8201_PHY)
 	/*
 	 * Cicada 8201 PHY needs to have an extended register whacked
 	 * for RGMII mode.
 	 */
-	if ( ((devnum == 2) || (devnum ==3)) && (4 == pfc1) ) {
+	if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
 		miiphy_write (reg, 23, 0x1200);
 	}
 #endif
-
+#endif
 	/* Start/Restart autonegotiation */
 	phy_setup_aneg (reg);
 	udelay (1000);
@@ -451,7 +484,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 
 	/* Set ZMII/RGMII speed according to the phy link speed */
 	reg = in32 (ZMII_SSR);
-	if (speed == 100)
+	if ( (speed == 100) || (speed == 1000) )
 		out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
 	else
 		out32 (ZMII_SSR,
@@ -619,8 +652,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
 
 	/* set speed */
-	/* TBS: do 1GbE */
-	if (speed == _100BASET)
+	if (speed == _1000BASET)
+		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
+	else if (speed == _100BASET)
 		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
 	else
 		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 7a7575b268..df6cb73fa3 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -101,9 +101,14 @@
 #define AMD_CMD_WRITE			0xA0
 #define AMD_CMD_ERASE_START		0x80
 #define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
 
 #define AMD_STATUS_TOGGLE		0x40
 #define AMD_STATUS_ERROR		0x20
+#define AMD_ADDR_ERASE_START		0x555
+#define AMD_ADDR_START			0x555
+#define AMD_ADDR_ACK			0x2AA
 
 #define FLASH_OFFSET_CFI		0x55
 #define FLASH_OFFSET_CFI_RESP		0x10
@@ -377,7 +382,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 			case CFI_CMDSET_AMD_STANDARD:
 			case CFI_CMDSET_AMD_EXTENDED:
 				flash_unlock_seq (info, sect);
-				flash_write_cmd (info, sect, 0x555, AMD_CMD_ERASE_START);
+				flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
+							AMD_CMD_ERASE_START);
 				flash_unlock_seq (info, sect);
 				flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
 				break;
@@ -479,24 +485,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 #ifdef CFG_FLASH_USE_BUFFER_WRITE
 	int buffered_size;
 #endif
-	int x8mode = 0;
-
-	/* special handling of 16 bit devices in 8 bit mode */
-	if ((info->interface == FLASH_CFI_X8X16)
-	    && (info->chipwidth == FLASH_CFI_BY8)) {
-		switch (info->vendor) {
-		case CFI_CMDSET_INTEL_STANDARD:
-		case CFI_CMDSET_INTEL_EXTENDED:
-			x8mode = info->portwidth;
-			info->portwidth >>= 1;	/* XXX - Need to test on x9/x16 in parallel. */
-			/*info->portwidth = FLASH_CFI_8BIT; */ /* XXX - Need to test on x9/x16 in parallel. */
-			break;
-		case CFI_CMDSET_AMD_STANDARD:
-		case CFI_CMDSET_AMD_EXTENDED:
-		default:
-			break;
-		}
-	}
 	/* get lower aligned address */
 	/* get lower aligned address */
 	wp = (addr & ~(info->portwidth - 1));
@@ -560,10 +548,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 		flash_add_byte (info, &cword, (*(uchar *) cp));
 	}
 
-	/* special handling of 16 bit devices in 8 bit mode */
-	if (x8mode) {
-		info->portwidth = x8mode;;
-	}
 	return flash_write_cfiword (info, wp, cword);
 }
 
@@ -847,8 +831,8 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
 
 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
 {
-	flash_write_cmd (info, sect, 0x555, 0xAA);
-	flash_write_cmd (info, sect, 0x2AA, 0x55);
+	flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
+	flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
 }
 
 /*-----------------------------------------------------------------------
@@ -1078,6 +1062,9 @@ static ulong flash_get_size (ulong base, int banknum)
 		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
 		info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
 		info->flash_id = FLASH_MAN_CFI;
+		if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
+			info->portwidth >>= 1;	/* XXX - Need to test on x8/x16 in parallel. */
+		}
 	}
 
 	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
@@ -1131,7 +1118,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 	case CFI_CMDSET_AMD_EXTENDED:
 	case CFI_CMDSET_AMD_STANDARD:
 		flash_unlock_seq (info, 0);
-		flash_write_cmd (info, 0, 0x555, AMD_CMD_WRITE);
+		flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
 		break;
 	}
 
@@ -1182,6 +1169,10 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 	int retcode;
 	volatile cfiptr_t src;
 	volatile cfiptr_t dst;
+	/* buffered writes in the AMD chip set is not supported yet */
+	if((info->vendor ==  CFI_CMDSET_AMD_STANDARD) ||
+		(info->vendor == CFI_CMDSET_AMD_EXTENDED))
+		return ERR_INVAL;
 
 	src.cp = cp;
 	dst.cp = (uchar *) dest;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 6f1e57cbc9..6025ad5c30 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -535,6 +535,10 @@ static dir_entry *get_dentfromdir (fsdata * mydata, int startsect,
 	    char s_name[14], l_name[256];
 
 	    l_name[0] = '\0';
+	    if (dentptr->name[0] == DELETED_FLAG) {
+		    dentptr++;
+		    continue;
+	    }
 	    if ((dentptr->attr & ATTR_VOLUME)) {
 #ifdef CONFIG_SUPPORT_VFAT
 		if ((dentptr->attr & ATTR_VFAT) &&
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
new file mode 100644
index 0000000000..eefb8a6ece
--- /dev/null
+++ b/include/configs/gcplus.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * Configuation settings for the ADS GraphicsClient+ board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef	 DEBUG
+
+/*
+ * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
+ * We don't actually init RAM in this case since we're using U-Boot as
+ * an secondary boot loader during Linux kernel development and testing,
+ * e.g. bootp/tftp download of the kernel is a far more convenient
+ * when testing new kernels on this target. However the ADS GCPlus Linux
+ * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
+ * we use memsetup (CONFIG_INIT_CRITICAL) to remedy that problem.
+ */
+#define CONFIG_INIT_CRITICAL
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110		1	/* This is an SA1100 CPU	*/
+#define CONFIG_GCPLUS		1	/* on an ADS GCPlus Board      */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
+
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96	/* we have an SMC9194 on-board */
+#define CONFIG_LAN91C96_BASE	0x100e0000
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on ADS GCPlus */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
+#define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
+#define CFG_AUTOLOAD            "n"             /* No autoload */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	38400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"ADS GCPlus # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0000000	/* default load address	*/
+
+#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x0a		/* set core clock to 206MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+#define PHYS_SDRAM_2		0xc8000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x01000000 /* 16 MB */
+
+
+#define PHYS_FLASH_1		0x08000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00800000 /* 8 MB */
+#define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#if	1
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#else
+/* REVISIT: This doesn't work on ADS GCPlus just yet:
+#define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
+#define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
+#define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
+#define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION    1       /* hardware flash protection    */
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+#endif
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		PHYS_FLASH_SECT_SIZE
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index 7d232ca3c3..e512f912a9 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -94,12 +94,9 @@
 
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
-				root=/dev/nfs rw nfsroot=157.87.82.48:\
-				/home/a0875451/mwd/myfs/target ip=dhcp"
-#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
-#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
-#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
-#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+				root=/dev/nfs ip=dhcp"
+#define CONFIG_BOOTCOMMAND      "bootp;tftp;bootm"
+#define CFG_AUTOLOAD            "n"             /* No autoload */
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
diff --git a/include/miiphy.h b/include/miiphy.h
index 672baf9f40..7f61cfa4e3 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -53,6 +53,7 @@ int  miiphy_link(unsigned char addr);
 
 /* phy seed setup */
 #define AUTO			99
+#define _1000BASET              1000
 #define _100BASET		100
 #define _10BASET		10
 #define HALF			22
@@ -67,6 +68,9 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
 #define PHY_ANNPTR		0x07
+#define PHY_ANLPNP              0x08
+#define PHY_1000BTCR            0x09
+#define PHY_1000BTSR            0x0A
 #define PHY_PHYSTS		0x10
 #define PHY_MIPSCR		0x11
 #define PHY_MIPGSR		0x12
@@ -113,4 +117,13 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR_10FD		0x0040
 #define PHY_ANLPAR_10		0x0020
 #define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
+
+/* PHY_1000BTSR */
+#define PHY_1000BTSR_MSCF       0x8000
+#define PHY_1000BTSR_MSCR       0x4000
+#define PHY_1000BTSR_LRS        0x2000
+#define PHY_1000BTSR_RRS        0x1000
+#define PHY_1000BTSR_1000FD     0x0800
+#define PHY_1000BTSR_1000HD     0x0400
+
 #endif