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| author | Vaibhav Hiremath <hvaibhav@ti.com> | 2013-03-14 21:11:16 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-24 12:49:05 -0400 |
| commit | 59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4 (patch) | |
| tree | 0e7cd3d2c8410d6207c84c16fc6fd4721cbc987b | |
| parent | 1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf (diff) | |
| download | u-boot-59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4.tar.gz u-boot-59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4.tar.xz u-boot-59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4.zip | |
am335x: Enable DDR PHY dynamic power down bit for DDR3 boards
Enable DDR PHY dynamic power down bit, which enables
powering down the IO receiver when not performing read.
This also helps in reducing overall power consumption in
low power states (suspend/standby).
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 1 | ||||
| -rw-r--r-- | board/ti/am335x/board.c | 6 |
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index ae43ef8778..7ab3bafc95 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -28,6 +28,7 @@ #define VTP_CTRL_START_EN (0x1) #define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 +#define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f4b972b3e9..2e230f456f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = { .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, .zq_config = MT41J128MJT125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; static struct emif_regs ddr3_evm_emif_reg_data = { @@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = { .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, .zq_config = MT41J512M8RH125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; #endif |