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| author | Steve Kipisz <s-kipisz2@ti.com> | 2013-03-08 07:40:58 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-22 11:12:53 -0400 |
| commit | 1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf (patch) | |
| tree | 81105e92c234be3141e32a5f950a7f29a6743b4d | |
| parent | 951d582778a221a79682c4a2619dfcdb7d05d54e (diff) | |
| download | u-boot-1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf.tar.gz u-boot-1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf.tar.xz u-boot-1e7e374b3577888ff6f9e3273fa0ad67e2dc45bf.zip | |
am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.
Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 448cc40157..7932a39e7c 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -54,10 +54,13 @@ void config_sdram(const struct emif_regs *regs) writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->sdram_config, &emif_reg->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); } - writel(regs->sdram_config, &emif_reg->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg->emif_sdram_config); } /** |