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| author | Andy Fleming <afleming@freescale.com> | 2007-02-23 17:12:25 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-23 19:58:28 -0500 |
| commit | 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe (patch) | |
| tree | b95596925ed90ce0a4577e7b4d68b323463564f4 | |
| parent | 45cef612cc601d2d1c890fbbd7cdc9609a189a46 (diff) | |
| download | u-boot-0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe.tar.gz u-boot-0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe.tar.xz u-boot-0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe.zip | |
Support 1G size on 8548
e500v2 and newer cores support 1G page sizes.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 16a697d40c..3777f49adc 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: + tlb_size = BOOKE_PAGESZ_256M; + break; case 1024: case 2048: - tlb_size = BOOKE_PAGESZ_256M; + if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) + tlb_size = BOOKE_PAGESZ_1G; + else + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); /* * The memory was not able to be mapped. + * Default to a small size. */ - return 0; + tlb_size = BOOKE_PAGESZ_64M; + memsize=64; break; } |