change bd->bi_memsize to gd->ram_size, as this is defined
on all archs, so this post test can used on none powerpc
archs too.

Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <hs@denx.de>
cc: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Heiko Schocher <hs@denx.de>

The post.c code is missing braces around the pass case, and as a
result, the diagnostic function will post both fail and pass for
a failed test.  The reason for this bug is probably the incorrect
indentation used, so when reading the code it seems like there
are proper braces.

Indent the code to the correct depth and put proper braces around
the "else" branch of the "if" statement.

Signed-off-by: James Kosin <jkosin@intcomgrp.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

This adds a simple flash test to automatically verify erasing,
writing, and reading of sectors.  The code is based on existing
Blackfin tests but generalized for everyone to use.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

We've got a handy dandy macro already for calculating the number of
elements in an array, so use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Now that we have the generic GPIO layer, we can easily provide a common
implementation for the post_hotkeys_pressed() function based on it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

If we built POST on PPC's that didn't enable CONFIG_SYS_POST_FPU we'd
get the following warning with newer toolchains:

powerpc-linux-gnu-ld: Warning: lib_powerpc/fpu/libpostpowerpcfpu.o
		      uses hard float, libpost.o uses soft float

We actually worked around this sometime ago with the following commit:

commit ce82ff05388b5ddafdf6082ef0776cce72c40b1c
Author: Yuri Tikhonov <yur@emcraft.com>
Date:   Sat Dec 20 14:54:21 2008 +0300

   FPU POST: fix warnings when building with 2.18 binutils

However, this only took into effect if CONFIG_SYS_POST_FPU was enabled.
We can simply move the GNU_FPOST_ATTR out of the CONFIG_SYS_POST_FPU
ifdef block to address the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This patch changes the PPC4xx ethernet POST loop test count from
currently 192 (256 - 64) to a default of 10. While doing this the max
frame size is increased. Each loop run uses a different frame size,
starting with a max of 1514 bytes, down to 64. The default loop
count of 10 can be overriden using CONFIG_SYS_POST_ETH_LOOPS in the
board config header.

The TEST_NUM loop has been removed as it was never used.

The main reason for this change is to reduce the boot time on boards
using this POST test, like the lwmon5 board. This change reduces the
boot time by about 600ms on the lwmon5 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>

This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.

Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>