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<title>u-boot.git/include/tsec.h, branch v2009.08-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<entry>
<title>tsec: Add support for BCM5482S PHY</title>
<updated>2009-06-15T07:13:54+00:00</updated>
<author>
<name>Zach LeRoy</name>
<email>zleroy@xes-inc.com</email>
</author>
<published>2009-05-22T15:26:33+00:00</published>
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Signed-off-by: Zach LeRoy &lt;zleroy@xes-inc.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Signed-off-by: Zach LeRoy &lt;zleroy@xes-inc.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx</title>
<updated>2009-06-12T18:47:17+00:00</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2009-05-22T22:23:24+00:00</published>
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Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
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<pre>
Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>net: tsec: Fix Marvell 88E1121R phy init</title>
<updated>2008-12-05T06:51:54+00:00</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2008-12-02T09:31:04+00:00</published>
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This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15+00:00</published>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Coding style cleanup, update CHANGELOG</title>
<updated>2008-09-13T00:23:05+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-09-13T00:23:05+00:00</published>
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<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>Add SGMII support to the tsec</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:27+00:00</published>
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<id>2abe361c03b43e6dcf68f54e96b5c05156c49284</id>
<content type='text'>
Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Pass in tsec_info struct through tsec_initialize</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:26+00:00</published>
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<content type='text'>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tsec: Move tsec.h to include/</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:25+00:00</published>
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<id>dd3d1f56a01f460d560766126ee7dfed2ea9bc10</id>
<content type='text'>
This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</entry>
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