u-boot.git/include/asm-ppc/processor.h, branch v2009.08-rc2 Unnamed repository; edit this file 'description' to name the repository. ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips 2009-07-30T05:22:18+00:00 Stefan Roese sr@denx.de 2009-07-29T06:45:27+00:00 89bcc4875007ef6608297dc11e7a0d1fbd9900d2 This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> 
This patch is based on a diff created by Phong Vo from AMCC.

Signed-off-by: Phong Vo <pvo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Replace 4xx lowercase SPR references 2009-07-24T04:47:17+00:00 Matthias Fuchs matthias.fuchs@esd.eu 2009-07-22T15:27:56+00:00 58ea142fb2e969f32306c8da1dabfaebd6fa141a Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
86xx: Add CPU_TYPE_ENTRY support 2009-06-30T13:24:22+00:00 Kumar Gala galak@kernel.crashing.org 2009-06-18T13:23:01+00:00 480f61790565d77432b70b4016b73f2ae27d530f Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Unify with 83xx and 85xx and use CPU_TYPE_ENTRY.  We are going to use
this to convey the # of cores and DDR width in the near future so its
good to keep in sync.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Added MPC8535/E identifiers 2009-06-12T22:16:26+00:00 Kumar Gala galak@kernel.crashing.org 2009-05-20T06:11:33+00:00 71b358cc26792889bbac35054d8e89d59b3fabc4 Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx 2009-06-12T18:47:17+00:00 Peter Tyser ptyser@xes-inc.com 2009-05-22T22:23:24+00:00 0f898604945af4543c1525fc33b6bae621a3b805 Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC85xx: Add MPC8569 CPU support 2009-03-30T18:33:51+00:00 Haiying Wang Haiying.Wang@freescale.com 2009-03-27T21:02:44+00:00 22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4 There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
86xx: Update CPU info output on bootup 2009-02-17T00:05:57+00:00 Peter Tyser ptyser@xes-inc.com 2009-02-06T20:30:40+00:00 a1c8a719262151f97119e76166043ee3da3f97b2 - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> 
- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
mpc85xx: Add support for the P2020 2009-02-17T00:05:55+00:00 Srikanth Srinivasan srikanth.srinivasan@freescale.com 2009-01-21T23:17:33+00:00 8d949aff38cfb4388cbd73876e77bcd06d601f20 Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Fix how we map DDR memory 2009-02-17T00:05:51+00:00 Kumar Gala galak@kernel.crashing.org 2009-02-06T15:56:35+00:00 f8523cb0815b2d3d2d780b7d49ca614105555f58 Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
mpc85xx: Add support for the MPC8536 2008-08-27T16:43:54+00:00 Kumar Gala galak@kernel.crashing.org 2008-08-12T16:14:19+00:00 ef50d6c06ece74fb17e8d7510e62cad9df8b810d The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> 
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>