u-boot.git/include/asm-ppc/processor.h, branch v2009.06-rc2

MPC85xx: Add MPC8569 CPU support

2009-03-30T18:33:51+00:00

There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang 
Signed-off-by: Kumar Gala

86xx: Update CPU info output on bootup

2009-02-17T00:05:57+00:00

- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser

mpc85xx: Add support for the P2020

2009-02-17T00:05:55+00:00

Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Travis Wheatley 
Signed-off-by: Kumar Gala

85xx: Fix how we map DDR memory

2009-02-17T00:05:51+00:00

Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala

mpc85xx: Add support for the MPC8536

2008-08-27T16:43:54+00:00

The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Dejan Minic 
Signed-off-by: Jason Jin 
Signed-off-by: Dave Liu

ppc4xx: CPU PPC440x5 on Virtex5 FX

2008-07-18T10:30:50+00:00

-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese

Signed-off-by: Ricardo Ribalda Delgado 
Acked-by: Stefan Roese

Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

2008-07-17T08:41:06+00:00

85xx: Add some L1/L2 SPR register definitions

2008-07-15T01:19:59+00:00

Add new L1/L2 SPRs related to e500mc cache config and control.

Signed-off-by: Kumar Gala

fdt: add crypto node handling for MPC8{3, 5}xxE processors

2008-07-14T22:01:29+00:00

Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips

ppc4xx: Add initial 460SX reference board (redwood) config file and defines.

2008-07-11T11:18:12+00:00

Signed-off-by: Feng Kan 
Signed-off-by: Stefan Roese