u-boot.git/drivers/timer/Kconfig, branch master

timer: Add _TIMER suffix to Andes PLMT Kconfig

2020-10-26T02:01:28+00:00

This matches the naming scheme of other timer drivers.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
Reviewed-by: Rick Chen

riscv: Move Andes PLMT driver to drivers/timer

2020-10-26T02:01:28+00:00

This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
Reviewed-by: Rick Chen

Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next

2020-10-05T14:54:27+00:00

First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.

riscv: Rework riscv timer driver to only support S-mode

2020-09-30T00:54:45+00:00

The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen

timer: mchp-pit64b: add support for pit64b

2020-09-28T11:06:50+00:00

Add support for Microchip PIT64B timer. The timer is 64 bit length and
is used as a free running counter (in continuous mode with highest values
for period registers). The clock feeding the timer would be no more
than 12.5MHz.

Signed-off-by: Claudiu Beznea

timer: Add driver for Nomadik Multi Timer Unit (MTU)

2020-01-22T22:47:56+00:00

The Nomadik Multi Timer Unit (MTU) provides 4 decrementing
free-running timers. It is used in ST-Ericsson Ux500 SoCs.

The driver uses the first timer to implement UCLASS_TIMER.

Signed-off-by: Stephan Gerhold 
Reviewed-by: Linus Walleij

x86: timer: Reduce timer code size in TPL on Intel CPUs

2019-12-15T03:44:10+00:00

Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as

   39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng

x86: timer: use a timer base of 0

2019-12-15T03:44:09+00:00

On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.

When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.

Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng

timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver

2019-05-07T03:41:32+00:00

Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut 
Cc: Chris Brandt 
Cc: Nobuhiro Iwamatsu

timer: Add generic driver for RISC-V privileged architecture defined timer

2018-12-18T01:56:26+00:00

RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.

Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.

With this timer driver the U-Boot timer functionalities like delay
works correctly now.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Reviewed-by: Anup Patel