u-boot.git/drivers/spi, branch v2009.06

Blackfin: spi: fix pin handling of SPI0 SSEL4

2009-05-29T21:11:33+00:00

CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a
peripheral in order to work.

Signed-off-by: Mike Frysinger

at91sam9/at91cap: improve clock framework

2009-04-16T19:30:44+00:00

calculate dynamically the clock rate and pllb setting for usb

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

Blackfin: spi: make cs deassert function deterministic

2009-04-06T07:49:31+00:00

Blackfin SPI driver was not driving the SPI chip-select high before
putting the chip-select signals into tri-state mode.  This is probably
something that slipped by unnoticed in most designs.  If the signals are
put directly into a tri-state mode, then the board is relying on the
pull-up resistors to pull up the chip-select before the next transaction.
Most of the time this is fine, except when you have two transactions that
follow each other very closely, such as the flash erase and read status
register commands.  In this case I was seeing a 500ns separation between
the transactions.  In my setup, with a 10kOhm pull-up, it would meet
timing spec about half the time and resulted in intermittent errors.  (A
stronger pull up would fix this, but our design is targeted for low power
consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
chip-selects high before putting them into tri-state.  For me, this
resulted in a rise time of 5ns instead of the previous rise time of about
1us, and fully satisfied the timing spec of the chip.

Signed-off-by: Todor I Mollov 
Signed-off-by: Mike Frysinger

at91: move dataflash spi driver to drivers/spi

2009-04-04T18:42:22+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

Blackfin: add BF538/BF539 SPI portmux handling

2009-04-02T10:42:18+00:00

Signed-off-by: Mike Frysinger

Blackfin: spi: there is no PORTJ_FER MMR on BF537

2009-03-23T19:14:52+00:00

Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality),
then there is no PORTJ_FER register for us to worry about.

Signed-off-by: Sonic Zhang 
Signed-off-by: Mike Frysinger

i.MX31: support GPIO as a chip-select in the mxc_spi driver

2009-02-24T08:48:33+00:00

Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.

Signed-off-by: Guennadi Liakhovetski 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD

i.MX31: fix SPI driver for shorter than 32 bit

2009-02-24T08:39:44+00:00

Fix setting the SPI Control register, 8 and 16-bit transfers
and a wrong pointer in the free routine in the mxc_spi driver.

Signed-off-by: Guennadi Liakhovetski 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD

Blackfin: add driver for on-chip SPI controller

2009-02-02T17:24:30+00:00

This fills out the SPI backend for the Blackfin on-chip SPI peripheral.

Signed-off-by: Mike Frysinger

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD