After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Marcin Wojtas <marcin@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.

Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

gd is not used in this file that's why doesn't make sense to declare it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Xilinx changes for v2021.07

net:
- Fix gem PCS support

spi:
- Small trivial fixes

zynq:
- Enable time/timer commands
- Update bitmain platform
- Several DT changes

zynqmp:
- Update clock driver
- mini config alignments
- Add/update psu_init for zcu208/zcu216/zc1275
- Several DT changes
- Enable efi debug command (also for Versal)

Use __func__ instead for function name in debug.
Use Linux style u32 instead of uint32_t.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add spi memory operations to relocate manually when
CONFIG_NEEDS_MANUAL_RELOC is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

In case of reading large area and memory-map mode is misconfigured
(memory-map size declared lower than the real size of the memory chip)
watchdog can be triggered.

Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it.

Issue reproduced with stm32mp157c-ev1 board and memory map size set to
1, with following command:
sf read 0xC0000000 0 0x4000000

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>