u-boot.git/drivers/ram/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS 2021-05-12T11:00:52+00:00 Dave Gerlach d-gerlach@ti.com 2021-05-11T15:22:10+00:00 db2438131d75ea0198487296b6c694bded080d11 Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> 
Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ram: k3-j721e: Rename to k3-ddrss 2021-05-12T11:00:52+00:00 Dave Gerlach d-gerlach@ti.com 2021-05-11T15:22:09+00:00 67124b9a74fca735beefea147bd4177acaa1661a Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> 
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ram: move aspeed ram driver into drivers/ directory 2020-10-08T14:58:33+00:00 Dylan Hung dylan_hung@aspeedtech.com 2020-09-07T08:25:06+00:00 5d457f8057962fbd2ae90826fe80b4039f2dba71 to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> 
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3) 2020-10-07T18:25:57+00:00 Aaron Williams awilliams@marvell.com 2020-09-02T06:29:08+00:00 15afe725f390774af588c21d127b94915b4f1e17 This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> 
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
sifive: fu540: add ddr driver 2020-06-04T01:44:08+00:00 Pragnesh Patel pragnesh.patel@sifive.com 2020-05-29T06:03:26+00:00 c514a94abf5aa997508ba072b90318ec10655193 Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> 
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
ram: add SDRAM driver for i.MXRT SoCs 2020-01-14T21:54:00+00:00 Giulio Benetti giulio.benetti@benettiengineering.com 2020-01-10T14:51:44+00:00 cd647fc4fb8e6018089d0e0a3dfa71bd6beffde4 Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> 
Add SDRAM driver for i.MXRT SoCs.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
ram: k3-j721e: Add support for J721E DDR controller 2019-10-25T21:33:21+00:00 Kevin Scholz k-scholz@ti.com 2019-10-07T13:56:36+00:00 3bb3f266ee617384bb282a6818f675b5aca5c371 The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ram: MediaTek: add DDR3 driver for MT7629 SoC 2018-11-29T04:04:53+00:00 Ryder Lee ryder.lee@mediatek.com 2018-11-15T02:08:03+00:00 60f633efd5fb6018785f8fb624fcac55dba6987e This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou <wu.zou@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
This patch adds a DDR3 driver for MT7629 SoC.

Signed-off-by: Wu Zou <wu.zou@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ram: Introduce K3 AM654 DDR Sub System driver 2018-11-16T21:51:58+00:00 Lokesh Vutla lokeshvutla@ti.com 2018-11-02T14:21:02+00:00 06bda1259ffc3ef899de70c7fb86b0982a2912f0 K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> 
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
drivers: cosmetic: Convert SPDX license tags to Linux Kernel style 2018-10-28T13:26:39+00:00 Patrick Delaunay patrick.delaunay@st.com 2018-10-26T07:02:52+00:00 22929e1266e9a61048bfaef381ad4fb2e2fc3ef5 Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> 
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>