u-boot.git/drivers/pci, branch master

arm: a37xx: pci: Fix configuring PCIe resources

2021-06-04T09:32:41+00:00

The `ranges` DT property of the PCIe node is currently ignored by
Aardvark driver - all entries are used as transparent PCIe MEM, despite
some of them being defined for IO in DT.

This is because the driver does not setup PCIe outbound windows and thus
a default configuration is used.

This can cause an external abort on CPU when a device driver tries to
access non-MEM space.

Setup the PCIe windows according to the `ranges` property for all
non-MEM resources (currently only IO) and also non-transparent MEM
resources.

Because Linux expects that bootloader does not setup Aardvark PCIe
windows, disable them before booting Linux.

Signed-off-by: Pali Rohár 
Reviewed-by: Marek Behún 
Reviewed-by: Stefan Roese

arm: a37xx: pci: Fix DT compatible string to Linux' DT compatible

2021-06-04T09:32:41+00:00

Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie'
to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible
with Linux' DT node.

Signed-off-by: Pali Rohár 
Reviewed-by: Marek Behún 
Reviewed-by: Stefan Roese

arm: a37xx: pci: Disable bus mastering when unloading driver

2021-06-04T09:32:41+00:00

Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's
remove method, which is called before booting Linux kernel.

This ensures that PCIe device which was initialized and used by U-Boot
cannot do new DMA transfers until Linux initializes PCI subsystem and loads
appropriate drivers for the device.

During initialization of PCI subsystem Linux in fact disables this bus
mastering on Root Bridge (and later enables it when driver is loaded and
configured), but there is a possibility of a small window after U-Boot
boots Linux when bus mastering is enabled, which is not correct.

Signed-off-by: Pali Rohár 
Reviewed-by: Marek Behún 
Reviewed-by: Stefan Roese

arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe

2021-06-04T09:32:41+00:00

During our debugging of the Aardvark driver in Linux we have discovered
that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard
PCIe Link Control Register for PCIe Root Bridge. This led us to discover
that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding
comment by this macro's usage is misleading; this bit in fact controls
Retrain Link, which, according to PCIe base spec is defined as:

  A write of 1b to this bit initiates Link retraining by directing the
  Physical Layer LTSSM to the Recovery state. If the LTSSM is already in
  Recovery or Configuration, re-entering Recovery is permitted but not
  required.

Entering Recovery state is normally done from LTSSM L0, L0s and L1 states.
But since the pci-aardvark.c driver enables Link Training just a few lines
above, the controller is not in L0 ready state yet. So setting aardvark bit
PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this
place.

Moreover, trying to enter LTSSM Recovery state without other configuration
is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since
Recovery state is not entered, these issues are not triggered.

Remove code which tries to enter LTSSM Recovery state completely.

Signed-off-by: Pali Rohár 
Reviewed-by: Marek Behún 
Reviewed-by: Stefan Roese

drivers: pci: pcie_dw_common: fix Werror compilation error

2021-05-31T08:35:55+00:00

Fix compilation error when Werror is turned on. The warning could
possible break some CI builds.

Signed-off-by: Green Wan 
Reviewed-by: Leo Yu-Chi Liang

drivers: pci: add pcie support for fu740

2021-05-31T08:35:54+00:00

Add pcie driver for SiFive fu740, the driver depends on
fu740 gpio, clk and reset driver to do init. Force running at Gen1
for better capatible enumeration.

Several devices are tested:
a) M.2 NVMe SSD
b) USB-to-PCI adapter
c) Ethernet adapter (E1000 compatible)

Signed-off-by: Green Wan 
Reviewed-by: Neil Armstrong

pcie: designware: mvebu: do not configure ATU for IO when not used

2021-05-16T04:48:45+00:00

The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.

Signed-off-by: Marcin Wojtas 
Reviewed-on: https://sj1git1.cavium.com/18136
Reviewed-by: Kostya Porotchkin 
Tested-by: Kostya Porotchkin

pci: imx: disable imx6sdl LTSSM upon driver remove

2021-05-02T10:46:54+00:00

commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function")
attempted to resolve an issue caused by MX6QDL not having a proper
intneral PCIe core reset and thus hanging during kernel init if the
bootloader had enabled PCI.

The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for
IMX6S and IMX6DL getting missed.

This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for
Linux v4.11+.

Signed-off-by: Tim Harvey 
Reviewed-by: Fabio Estevam

pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI

2021-05-02T10:46:54+00:00

Add a board_pci_fixup_dev weak function to allow PCI device fixups
during enumeration.

Signed-off-by: Tim Harvey

pci: Update the highest subordinate bus number for bridge setup

2021-05-02T10:46:54+00:00

Update the highest subordinate bus number after probing the devices
under the bus for setting up the bridge correctly.
The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
removed this but it is required if a PCIe bridge is under the bus.

Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
Signed-off-by: Masami Hiramatsu