u-boot.git/drivers/mtd, branch master

ARM: fix LTO for apf27

2021-05-24T18:21:30+00:00

When apf27_defconfig is built with LTO, linking complains about
undefined reference to `nand_boot`. This is because it is referenced
from inline assembly. Make it visible.

Signed-off-by: Marek Behún

mtd: cfi: Fix PPB lock status readout

2021-04-28T08:29:36+00:00

According to S26KL512S datasheet [1] and S29GL01GS datasheet [2],
the procedure to read out PPB lock bits is to send the PPB Entry,
PPB Read, Reset/ASO Exit. Currently, the code does send incorrect
PPB Entry, PPB Read and Reset/ASO Exit is completely missing.

The PPB Entry sent is implemented by sending flash_unlock_seq()
and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to
sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID.
However, both [1] and [2] specify the last byte of PPB Entry as
0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID,
that is  0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY.
Since this does make sense, this patch fixes it and thus also
aligns the code in flash_get_size() with flash_real_protect().

The PPB Read returns 00h in case of Protected state and 01h in case
of Unprotected state, according to [1] Note 83 and [2] Note 17, so
invert the result. Moreover, align the arguments with similar code
in flash_real_protect().

Finally, Reset/ASO Exit command should be executed to exit the PPB
mode, so add the missing reset.

[1] https://www.cypress.com/file/213346/download
    Document Number: 001-99198 Rev. *M
    Table 40. Command Definitions, Nonvolatile Sector Protection
    Command Set Definitions
[2] https://www.cypress.com/file/177976/download
    Document Number: 001-98285 Rev. *R
    Table 7.1 Command Definitions, Nonvolatile Sector Protection
    Command Set Definitions

Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips")
Signed-off-by: Marek Vasut 
Cc: Stefan Roese 
Reviewed-by: Stefan Roese

mtd: Update fail_addr when erase fails due to bad blocks

2021-04-12T21:17:11+00:00

For all other erase failures, the fail_addr is updated with the
failing address. Only in the case of erase failure due to bad block
detection, the fail_addr is not updated. This change simply updates
the fail_addr for this specific scenario so that it is consistent with
the rest of the code.

Signed-off-by: Farhan Ali

spl: fit: nand: allow for non-page-aligned elements

2021-04-08T18:29:53+00:00

Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.

The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.

Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.

Signed-off-by: Tim Harvey 
Reviewed-by: Tom Rini

cfi_flash: Fix detection of 8-bit bus flash devices via address shift

2021-04-06T06:55:53+00:00

We had a problem detecting 8/16bit flash devices connected only via
8bits to the SoC for quite a while. Commit 239cb9d9
[mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support] finally
fixed this 8-bit bus support. But also broke some other boards using
this cfi driver. So this patch had to be reverted.

I spotted a different, simpler approach for this 8-bit bus support
on the barebox mailing list posted by
Oleksij Rempel :

http://www.spinics.net/lists/u-boot-v2/msg14687.html

Here the commit text:

"
Many cfi chips support 16 and 8 bit modes. Most important
difference is use of so called "Q15/A-1" pin. In 16bit mode this
pin is used for data IO. In 8bit mode, it is an address input
which add one more least significant bit (LSB). In this case
we should shift all adresses by one:
For example 0xaa << 1 = 0x154
"

This patch now is a port of this barebox patch to U-Boot.

Along with the change w.r.t from barebox,
Some flash chips can support multiple bus widths, override the
interface width and limit it to the port width.

Tested on 16-bit Spansion flash on sequoia.
Tested 8-bit flashes like 256M29EW, 512M29EW.

Signed-off-by: Stefan Roese 
Tested-by: Jagannadha Sutradharudu Teki 
Cc: Jagannadha Sutradharudu Teki 
Cc: Aaron Williams 
Cc: Chandrakala Chavva 
Cc: Andre Przywara 
Cc: Vignesh Raghavendra 
Cc: Simon Glass 
Cc: Mario Six 
Cc: York Sun 
Cc: Marek Vasut

Merge tag 'v2021.04-rc5' into next

2021-03-29T22:00:21+00:00

Prepare v2021.04-rc5

sf: Support querying write-protect

2021-03-27T02:04:31+00:00

This feature was dropped from U-Boot some time ago:

   f12f96cfaf5 (sf: Drop spl_flash_get_sw_write_prot")

However, we do need a way to see if a flash device is write-protected,
since if it is, it may not be possible to write to do (i.e. failing to
write is expected).

I am not sure of the correct layer to implement this, so this patch is a
stab at it. If spi-flash makes sense then I will add to the 'sf' also.

Re the points mentioned in the removal commit:

    1) This kind of requirement can be achieved using existing
       flash operations and flash locking API calls instead of
       making a separate flash API.

Which uclass is this?

    2) Technically there is no real hardware user for this API to
       use in the source tree.

I do want coral (at least) to support this.

    3) Having a flash operations API for simple register read bits
       also make difficult to extend the flash operations.

This new patch only mentions write-protect being on or off, rather than
the actual mechanism.

    4) Instead of touching generic code, it is possible to have
       this functionality inside spinor operations in the form of
       flash hooks or fixups for associated flash chips.

That sounds to me like what drivers are for. But we still need some sort
of API for it to be accessible.

Signed-off-by: Simon Glass

mtd: spi_flash_free()

2021-03-27T00:59:36+00:00

dfu_free_entities() invoking dfu_free_entity_sf() has let to segementation
faults due to double freeing the same device.

spi_flash_free() is not relevant for the driver model but exists only for
compatibility with old drivers.

We must not remove any device here:

* The device may still be referenced.
* We don't want to have to probe again.

Signed-off-by: Heinrich Schuchardt

mtd: rawnand: fsl_ifc: fix FSL NAND driver to read all ONFI parameter pages

2021-03-23T12:36:07+00:00

Linux commit a75bbe71a27 ("mtd: rawnand: fsl_ifc: fix FSL NAND driver to
 read all ONFI parameter pages")

Per ONFI specification (Rev. 4.0), if the CRC of the first parameter page
read is not valid, the host should read redundant parameter page copies.
Fix FSL NAND driver to read the two redundant copies which are mandatory
in the specification.

Signed-off-by: Jane Wan 
Signed-off-by: Boris Brezillon 
Signed-off-by: Maxim Kochetkov 
Reviewed-by: Priyanka Jain

mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write()

2021-03-11T16:00:41+00:00

In case of big area read/write on spi nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and
spinand_mtd_write() to ensure that watchdog is reset.

Signed-off-by: Patrice Chotard 
Reviewed-by: Patrick Delaunay