u-boot.git/drivers/mtd/nand, branch master Unnamed repository; edit this file 'description' to name the repository. ARM: fix LTO for apf27 2021-05-24T18:21:30+00:00 Marek Behún marek.behun@nic.cz 2021-05-20T11:24:13+00:00 28d476eada6b49fdbd331171c6a487466e709a66 When apf27_defconfig is built with LTO, linking complains about undefined reference to `nand_boot`. This is because it is referenced from inline assembly. Make it visible. Signed-off-by: Marek Behún <marek.behun@nic.cz> 
When apf27_defconfig is built with LTO, linking complains about
undefined reference to `nand_boot`. This is because it is referenced
from inline assembly. Make it visible.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
mtd: Update fail_addr when erase fails due to bad blocks 2021-04-12T21:17:11+00:00 Farhan Ali farhan.ali@broadcom.com 2021-02-24T23:25:53+00:00 c146de48727da66ea7dc43f12bd41814cff2faa8 For all other erase failures, the fail_addr is updated with the failing address. Only in the case of erase failure due to bad block detection, the fail_addr is not updated. This change simply updates the fail_addr for this specific scenario so that it is consistent with the rest of the code. Signed-off-by: Farhan Ali <farhan.ali@broadcom.com> 
For all other erase failures, the fail_addr is updated with the
failing address. Only in the case of erase failure due to bad block
detection, the fail_addr is not updated. This change simply updates
the fail_addr for this specific scenario so that it is consistent with
the rest of the code.

Signed-off-by: Farhan Ali <farhan.ali@broadcom.com>
spl: fit: nand: allow for non-page-aligned elements 2021-04-08T18:29:53+00:00 Tim Harvey tharvey@gateworks.com 2021-03-01T22:33:28+00:00 aa0032f67267232c6b315b5f6e1c086c217c9aae Add a weak nand_get_mtd function for nand drivers to provide mtd info and use this to set pagesize such that reading of non page-aligned elements can succeed. The spl_load_simple_fit already handles block block access so all we need to do is provide the nand writesize as the block length. Further cleanup of the drivers which use nand_spl_loaders.c such as am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done using info from mtd_info instead of statically defined details. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.

The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.

Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
mtd: rawnand: fsl_ifc: fix FSL NAND driver to read all ONFI parameter pages 2021-03-23T12:36:07+00:00 Maxim Kochetkov fido_max@inbox.ru 2021-03-12T06:27:41+00:00 cad6ffa34d255692833576bc2c911d1ee39f2af0 Linux commit a75bbe71a27 ("mtd: rawnand: fsl_ifc: fix FSL NAND driver to read all ONFI parameter pages") Per ONFI specification (Rev. 4.0), if the CRC of the first parameter page read is not valid, the host should read redundant parameter page copies. Fix FSL NAND driver to read the two redundant copies which are mandatory in the specification. Signed-off-by: Jane Wan <Jane.Wan@nokia.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 
Linux commit a75bbe71a27 ("mtd: rawnand: fsl_ifc: fix FSL NAND driver to
 read all ONFI parameter pages")

Per ONFI specification (Rev. 4.0), if the CRC of the first parameter page
read is not valid, the host should read redundant parameter page copies.
Fix FSL NAND driver to read the two redundant copies which are mandatory
in the specification.

Signed-off-by: Jane Wan <Jane.Wan@nokia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write() 2021-03-11T16:00:41+00:00 Patrice Chotard patrice.chotard@foss.st.com 2021-01-20T13:42:04+00:00 de6f70a6329ebf3845fa9173dbd7962a15802c05 In case of big area read/write on spi nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and spinand_mtd_write() to ensure that watchdog is reset. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> 
In case of big area read/write on spi nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and
spinand_mtd_write() to ensure that watchdog is reset.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
mtd: nand: Add WATCHDOG_RESET() in nanddev_mtd_erase() 2021-03-11T15:59:16+00:00 Patrice Chotard patrice.chotard@foss.st.com 2021-01-20T13:42:03+00:00 3f6cfdaa23763b691345d2d3709fe1668291f407 In case of big area erased on nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that watchdog is reset. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> 
In case of big area erased on nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that
watchdog is reset.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG 2021-02-26T10:31:37+00:00 Reto Schneider reto.schneider@husqvarnagroup.com 2021-02-11T12:05:48+00:00 783a15b35131abc599ec6deca55cf841d2e7c208 The relevant changes to the already existing GD5F1GQ4UExxG support has been determined by consulting the GigaDevice product change notice AN-0392-10, version 1.0 from November 30, 2020. As the overlaps are huge, variable names have been generalized accordingly. Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes), the new device ID, and the extra quad IO dummy byte, no changes had to be taken into account. New hardware features are not supported, namely: - Power on reset - Unique ID - Double transfer rate (DTR) - Parameter page - Random data quad IO The inverted semantic of the "driver strength" register bits, defaulting to 100% instead of 50% for the Q5 devices, got ignored as the driver has never touched them anyway. The no longer supported "read from cache during block erase" functionality is not reflected as the current SPI NAND core does not support it anyway. Implementation has been tested on MediaTek MT7688 based GARDENA smart Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG. Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com> 
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.

As the overlaps are huge, variable names have been generalized
accordingly.

Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.

New hardware features are not supported, namely:
 - Power on reset
 - Unique ID
 - Double transfer rate (DTR)
 - Parameter page
 - Random data quad IO

The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.

The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.

Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: nand: spi: Only one dummy byte in QUADIO 2021-02-26T10:31:29+00:00 Hauke Mehrtens hauke@hauke-m.de 2021-02-11T12:05:47+00:00 12926f46fdf443144451416939074c688b2c43a4 The datasheet only lists one dummy byte in the 0xEB operation for the following chips: * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG Reto Schneider: - Linux patch ported to U-Boot - Checked for compatibility with GD5F1GQ4xBxxG - Fixed operation code in original commit message (0xEH -> 0xEB) Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com> 
The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: rawnand: cortina_nand: missing initialization 2021-02-24T21:51:49+00:00 Heinrich Schuchardt xypron.glpk@gmx.de 2021-02-20T09:42:50+00:00 6b0431dc21050a14bf80db4b3c34444816d7652d ca_do_bch_correction() takes a random value from the stack and starts counting bitflips from this value. Initialize the counter. This passed unnoticed as the value is finally ignored in the call hierarchy. Fixes: 161df94b3c43 ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> 
ca_do_bch_correction() takes a random value from the stack and starts
counting bitflips from this value. Initialize the counter.

This passed unnoticed as the value is finally ignored in the call
hierarchy.

Fixes: 161df94b3c43 ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Merge branch '2021-02-02-drop-asm_global_data-when-unused' 2021-02-15T15:16:45+00:00 Tom Rini trini@konsulko.com 2021-02-15T13:19:40+00:00 2ae80437fbe0181184ae4b188b89629b902702c6 - Merge the patch to take <asm/global_data.h> out of <common.h> 
- Merge the patch to take <asm/global_data.h> out of <common.h>