u-boot.git/drivers/mmc, branch v2011.03

S5P: mmc: Resolved interrupt error during mmc_init

2011-03-27T17:20:26+00:00

Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.

It is now calculated based upon the request sent by mmc subsystem.

Signed-off-by: Chander Kashyap 
Signed-off-by: Minkyu Kang

fsl_esdhc: Correcting esdhc timeout counter calculation

2011-03-07T14:49:28+00:00

- Timeout counter value is set as DTOCV bits in SYSCTL register
  For counter value set as timeout,
  Timeout period = (2^(timeout + 13)) SD Clock cycles

- As per 4.6.2.2 section of SD Card specification v2.00, host should
  cofigure timeout period value to minimum 0.25 sec.

- Number of SD Clock cycles for 0.25sec should be minimum
	(SD Clock/sec * 0.25 sec) SD Clock cycles
	= (mmc->tran_speed * 1/4) SD Clock cycles

- Calculating timeout based on
	(2^(timeout + 13)) >=  mmc->tran_speed * 1/4
	Taking log2 both the sides and rounding up to next power of 2
	=> timeout + 13 = log2(mmc->tran_speed/4) + 1

Signed-off-by: Priyanka Jain 
Signed-off-by: Andy Fleming 
Acked-by: Mingkai Hu 
Tested-by: Stefano Babic 
Signed-off-by: Kumar Gala

fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)

2011-02-03T08:46:12+00:00

Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala

Minor Coding Style Cleanup.

2011-02-02T21:36:10+00:00

Signed-off-by: Wolfgang Denk

Davinci MMCSD Support

2011-02-01T23:54:44+00:00

Added support for MMC/SD cards for Davinci.  This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.

Signed-off-by: Alagu Sankar 
Signed-off-by: Sandeep Paulraj

fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)

2011-01-14T07:32:22+00:00

The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.

Signed-off-by: Roy Zang 
Signed-off-by: Kumar Gala

fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)

2011-01-14T07:32:22+00:00

Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.

Signed-off-by: Jerry Huang 
Signed-off-by: Roy Zang 
Signed-off-by: Kumar Gala

fsl_esdhc: Fix esdhc disabled problem on some platforms

2011-01-14T07:32:19+00:00

Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.

Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Li Yang 
Signed-off-by: Kumar Gala

fsl_esdhc: Fix the voltage validation process

2010-12-18T22:15:24+00:00

The current code use all the voltage range support by the host
controller to do the validation.  This will cause problem when
the host supports Low Voltage Range.  Change the validation
voltage to be based on board setup.

Signed-off-by: Li Yang 
Tested-by: Stefano Babic 
Signed-off-by: Kumar Gala

fsl_esdhc: Fix max clock frequency

2010-12-18T22:15:24+00:00

The max clock of MMC is 52MHz

Signed-off-by: Jerry Huang 
Tested-by: Stefano Babic 
Signed-off-by: Kumar Gala