u-boot.git/drivers/fpga, branch master

arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64

2021-03-08T02:59:10+00:00

Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim

Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

2021-02-23T15:45:55+00:00

Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name

fpga: zynqpl: fix buffer alignment

2021-02-23T13:56:55+00:00

Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is
subtracted. It seems that the original intention was to just subtract
ARCH_DMA_MINALIGN. Fix it.

Signed-off-by: Michael Walle 
Signed-off-by: Michal Simek

image: Adjust the workings of fit_check_format()

2021-02-16T03:31:52+00:00

At present this function does not accept a size for the FIT. This means
that it must be read from the FIT itself, introducing potential security
risk. Update the function to include a size parameter, which can be
invalid, in which case fit_check_format() calculates it.

For now no callers pass the size, but this can be updated later.

Also adjust the return value to an error code so that all the different
types of problems can be distinguished by the user.

Signed-off-by: Simon Glass 
Reported-by: Bruce Monroe 
Reported-by: Arie Haenel 
Reported-by: Julien Lenoir

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42+00:00

Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include  at all, so
remove that include.

Signed-off-by: Simon Glass 
Signed-off-by: Tom Rini

arm: socfpga: soc64: Add ATF support for FPGA reconfig driver

2021-01-15T09:48:37+00:00

In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.

Signed-off-by: Chee Hong Ang

arm: socfpga: agilex: Enable FPGA Full Reconfiguration support

2020-10-09T09:53:12+00:00

Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang 
Reviewed-by: Ley Foon Tan

fpga: intel_sdm_mb: Add watchdog reset

2020-10-09T09:53:12+00:00

Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.

Signed-off-by: Chee Hong Ang 
Reviewed-by: Ley Foon Tan

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09T09:53:12+00:00

Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang 
Reviewed-by: Ley Foon Tan

fpga: zynqmp: Protect zynqmp_loads() for SPL

2020-09-23T08:31:41+00:00

if conditions should match.

Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP")
Signed-off-by: Michal Simek