u-boot.git/cpu, branch v2009.06

fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT

2009-06-12T14:15:50+00:00

The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.

Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.

This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have.  Its only the LAW
setup that limits what is visible to the system.

Signed-off-by: Kumar Gala

85xx: Use print_size to report amount of memory not mapped by TLBs

2009-06-12T14:15:48+00:00

Signed-off-by: Kumar Gala

at91/cpu.c: add missing Copyright & GPL header

2009-06-09T23:29:29+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

85xx: bugfix for reading maximum TLB size on mpc85xx

2009-06-09T20:58:18+00:00

The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits.
This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum
(256 MB)
which made u-boot hang in board_init_f() when trying to create a new stack
in RAM.
I have an mpc8540 with one 1GB dimm.

Signed-off-by: Fredrik Arnerup 
Signed-off-by: Andy Fleming 
Acked-by: Kumar Gala

ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platforms

2009-05-23T10:51:39+00:00

This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.

Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.

Signed-off-by: Stefan Roese 
Acked-by: Scott Wood

ppc4xx: Move definition for PPC4xx NAND FLASH controller to header

2009-05-23T10:51:39+00:00

This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.

Signed-off-by: Stefan Roese 
Acked-by: Scott Wood

Blackfin: fix timer_init()/timer_reset()

2009-05-19T08:57:33+00:00

The timer_init() function was not using the right csync instruction, nor
was it doing it right after disabling the core timer.

The timer_reset() function would reset the timestamp, but not the actual
timer, so there was a common edge case where get_timer() return a jump of
one timestamp (couple milliseconds) right after resetting.  This caused
many functions to improperly timeout right away.

Signed-off-by: Graf Yang 
Signed-off-by: Mike Frysinger

MIPS: Implement ethernet halt for au1x00

2009-05-16T00:20:03+00:00

Implement ethernet halt() by putting MAC0 in reset.
If we do not do this, we will get memory corruption
when ethernet frames are received during early OS boot.

Signed-off-by: Thomas Lange 
Signed-off-by: Shinya Kuribayashi

74xx_7xx: Fix rounding problem in CPU frequency calculation

2009-05-15T20:22:01+00:00

This patch fixes a problem in the CPU frequency calculation. Without it
a 798MHz CPU is displayed as 368.503 MHz. And with it it's 798 MHz.

Signed-off-by: Stefan Roese

Fix e-mail address of Gary Jennejohn.

2009-05-15T20:11:59+00:00

Signed-off-by: Detlev Zundel