u-boot.git/cpu/mpc8xxx, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

85xx: Added various P1012/P1013/P1021/P1022 defines

2010-04-07T05:21:22+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config

Signed-off-by: Haiying Wang 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Kumar Gala

fsl-ddr: change the default burst mode for DDR3

2010-04-07T05:08:06+00:00

For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.

Signed-off-by: Dave Liu

fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

2010-04-07T05:07:23+00:00

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.

Signed-off-by: Dave Liu

fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave

2010-01-05T19:50:07+00:00

In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

fsl-ddr: add override for the Rtt_Wr

2010-01-05T19:49:27+00:00

Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

fsl-ddr: add the override for write leveling

2010-01-05T19:49:10+00:00

add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

fsl-ddr: Fix power-down timing settings

2010-01-05T19:49:10+00:00

1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

ppc/8xxx: Remove is_fsl_pci_agent

2010-01-05T19:49:07+00:00

All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.

Signed-off-by: Kumar Gala

ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms

2010-01-05T19:49:03+00:00

The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.

Signed-off-by: Kumar Gala