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<title>u-boot.git/cpu/mips/cpu.c, branch v2009.06-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<entry>
<title>MIPS: Add flush_dcache_range() and invalidate_dcache_range()</title>
<updated>2009-01-27T14:06:58+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2009-01-21T16:20:20+00:00</published>
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This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
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<pre>
This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</pre>
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</entry>
<entry>
<title>net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_init</title>
<updated>2008-11-10T05:38:02+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-10-19T03:08:50+00:00</published>
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This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init
as a part of ongoing eth_initialize cleanup work.  The function ret value
is also fixed as it should be negative on fail.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init
as a part of ongoing eth_initialize cleanup work.  The function ret value
is also fixed as it should be negative on fail.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15+00:00</published>
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<id>6d0f6bcf337c5261c08fabe12982178c2c489d76</id>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>[MIPS] &lt;asm/mipsregs.h&gt;: Update coprocessor register access macros</title>
<updated>2008-05-29T15:53:38+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-05-29T15:53:38+00:00</published>
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<content type='text'>
Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</content>
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<pre>
Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</pre>
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</content>
</entry>
<entry>
<title>cpu/mips/cpu.c: Fix flush_cache bug</title>
<updated>2008-04-17T21:54:23+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>shinya.kuribayashi@necel.com</email>
</author>
<published>2008-04-08T07:20:35+00:00</published>
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<content type='text'>
Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
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<pre>
Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>[MIPS] Introduce _machine_restart</title>
<updated>2008-03-25T12:30:07+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-03-25T12:30:07+00:00</published>
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<id>b0c66af53ec9385ac2d1cc2e5d7d1ecdc81caf34</id>
<content type='text'>
Handles machine specific functions by using weak functions.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
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<pre>
Handles machine specific functions by using weak functions.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</pre>
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</content>
</entry>
<entry>
<title>[MIPS] Implement flush_cache()</title>
<updated>2008-03-25T12:30:06+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-03-25T12:30:06+00:00</published>
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<content type='text'>
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
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<pre>
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</pre>
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</content>
</entry>
<entry>
<title>[MIPS] MIPS 4K core: Coding style cleanups</title>
<updated>2007-11-17T11:05:26+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2007-10-27T06:27:06+00:00</published>
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<id>03c031d5660ea946c39af6e2e16267da857c609f</id>
<content type='text'>
No logical changes.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
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<pre>
No logical changes.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
</pre>
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</content>
</entry>
<entry>
<title>* Patch by liang a lei, 9 Jan 2004:</title>
<updated>2004-02-07T01:27:10+00:00</updated>
<author>
<name>wdenk</name>
<email>wdenk</email>
</author>
<published>2004-02-07T01:27:10+00:00</published>
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<id>f4863a7aec41f1f78fe93eade700b15b287a5ef7</id>
<content type='text'>
  Fix Intel 28F128J3 ID in include/flash.h

* Patch by Masami Komiya, 09 Jan 2004:
  add support for TB0229 board (NEC VR4131 MIPS processor)

* Patch by Leon Kukovec, 12 Dec 2003:
  changed extern __inline__ into static __inline__ in
  include/linux/byteorder/swab.h
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<pre>
  Fix Intel 28F128J3 ID in include/flash.h

* Patch by Masami Komiya, 09 Jan 2004:
  add support for TB0229 board (NEC VR4131 MIPS processor)

* Patch by Leon Kukovec, 12 Dec 2003:
  changed extern __inline__ into static __inline__ in
  include/linux/byteorder/swab.h
</pre>
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</content>
</entry>
<entry>
<title>* Patch by Steven Scholz, 10 Oct 2003</title>
<updated>2003-10-09T20:09:04+00:00</updated>
<author>
<name>wdenk</name>
<email>wdenk</email>
</author>
<published>2003-10-09T20:09:04+00:00</published>
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<id>5da627a424b3ad2d38a81886ba4a18e5123a6788</id>
<content type='text'>
  - Add support for Altera FPGA ACEX1K

* Patches by Thomas Lange, 09 Oct 2003:
  - Endian swap ATA identity for all big endian CPUs, not just PPC
  - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
    args to linux
  - add support for dbau1x00 board (MIPS32)
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<pre>
  - Add support for Altera FPGA ACEX1K

* Patches by Thomas Lange, 09 Oct 2003:
  - Endian swap ATA identity for all big endian CPUs, not just PPC
  - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
    args to linux
  - add support for dbau1x00 board (MIPS32)
</pre>
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</content>
</entry>
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