u-boot.git/cpu/mips/cache.S, branch v2009.06-rc2

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

[MIPS] Update header

2008-06-05T13:29:00+00:00

- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR

Signed-off-by: Shinya Kuribayashi

[MIPS] Kill unused inclusions

2008-06-05T13:29:00+00:00

Signed-off-by: Shinya Kuribayashi

[MIPS] cpu/mips/cache.S: Fix build warning

2008-05-06T04:22:52+00:00

Some old GNU assemblers, such as v2.14 (ELDK 3.1.1), v2.16 (ELDK 4.1.0),
warns illegal global symbol references by bal (and jal also) instruction.
This does not happen with the latest binutils v2.18.

Here's an example on gth2_config:

mips_4KC-gcc  -D__ASSEMBLY__ -g  -Os   -D__KERNEL__ -DTEXT_BASE=0x90000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isy
stem /opt/eldk311/usr/bin/../lib/gcc-lib/mips-linux/3.3.3/include -pipe  -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4k
c -EB -c -o cache.o cache.S
cache.S: Assembler messages:
cache.S:243: Warning: Pretending global symbol used as branch target is local.
cache.S:250: Warning: Pretending global symbol used as branch target is local.

In principle, gas might be sensitive to global symbol references in PIC
code because they should be processed through GOT (global offset table).
But if `bal' instruction is used, it results in PC-based offset jump.
This is the cause of this warning.

In practice, we know it doesn't matter whether PC-based reference or GOT-
based. As for this case, both will work before/after relocation. But let's
fix the code.

This patch explicitly sets up a target address, then jump there.
Here's an example of disassembled code with/without this patch.

 90000668:       1485ffef        bne     a0,a1,90000628 
 9000066c:       ac80fffc        sw      zero,-4(a0)
 90000670:       01402821        move    a1,t2
-90000674:       0411ffba        bal     90000560 
-90000678:       01803021        move    a2,t4
-9000067c:       01602821        move    a1,t3
-90000680:       0411ffcc        bal     900005b4 
-90000684:       01a03021        move    a2,t5
-90000688:       03000008        jr      t8
-9000068c:       00000000        nop
+90000674:       01803021        move    a2,t4
+90000678:       8f8f83ec        lw      t7,-31764(gp)
+9000067c:       01e0f809        jalr    t7
+90000680:       00000000        nop
+90000684:       01602821        move    a1,t3
+90000688:       01a03021        move    a2,t5
+9000068c:       8f8f81e0        lw      t7,-32288(gp)
+90000690:       01e0f809        jalr    t7
+90000694:       00000000        nop
+90000698:       03000008        jr      t8
+9000069c:       00000000        nop

Signed-off-by: Shinya Kuribayashi

[MIPS] cpu/mips/cache.S: Add dcache_enable

2008-05-03T04:51:28+00:00

Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482,
"allow ports to override bootelf behavior") requires ports to have this
function.

Signed-off-by: Shinya Kuribayashi 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD

Use jr as register jump instruction

2008-04-18T07:47:29+00:00

Current assembler codes are inconsistent in the way of register jump
instruction usage; some use jr, some use j. Of course GNU as allows both
usages, but as can be expected from `Jump Register' the mnemonic `jr' is
more intuitive than `j'. For example, Linux doesn't have `j ' usage
at all.

Signed-off-by: Shinya Kuribayashi

[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB

2008-03-25T12:30:07+00:00

Signed-off-by: Shinya Kuribayashi

[MIPS] Fix dcache_status()

2008-03-25T12:30:07+00:00

You can't judge UNCACHED by Config.K0 LSB.

Signed-off-by: Shinya Kuribayashi

[MIPS] Fix I-/D-cache initialization loops

2008-03-25T12:30:06+00:00

Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.

In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.

Signed-off-by: Shinya Kuribayashi

[MIPS] Replace memory clearance code with f_fill64

2008-03-25T12:30:06+00:00

This routine fills memory with zero by 64 bytes, and is 64-bit capable.

Signed-off-by: Shinya Kuribayashi