u-boot.git/board/freescale/mx7ulp_evk, branch master

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42+00:00

Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include  at all, so
remove that include.

Signed-off-by: Simon Glass 
Signed-off-by: Tom Rini

treewide: convert bd_t to struct bd_info by coccinelle

2020-07-17T13:30:13+00:00

The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include 

  #include 
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  

Signed-off-by: Masahiro Yamada

common: Drop init.h from common header

2020-05-18T21:33:33+00:00

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass

mx7ulp_evk: Use imx_ddr_size()

2019-10-14T07:31:41+00:00

Use imx_ddr_size() to retrieve the total DDR size instead
of passing a hardcoded memory size.

imx_ddr_size() calculates the memory size based on the actual
MMDC registers values and is useful to detect misconfigurations,
so switch to this more robust approach.

Signed-off-by: Fabio Estevam

imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB

2019-10-08T14:36:37+00:00

CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.

Signed-off-by: Stefano Babic

i.MX7ULP: evk: Modify FDT file to disable SD3.0 for usb boot

2019-10-08T14:35:16+00:00

Since the SD3.0 kernel driver needs M4 image support, this causes
problem for usb boot booting into kernel.  To decouple the relationship,
we modify the FDT file in u-boot to disable SD3.0.
So the kernel won't depend on M4 image.

Signed-off-by: Peng Fan

mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0

2019-07-19T18:14:50+00:00

On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:

	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

	NIC0_DIV:      1
	NIC1_DIV:      0
	LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

	PFD0 FRAC:  27
	APLL MULT:  22
	APLL NUM:   1
	APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li 
Reviewed-by: Peng Fan

mx7ulp: Select the SCG1 APLL PFD as a system clock source

2019-07-19T18:14:50+00:00

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li 
Acked-by: Peng Fan

mx7ulp_evk: Change APLL and its PFD0 frequencies

2019-07-19T18:14:50+00:00

To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li 
Tested-by: Fancy Fang 
Signed-off-by: Peng Fan

mx7ulp_evk: Update LPDDR3 script

2019-07-19T18:14:50+00:00

Update LPDDR3 script with the changes below:
  -Update the precharge command to CMD=01 at the DDR initialization phase
  -remove unimplemented registers
   Write data bit delay --refer to the DDR_TRIM bits in
   IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn

Test:
  One EVK board passes overnight stress test.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan