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<title>u-boot.git/arch/mips/lib, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/'/>
<entry>
<title>common: Drop asm/global_data.h from common header</title>
<updated>2021-02-02T20:33:42+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-31T03:38:53+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=401d1c4f5d2d29c4bc4beaec95402ca23eb63295'/>
<id>401d1c4f5d2d29c4bc4beaec95402ca23eb63295</id>
<content type='text'>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common: board_r: Drop arch-specific ifdefs around initr_trap</title>
<updated>2021-01-15T19:36:12+00:00</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait@windriver.com</email>
</author>
<published>2020-11-28T08:43:18+00:00</published>
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<id>130845bac11ecd542587b2d2ce2b2fe87f112f1d</id>
<content type='text'>
In order to remove the arch-specific ifdefs around initr_trap, introduce
arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have
been moved to arch/&lt;arch&gt;/lib/traps.c

Default implementation is a nop stub.

Signed-off-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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<pre>
In order to remove the arch-specific ifdefs around initr_trap, introduce
arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have
been moved to arch/&lt;arch&gt;/lib/traps.c

Default implementation is a nop stub.

Signed-off-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>global: Move from bi_memstart/memsize -&gt; gd-&gt;ram_base/ram_size</title>
<updated>2020-08-26T07:19:34+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-08-12T11:16:36+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=e207f2256f1fc3d0616608ab75e7dace15b0f9e6'/>
<id>e207f2256f1fc3d0616608ab75e7dace15b0f9e6</id>
<content type='text'>
With the planned removal of bi_memstart &amp; bi_memsize, this patch now
moves the references to the better suiting gd-&gt;ram_base/ram_size
variables.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
With the planned removal of bi_memstart &amp; bi_memsize, this patch now
moves the references to the better suiting gd-&gt;ram_base/ram_size
variables.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: sync asm/mipsregs.h with Linux 5.7</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2020-07-11T23:46:18+00:00</published>
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<id>81d4b14f7e7e4492d99af96c42be7fd8b26eb4d7</id>
<content type='text'>
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom
symbols EBASE_CPUNUM and EBASE_WG with the according symbols
from Linux.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom
symbols EBASE_CPUNUM and EBASE_WG with the according symbols
from Linux.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: remove deprecated UNCACHED_SDRAM() macro</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2020-07-11T23:46:15+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=dd1bb42305033b77032099ce03cbed6bdbb74612'/>
<id>dd1bb42305033b77032099ce03cbed6bdbb74612</id>
<content type='text'>
This macro only served as a wrapper for CKSEG1ADDR() with an
exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus
use CKSEG1ADDR() directly.

This also prepares for an upcoming asm header sync with Linux.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This macro only served as a wrapper for CKSEG1ADDR() with an
exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus
use CKSEG1ADDR() directly.

This also prepares for an upcoming asm header sync with Linux.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: refactor disabling of caches</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2020-07-11T22:45:56+00:00</published>
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<id>60772433dd42987f3b965188d9577150084b8956</id>
<content type='text'>
Logically this code belongs to cache_init.S.

If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
Logically this code belongs to cache_init.S.

If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: add KSEG1 wrapper for change_k0_cca</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2020-07-11T22:45:55+00:00</published>
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<id>b55e07e5656c6838a14453705e90189908ad7d92</id>
<content type='text'>
change_k0_cca() is called multiple times. Move the code for
changing to KSEG1 to a macro to avoid code duplication.

Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
change_k0_cca() is called multiple times. Move the code for
changing to KSEG1 to a macro to avoid code duplication.

Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Tested-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: cache: Make invalidate_dcache_range() weak to enable overwrite</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-06-30T10:33:19+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=60a0559b7fe9bdb9433dc39c42e3e12c4363d63e'/>
<id>60a0559b7fe9bdb9433dc39c42e3e12c4363d63e</id>
<content type='text'>
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: cache: Make flush_cache() weak to enable overwrite</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-05-14T09:59:04+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=1d4ba15c6fe1265c5964cce3436fd501b14bae3b'/>
<id>1d4ba15c6fe1265c5964cce3436fd501b14bae3b</id>
<content type='text'>
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-05-14T09:59:03+00:00</published>
<link rel='alternate' type='text/html' href='https://fedorapeople.org/cgit/ausil/public_git/u-boot.git/commit/?id=2eed3dca229e97aa03954ee5178457c4f2f8cfdb'/>
<id>2eed3dca229e97aa03954ee5178457c4f2f8cfdb</id>
<content type='text'>
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
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