struct arm_opcode { unsigned long arch; const char *assembler; }; struct arm_reg { unsigned long arch; const char *assembler; }; enum arm_arch { ARM_NONE, ARM_GENERIC, ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M, ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP, ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM, ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP, ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK, ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG, FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD, FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3, FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA }; static const struct arm_reg arm_regs[] = { {ARM_GENERIC, "R0"}, {ARM_GENERIC, "R1"}, {ARM_GENERIC, "R2"}, {ARM_GENERIC, "R3"}, {ARM_GENERIC, "R4"}, {ARM_GENERIC, "R5"}, {ARM_GENERIC, "R6"}, {ARM_GENERIC, "R7"}, {ARM_GENERIC, "R8"}, {ARM_GENERIC, "R9"}, {ARM_GENERIC, "R10"}, {ARM_GENERIC, "R11"}, {ARM_GENERIC, "R12"}, {ARM_GENERIC, "R13"}, /* SVC, IRQ, FIQ transparent */ {ARM_GENERIC, "R14"}, /* SVC, IRQ, FIQ transparent */ {ARM_GENERIC, "R15"}, {ARM_GENERIC, "FP"}, {ARM_GENERIC, "IP"}, {ARM_GENERIC, "SP"}, {ARM_GENERIC, "LR"}, {ARM_GENERIC, "PC"}, {ARM_GENERIC, "APSR"}, {ARM_GENERIC, "SPSR"}, {ARM_GENERIC, "CPSR"}, {ARM_GENERIC, "A1"}, {ARM_GENERIC, "A2"}, {ARM_GENERIC, "A3"}, {ARM_GENERIC, "A4"}, {ARM_GENERIC, "V1"}, {ARM_GENERIC, "V2"}, {ARM_GENERIC, "V3"}, {ARM_GENERIC, "V4"}, {ARM_GENERIC, "V5"}, {ARM_GENERIC, "V6"}, {ARM_GENERIC, "V7"}, {ARM_GENERIC, "V8"}, {0, 0} }; static const struct arm_opcode arm_opcodes[] = { {ARM_CEXT_IWMMXT, "tandc"}, {ARM_CEXT_MAVERICK, "cfabs32"}, {ARM_CEXT_MAVERICK, "cfabs64"}, {ARM_CEXT_MAVERICK, "cfabsd"}, {ARM_CEXT_MAVERICK, "cfabss"}, {ARM_CEXT_MAVERICK, "cfadd32"}, {ARM_CEXT_MAVERICK, "cfadd64"}, {ARM_CEXT_MAVERICK, "cfaddd"}, {ARM_CEXT_MAVERICK, "cfadds"}, {ARM_CEXT_MAVERICK, "cfcmp32"}, {ARM_CEXT_MAVERICK, "cfcmp64"}, {ARM_CEXT_MAVERICK, "cfcmpd"}, {ARM_CEXT_MAVERICK, "cfcmps"}, {ARM_CEXT_MAVERICK, "cfcpyd"}, {ARM_CEXT_MAVERICK, "cfcpys"}, {ARM_CEXT_MAVERICK, "cfcvt32d"}, {ARM_CEXT_MAVERICK, "cfcvt32s"}, {ARM_CEXT_MAVERICK, "cfcvt64d"}, {ARM_CEXT_MAVERICK, "cfcvt64s"}, {ARM_CEXT_MAVERICK, "cfcvtd32"}, {ARM_CEXT_MAVERICK, "cfcvtds"}, {ARM_CEXT_MAVERICK, "cfcvts32"}, {ARM_CEXT_MAVERICK, "cfcvtsd"}, {ARM_CEXT_MAVERICK, "cfldr32"}, {ARM_CEXT_MAVERICK, "cfldr64"}, {ARM_CEXT_MAVERICK, "cfldrd"}, {ARM_CEXT_MAVERICK, "cfldrd"}, {ARM_CEXT_MAVERICK, "cfldrs"}, {ARM_CEXT_MAVERICK, "cfmac32"}, {ARM_CEXT_MAVERICK, "cfmadd32"}, {ARM_CEXT_MAVERICK, "cfmadda32"}, {ARM_CEXT_MAVERICK, "cfmsc32"}, {ARM_CEXT_MAVERICK, "cfmsub32"}, {ARM_CEXT_MAVERICK, "cfmsuba32"}, {ARM_CEXT_MAVERICK, "cfmul32"}, {ARM_CEXT_MAVERICK, "cfmul64"}, {ARM_CEXT_MAVERICK, "cfmuld"}, {ARM_CEXT_MAVERICK, "cfmuls"}, {ARM_CEXT_MAVERICK, "cfmv32a"}, {ARM_CEXT_MAVERICK, "cfmv32ah"}, {ARM_CEXT_MAVERICK, "cfmv32al"}, {ARM_CEXT_MAVERICK, "cfmv32am"}, {ARM_CEXT_MAVERICK, "cfmv32sc"}, {ARM_CEXT_MAVERICK, "cfmv64a"}, {ARM_CEXT_MAVERICK, "cfmv64hr"}, {ARM_CEXT_MAVERICK, "cfmv64lr"}, {ARM_CEXT_MAVERICK, "cfmva32"}, {ARM_CEXT_MAVERICK, "cfmva64"}, {ARM_CEXT_MAVERICK, "cfmvah32"}, {ARM_CEXT_MAVERICK, "cfmval32"}, {ARM_CEXT_MAVERICK, "cfmvam32"}, {ARM_CEXT_MAVERICK, "cfmvdhr"}, {ARM_CEXT_MAVERICK, "cfmvdlr"}, {ARM_CEXT_MAVERICK, "cfmvr64h"}, {ARM_CEXT_MAVERICK, "cfmvr64l"}, {ARM_CEXT_MAVERICK, "cfmvrdh"}, {ARM_CEXT_MAVERICK, "cfmvrdl"}, {ARM_CEXT_MAVERICK, "cfmvrs"}, {ARM_CEXT_MAVERICK, "cfmvsc32"}, {ARM_CEXT_MAVERICK, "cfmvsr"}, {ARM_CEXT_MAVERICK, "cfneg32"}, {ARM_CEXT_MAVERICK, "cfneg64"}, {ARM_CEXT_MAVERICK, "cfnegd"}, {ARM_CEXT_MAVERICK, "cfnegs"}, {ARM_CEXT_MAVERICK, "cfrshl32"}, {ARM_CEXT_MAVERICK, "cfrshl64"}, {ARM_CEXT_MAVERICK, "cfsh32"}, {ARM_CEXT_MAVERICK, "cfsh64"}, {ARM_CEXT_MAVERICK, "cfstr32"}, {ARM_CEXT_MAVERICK, "cfstr64"}, {ARM_CEXT_MAVERICK, "cfstrd"}, {ARM_CEXT_MAVERICK, "cfstrs"}, {ARM_CEXT_MAVERICK, "cfsub32"}, {ARM_CEXT_MAVERICK, "cfsub64"}, {ARM_CEXT_MAVERICK, "cfsubd"}, {ARM_CEXT_MAVERICK, "cfsubs"}, {ARM_CEXT_MAVERICK, "cftruncd32"}, {ARM_CEXT_MAVERICK, "cftruncs32"}, {ARM_CEXT_XSCALE, "mar"}, {ARM_CEXT_XSCALE, "mia"}, {ARM_CEXT_XSCALE, "miaph"}, {ARM_CEXT_XSCALE, "mra"}, {ARM_CEXT_XSCALE, "tbcst"}, {ARM_CEXT_XSCALE, "textrc"}, {ARM_CEXT_XSCALE, "textrm"}, {ARM_CEXT_XSCALE, "tinsr"}, {ARM_CEXT_XSCALE, "tmcr"}, {ARM_CEXT_XSCALE, "tmcrr"}, {ARM_CEXT_XSCALE, "tmia"}, {ARM_CEXT_XSCALE, "tmiaph"}, {ARM_CEXT_XSCALE, "tmovmsk"}, {ARM_CEXT_XSCALE, "tmrc"}, {ARM_CEXT_XSCALE, "tmrrc"}, {ARM_CEXT_XSCALE, "torc"}, {ARM_CEXT_XSCALE, "torvsc"}, {ARM_CEXT_XSCALE, "wabs"}, {ARM_CEXT_XSCALE, "wabsdiff"}, {ARM_CEXT_XSCALE, "wacc"}, {ARM_CEXT_XSCALE, "wadd"}, {ARM_CEXT_XSCALE, "waddbhus"}, {ARM_CEXT_XSCALE, "waddsubhx"}, {ARM_CEXT_XSCALE, "waligni"}, {ARM_CEXT_XSCALE, "walignr"}, {ARM_CEXT_XSCALE, "wand"}, {ARM_CEXT_XSCALE, "wavg2"}, {ARM_CEXT_XSCALE, "wavg4"}, {ARM_CEXT_XSCALE, "wcmpeq"}, {ARM_CEXT_XSCALE, "wcmpgt"}, {ARM_CEXT_XSCALE, "wldr"}, {ARM_CEXT_XSCALE, "wldrd"}, {ARM_CEXT_XSCALE, "wldrw"}, {ARM_CEXT_XSCALE, "wmac"}, {ARM_CEXT_XSCALE, "wmadd"}, {ARM_CEXT_XSCALE, "wmax"}, {ARM_CEXT_XSCALE, "wmerge"}, {ARM_CEXT_XSCALE, "wmia"}, {ARM_CEXT_XSCALE, "wmiaw"}, {ARM_CEXT_XSCALE, "wmin"}, {ARM_CEXT_XSCALE, "wmul"}, {ARM_CEXT_XSCALE, "wmulwl"}, {ARM_CEXT_XSCALE, "wmulwsm"}, {ARM_CEXT_XSCALE, "wmulwum"}, {ARM_CEXT_XSCALE, "wor"}, {ARM_CEXT_XSCALE, "wpack"}, {ARM_CEXT_XSCALE, "wqmia"}, {ARM_CEXT_XSCALE, "wqmulm"}, {ARM_CEXT_XSCALE, "wqmulwm"}, {ARM_CEXT_XSCALE, "wror"}, {ARM_CEXT_XSCALE, "wsad"}, {ARM_CEXT_XSCALE, "wshufh"}, {ARM_CEXT_XSCALE, "wsll"}, {ARM_CEXT_XSCALE, "wsra"}, {ARM_CEXT_XSCALE, "wsrl"}, {ARM_CEXT_XSCALE, "wstr"}, {ARM_CEXT_XSCALE, "wstrd"}, {ARM_CEXT_XSCALE, "wstrw"}, {ARM_CEXT_XSCALE, "wsub"}, {ARM_CEXT_XSCALE, "wsubaddhx"}, {ARM_CEXT_XSCALE, "wunpckeh"}, {ARM_CEXT_XSCALE, "wunpckel"}, {ARM_CEXT_XSCALE, "wunpckih"}, {ARM_CEXT_XSCALE, "wunpckil"}, {ARM_CEXT_XSCALE, "wxor"}, {ARM_EXT_ADIV, "sdiv"}, {ARM_EXT_ADIV, "udiv"}, {ARM_EXT_DIV, "sdiv"}, {ARM_EXT_DIV, "udiv"}, {ARM_EXT_MP, "pldw"}, {ARM_EXT_SEC, "smc"}, {ARM_EXT_V1, "adc"}, {ARM_EXT_V1, "add"}, {ARM_EXT_V1, "and"}, {ARM_EXT_V1, "asr"}, {ARM_EXT_V1, "b"}, {ARM_EXT_V1, "bic"}, {ARM_EXT_V1, "cmn"}, {ARM_EXT_V1, "cmp"}, {ARM_EXT_V1, "eor"}, {ARM_EXT_V1, "ldm"}, {ARM_EXT_V1, "ldmfd"}, {ARM_EXT_V1, "ldr"}, {ARM_EXT_V1, "ldrb"}, {ARM_EXT_V1, "ldrt"}, {ARM_EXT_V1, "lsl"}, {ARM_EXT_V1, "lsr"}, {ARM_EXT_V1, "mov"}, {ARM_EXT_V1, "mvn"}, {ARM_EXT_V1, "nop"}, {ARM_EXT_V1, "orr"}, {ARM_EXT_V1, "pop"}, {ARM_EXT_V1, "push"}, {ARM_EXT_V1, "ror"}, {ARM_EXT_V1, "rrx"}, {ARM_EXT_V1, "rsb"}, {ARM_EXT_V1, "rsc"}, {ARM_EXT_V1, "sbc"}, {ARM_EXT_V1, "stm"}, {ARM_EXT_V1, "stmfd"}, {ARM_EXT_V1, "str"}, {ARM_EXT_V1, "strb"}, {ARM_EXT_V1, "strh"}, {ARM_EXT_V1, "sub"}, {ARM_EXT_V1, "svc"}, {ARM_EXT_V1, "teq"}, {ARM_EXT_V1, "tst"}, {ARM_EXT_V2, "cdp"}, {ARM_EXT_V2, "ldc"}, {ARM_EXT_V2, "mcr"}, {ARM_EXT_V2, "mla"}, {ARM_EXT_V2, "mrc"}, {ARM_EXT_V2, "mul"}, {ARM_EXT_V2S, "swp"}, {ARM_EXT_V2, "stc"}, {ARM_EXT_V3, "mrs"}, {ARM_EXT_V3, "msr"}, {ARM_EXT_V4T, "adc"}, {ARM_EXT_V4T, "add"}, {ARM_EXT_V4T, "and"}, {ARM_EXT_V4T | ARM_EXT_V5, "bx"}, {ARM_EXT_V4T, "asr"}, {ARM_EXT_V4T, "b"}, {ARM_EXT_V4T, "bic"}, {ARM_EXT_V4T, "bl"}, {ARM_EXT_V4T, "blx"}, {ARM_EXT_V4T, "bx"}, {ARM_EXT_V4T, "cmn"}, {ARM_EXT_V4T, "cmp"}, {ARM_EXT_V4T, "eor"}, {ARM_EXT_V4T, "ldmia"}, {ARM_EXT_V4T, "ldr"}, {ARM_EXT_V4T, "ldrb"}, {ARM_EXT_V4T, "ldrh"}, {ARM_EXT_V4T, "ldrs"}, {ARM_EXT_V4T, "lsl"}, {ARM_EXT_V4T, "lsr"}, {ARM_EXT_V4T, "mov"}, {ARM_EXT_V4T, "mul"}, {ARM_EXT_V4T, "mvn"}, {ARM_EXT_V4T, "neg"}, {ARM_EXT_V4T, "nop"}, {ARM_EXT_V4T, "orr"}, {ARM_EXT_V4T, "pop"}, {ARM_EXT_V4T, "push"}, {ARM_EXT_V4T, "ror"}, {ARM_EXT_V4T, "sbc"}, {ARM_EXT_V4T, "stmia"}, {ARM_EXT_V4T, "str"}, {ARM_EXT_V4T, "strb"}, {ARM_EXT_V4T, "strh"}, {ARM_EXT_V4T, "sub"}, {ARM_EXT_V4T, "svc"}, {ARM_EXT_V4T, "tst"}, {ARM_EXT_V5, "bkpt"}, {ARM_EXT_V5, "blx"}, {ARM_EXT_V5, "cdp2"}, {ARM_EXT_V5, "clz"}, {ARM_EXT_V5E, "ldrd"}, {ARM_EXT_V5E, "mcrr"}, {ARM_EXT_V5E, "mrrc"}, {ARM_EXT_V5E, "pld"}, {ARM_EXT_V5E, "strd"}, {ARM_EXT_V5ExP, "qadd"}, {ARM_EXT_V5ExP, "qdadd"}, {ARM_EXT_V5ExP, "qdsub"}, {ARM_EXT_V5ExP, "qsub"}, {ARM_EXT_V5ExP, "smlabb"}, {ARM_EXT_V5ExP, "smlabt"}, {ARM_EXT_V5ExP, "smlalbb"}, {ARM_EXT_V5ExP, "smlalbt"}, {ARM_EXT_V5ExP, "smlaltb"}, {ARM_EXT_V5ExP, "smlaltt"}, {ARM_EXT_V5ExP, "smlatb"}, {ARM_EXT_V5ExP, "smlatt"}, {ARM_EXT_V5ExP, "smlawb"}, {ARM_EXT_V5ExP, "smlawt"}, {ARM_EXT_V5ExP, "smulbb"}, {ARM_EXT_V5ExP, "smulbt"}, {ARM_EXT_V5ExP, "smultb"}, {ARM_EXT_V5ExP, "smultt"}, {ARM_EXT_V5ExP, "smulwb"}, {ARM_EXT_V5ExP, "smulwt"}, {ARM_EXT_V5J, "bxj"}, {ARM_EXT_V5, "ldc2"}, {ARM_EXT_V5, "mcr2"}, {ARM_EXT_V5, "mrc2"}, {ARM_EXT_V5, "stc2"}, {ARM_EXT_V5T, "bkpt"}, {ARM_EXT_V5T, "blx"}, {ARM_EXT_V6, "cps"}, {ARM_EXT_V6, "cpsid"}, {ARM_EXT_V6, "cpsie"}, {ARM_EXT_V6K, "clrex"}, {ARM_EXT_V6K, "ldrexb"}, {ARM_EXT_V6K, "ldrexd"}, {ARM_EXT_V6K, "ldrexh"}, {ARM_EXT_V6K, "nop"}, {ARM_EXT_V6K, "sev"}, {ARM_EXT_V6K, "strexb"}, {ARM_EXT_V6K, "strexd"}, {ARM_EXT_V6K, "strexh"}, {ARM_EXT_V6K, "wfe"}, {ARM_EXT_V6K, "wfi"}, {ARM_EXT_V6K, "yield"}, {ARM_EXT_V6, "ldrex"}, {ARM_EXT_V6, "mcrr2"}, {ARM_EXT_V6, "mov"}, {ARM_EXT_V6, "mrrc2"}, {ARM_EXT_V6, "pkhbt"}, {ARM_EXT_V6, "pkhtb"}, {ARM_EXT_V6, "qadd16"}, {ARM_EXT_V6, "qadd8"}, {ARM_EXT_V6, "qasx"}, {ARM_EXT_V6, "qsax"}, {ARM_EXT_V6, "qsub16"}, {ARM_EXT_V6, "qsub8"}, {ARM_EXT_V6, "rev"}, {ARM_EXT_V6, "rev16"}, {ARM_EXT_V6, "revsh"}, {ARM_EXT_V6, "rfe"}, {ARM_EXT_V6, "sadd16"}, {ARM_EXT_V6, "sadd8"}, {ARM_EXT_V6, "sasx"}, {ARM_EXT_V6, "sel"}, {ARM_EXT_V6, "setend"}, {ARM_EXT_V6, "shadd16"}, {ARM_EXT_V6, "shadd8"}, {ARM_EXT_V6, "shasx"}, {ARM_EXT_V6, "shsax"}, {ARM_EXT_V6, "shsub16"}, {ARM_EXT_V6, "shsub8"}, {ARM_EXT_V6, "smlad"}, {ARM_EXT_V6, "smlald"}, {ARM_EXT_V6, "smlsd"}, {ARM_EXT_V6, "smlsld"}, {ARM_EXT_V6, "smmla"}, {ARM_EXT_V6, "smmls"}, {ARM_EXT_V6, "smmul"}, {ARM_EXT_V6, "smuad"}, {ARM_EXT_V6, "smusd"}, {ARM_EXT_V6, "srs"}, {ARM_EXT_V6, "ssat"}, {ARM_EXT_V6, "ssat16"}, {ARM_EXT_V6, "ssax"}, {ARM_EXT_V6, "ssub16"}, {ARM_EXT_V6, "ssub8"}, {ARM_EXT_V6, "strex"}, {ARM_EXT_V6, "sxtab"}, {ARM_EXT_V6, "sxtab16"}, {ARM_EXT_V6, "sxtah"}, {ARM_EXT_V6, "sxtb"}, {ARM_EXT_V6, "sxtb16"}, {ARM_EXT_V6, "sxth"}, {ARM_EXT_V6T2, "adc"}, {ARM_EXT_V6T2, "add"}, {ARM_EXT_V6T2, "addw"}, {ARM_EXT_V6T2, "and"}, {ARM_EXT_V6T2, "asr"}, {ARM_EXT_V6T2, "b"}, {ARM_EXT_V6T2, "bfc"}, {ARM_EXT_V6T2, "bfi"}, {ARM_EXT_V6T2, "bic"}, {ARM_EXT_V6T2, "bxj"}, {ARM_EXT_V6T2, "cbnz"}, {ARM_EXT_V6T2, "cbz"}, {ARM_EXT_V6T2, "clrex"}, {ARM_EXT_V6T2, "clz"}, {ARM_EXT_V6T2, "cmn"}, {ARM_EXT_V6T2, "cmp"}, {ARM_EXT_V6T2, "cps"}, {ARM_EXT_V6T2, "cpsid"}, {ARM_EXT_V6T2, "cpsid.w"}, {ARM_EXT_V6T2, "cpsie"}, {ARM_EXT_V6T2, "cpsie.w"}, {ARM_EXT_V6T2, "eor"}, {ARM_EXT_V6T2, "it"}, {ARM_EXT_V6T2, "ldmdb"}, {ARM_EXT_V6T2, "ldmia"}, {ARM_EXT_V6T2, "ldr"}, {ARM_EXT_V6T2, "ldrd"}, {ARM_EXT_V6T2, "ldrex"}, {ARM_EXT_V6T2, "ldrexd"}, {ARM_EXT_V6T2, "lsl"}, {ARM_EXT_V6T2, "lsr"}, {ARM_EXT_V6T2, "mla"}, {ARM_EXT_V6T2, "mls"}, {ARM_EXT_V6T2, "mov"}, {ARM_EXT_V6T2, "movt"}, {ARM_EXT_V6T2, "movw"}, {ARM_EXT_V6T2, "mrs"}, {ARM_EXT_V6T2, "msr"}, {ARM_EXT_V6T2, "mul"}, {ARM_EXT_V6T2, "mvn"}, {ARM_EXT_V6T2, "nop"}, {ARM_EXT_V6T2, "orn"}, {ARM_EXT_V6T2, "orr"}, {ARM_EXT_V6T2, "pkhbt"}, {ARM_EXT_V6T2, "pkhtb"}, {ARM_EXT_V6T2, "pld"}, {ARM_EXT_V6T2, "qadd"}, {ARM_EXT_V6T2, "qadd16"}, {ARM_EXT_V6T2, "qadd8"}, {ARM_EXT_V6T2, "qasx"}, {ARM_EXT_V6T2, "qdadd"}, {ARM_EXT_V6T2, "qdsub"}, {ARM_EXT_V6T2, "qsax"}, {ARM_EXT_V6T2, "qsub"}, {ARM_EXT_V6T2, "qsub16"}, {ARM_EXT_V6T2, "qsub8"}, {ARM_EXT_V6T2, "rbit"}, {ARM_EXT_V6T2, "rev"}, {ARM_EXT_V6T2, "rev16"}, {ARM_EXT_V6T2, "revsh"}, {ARM_EXT_V6T2, "rfedb"}, {ARM_EXT_V6T2, "rfeia"}, {ARM_EXT_V6T2, "ror"}, {ARM_EXT_V6T2, "rsb"}, {ARM_EXT_V6T2, "sadd16"}, {ARM_EXT_V6T2, "sadd8"}, {ARM_EXT_V6T2, "sasx"}, {ARM_EXT_V6T2, "sbc"}, {ARM_EXT_V6T2, "sbfx"}, {ARM_EXT_V6T2, "sel"}, {ARM_EXT_V6T2, "sev"}, {ARM_EXT_V6T2, "shadd16"}, {ARM_EXT_V6T2, "shadd8"}, {ARM_EXT_V6T2, "shasx"}, {ARM_EXT_V6T2, "shsax"}, {ARM_EXT_V6T2, "shsub16"}, {ARM_EXT_V6T2, "shsub8"}, {ARM_EXT_V6T2, "smla"}, {ARM_EXT_V6T2, "smlad"}, {ARM_EXT_V6T2, "smlal"}, {ARM_EXT_V6T2, "smlald"}, {ARM_EXT_V6T2, "smlaw"}, {ARM_EXT_V6T2, "smlsd"}, {ARM_EXT_V6T2, "smlsld"}, {ARM_EXT_V6T2, "smmla"}, {ARM_EXT_V6T2, "smmls"}, {ARM_EXT_V6T2, "smmul"}, {ARM_EXT_V6T2, "smuad"}, {ARM_EXT_V6T2, "smul"}, {ARM_EXT_V6T2, "smull"}, {ARM_EXT_V6T2, "smulw"}, {ARM_EXT_V6T2, "smusd"}, {ARM_EXT_V6T2, "srsdb"}, {ARM_EXT_V6T2, "srsia"}, {ARM_EXT_V6T2, "ssat"}, {ARM_EXT_V6T2, "ssat16"}, {ARM_EXT_V6T2, "ssax"}, {ARM_EXT_V6T2, "ssub16"}, {ARM_EXT_V6T2, "ssub8"}, {ARM_EXT_V6T2, "stmdb"}, {ARM_EXT_V6T2, "stmia"}, {ARM_EXT_V6T2, "str"}, {ARM_EXT_V6T2, "strd"}, {ARM_EXT_V6T2, "strex"}, {ARM_EXT_V6T2, "strexd"}, {ARM_EXT_V6T2, "strht"}, {ARM_EXT_V6T2, "sub"}, {ARM_EXT_V6T2, "subs"}, {ARM_EXT_V6T2, "subw"}, {ARM_EXT_V6T2, "sxtab"}, {ARM_EXT_V6T2, "sxtab16"}, {ARM_EXT_V6T2, "sxtah"}, {ARM_EXT_V6T2, "sxtb"}, {ARM_EXT_V6T2, "sxtb16"}, {ARM_EXT_V6T2, "sxth"}, {ARM_EXT_V6T2, "tbb"}, {ARM_EXT_V6T2, "tbh"}, {ARM_EXT_V6T2, "teq"}, {ARM_EXT_V6T2, "tst"}, {ARM_EXT_V6T2, "uadd16"}, {ARM_EXT_V6T2, "uadd8"}, {ARM_EXT_V6T2, "uasx"}, {ARM_EXT_V6T2, "ubfx"}, {ARM_EXT_V6T2, "uhadd16"}, {ARM_EXT_V6T2, "uhadd8"}, {ARM_EXT_V6T2, "uhasx"}, {ARM_EXT_V6T2, "uhsax"}, {ARM_EXT_V6T2, "uhsub16"}, {ARM_EXT_V6T2, "uhsub8"}, {ARM_EXT_V6T2, "umaal"}, {ARM_EXT_V6T2, "umlal"}, {ARM_EXT_V6T2, "umull"}, {ARM_EXT_V6T2, "uqadd16"}, {ARM_EXT_V6T2, "uqadd8"}, {ARM_EXT_V6T2, "uqasx"}, {ARM_EXT_V6T2, "uqsax"}, {ARM_EXT_V6T2, "uqsub16"}, {ARM_EXT_V6T2, "uqsub8"}, {ARM_EXT_V6T2, "usad8"}, {ARM_EXT_V6T2, "usada8"}, {ARM_EXT_V6T2, "usat"}, {ARM_EXT_V6T2, "usat16"}, {ARM_EXT_V6T2, "usax"}, {ARM_EXT_V6T2, "usub16"}, {ARM_EXT_V6T2, "usub8"}, {ARM_EXT_V6T2, "uxtab"}, {ARM_EXT_V6T2, "uxtab16"}, {ARM_EXT_V6T2, "uxtah"}, {ARM_EXT_V6T2, "uxtb"}, {ARM_EXT_V6T2, "uxtb16"}, {ARM_EXT_V6T2, "uxth"}, {ARM_EXT_V6T2, "wfe"}, {ARM_EXT_V6T2, "wfi"}, {ARM_EXT_V6T2, "yield"}, {ARM_EXT_V6, "uadd16"}, {ARM_EXT_V6, "uadd8"}, {ARM_EXT_V6, "uasx"}, {ARM_EXT_V6, "uhadd16"}, {ARM_EXT_V6, "uhadd8"}, {ARM_EXT_V6, "uhasx"}, {ARM_EXT_V6, "uhsax"}, {ARM_EXT_V6, "uhsub16"}, {ARM_EXT_V6, "uhsub8"}, {ARM_EXT_V6, "umaal"}, {ARM_EXT_V6, "uqadd16"}, {ARM_EXT_V6, "uqadd8"}, {ARM_EXT_V6, "uqasx"}, {ARM_EXT_V6, "uqsax"}, {ARM_EXT_V6, "uqsub16"}, {ARM_EXT_V6, "uqsub8"}, {ARM_EXT_V6, "usad8"}, {ARM_EXT_V6, "usada8"}, {ARM_EXT_V6, "usat"}, {ARM_EXT_V6, "usat16"}, {ARM_EXT_V6, "usax"}, {ARM_EXT_V6, "usub16"}, {ARM_EXT_V6, "usub8"}, {ARM_EXT_V6, "uxtab"}, {ARM_EXT_V6, "uxtab16"}, {ARM_EXT_V6, "uxtah"}, {ARM_EXT_V6, "uxtb"}, {ARM_EXT_V6, "uxtb16"}, {ARM_EXT_V6, "uxth"}, {ARM_EXT_V7, "dbg"}, {ARM_EXT_V7, "dmb"}, {ARM_EXT_V7, "dsb"}, {ARM_EXT_V7, "isb"}, {ARM_EXT_V7, "pli"}, {ARM_EXT_VIRT, "eret"}, {ARM_EXT_VIRT, "hvc"}, {ARM_EXT_VIRT, "msr"}, {FPU_FPA_EXT_V1, "abs"}, {FPU_FPA_EXT_V1, "acs"}, {FPU_FPA_EXT_V1, "adf"}, {FPU_FPA_EXT_V1, "asn"}, {FPU_FPA_EXT_V1, "atn"}, {FPU_FPA_EXT_V1, "cmf"}, {FPU_FPA_EXT_V1, "cmfe"}, {FPU_FPA_EXT_V1, "cnf"}, {FPU_FPA_EXT_V1, "cnfe"}, {FPU_FPA_EXT_V1, "cos"}, {FPU_FPA_EXT_V1, "dvf"}, {FPU_FPA_EXT_V1, "exp"}, {FPU_FPA_EXT_V1, "fdv"}, {FPU_FPA_EXT_V1, "fix"}, {FPU_FPA_EXT_V1, "flt"}, {FPU_FPA_EXT_V1, "fml"}, {FPU_FPA_EXT_V1, "frd"}, {FPU_FPA_EXT_V1, "ldf"}, {FPU_FPA_EXT_V1, "lgn"}, {FPU_FPA_EXT_V1, "log"}, {FPU_FPA_EXT_V1, "mnf"}, {FPU_FPA_EXT_V1, "muf"}, {FPU_FPA_EXT_V1, "mvf"}, {FPU_FPA_EXT_V1, "nrm"}, {FPU_FPA_EXT_V1, "pol"}, {FPU_FPA_EXT_V1, "pow"}, {FPU_FPA_EXT_V1, "rdf"}, {FPU_FPA_EXT_V1, "rfc"}, {FPU_FPA_EXT_V1, "rfs"}, {FPU_FPA_EXT_V1, "rmf"}, {FPU_FPA_EXT_V1, "rnd"}, {FPU_FPA_EXT_V1, "rpw"}, {FPU_FPA_EXT_V1, "rsf"}, {FPU_FPA_EXT_V1, "sin"}, {FPU_FPA_EXT_V1, "sqt"}, {FPU_FPA_EXT_V1, "stf"}, {FPU_FPA_EXT_V1, "suf"}, {FPU_FPA_EXT_V1, "tan"}, {FPU_FPA_EXT_V1, "urd"}, {FPU_FPA_EXT_V1, "wfc"}, {FPU_FPA_EXT_V1, "wfs"}, {FPU_FPA_EXT_V2, "lfm"}, {FPU_FPA_EXT_V2, "sfm"}, {FPU_NEON_EXT_FMA, "vfma"}, {FPU_NEON_EXT_FMA, "vfms"}, {FPU_NEON_EXT_V1, "vaba"}, {FPU_NEON_EXT_V1, "vabal"}, {FPU_NEON_EXT_V1, "vabd"}, {FPU_NEON_EXT_V1, "vabdl"}, {FPU_NEON_EXT_V1, "vabs"}, {FPU_NEON_EXT_V1, "vacge"}, {FPU_NEON_EXT_V1, "vacgt"}, {FPU_NEON_EXT_V1, "vadd"}, {FPU_NEON_EXT_V1, "vaddhn"}, {FPU_NEON_EXT_V1, "vaddl"}, {FPU_NEON_EXT_V1, "vaddw"}, {FPU_NEON_EXT_V1, "vand"}, {FPU_NEON_EXT_V1, "vbic"}, {FPU_NEON_EXT_V1, "vbif"}, {FPU_NEON_EXT_V1, "vbit"}, {FPU_NEON_EXT_V1, "vbsl"}, {FPU_NEON_EXT_V1, "vceq"}, {FPU_NEON_EXT_V1, "vcge"}, {FPU_NEON_EXT_V1, "vcgt"}, {FPU_NEON_EXT_V1, "vcle"}, {FPU_NEON_EXT_V1, "vcls"}, {FPU_NEON_EXT_V1, "vclt"}, {FPU_NEON_EXT_V1, "vclz"}, {FPU_NEON_EXT_V1, "vcnt"}, {FPU_NEON_EXT_V1, "vcvt"}, {FPU_NEON_EXT_V1, "vdup"}, {FPU_NEON_EXT_V1, "veor"}, {FPU_NEON_EXT_V1, "vext"}, {FPU_NEON_EXT_V1, "vhadd"}, {FPU_NEON_EXT_V1, "vhsub"}, {FPU_NEON_EXT_V1, "vld1"}, {FPU_NEON_EXT_V1, "vld2"}, {FPU_NEON_EXT_V1, "vld3"}, {FPU_NEON_EXT_V1, "vld4"}, {FPU_NEON_EXT_V1, "vmax"}, {FPU_NEON_EXT_V1, "vmin"}, {FPU_NEON_EXT_V1, "vmla"}, {FPU_NEON_EXT_V1, "vmlal"}, {FPU_NEON_EXT_V1, "vmls"}, {FPU_NEON_EXT_V1, "vmlsl"}, {FPU_NEON_EXT_V1, "vmov"}, {FPU_NEON_EXT_V1, "vmovl"}, {FPU_NEON_EXT_V1, "vmovn"}, {FPU_NEON_EXT_V1, "vmul"}, {FPU_NEON_EXT_V1, "vmull"}, {FPU_NEON_EXT_V1, "vmvn"}, {FPU_NEON_EXT_V1, "vneg"}, {FPU_NEON_EXT_V1, "vorn"}, {FPU_NEON_EXT_V1, "vorr"}, {FPU_NEON_EXT_V1, "vpadal"}, {FPU_NEON_EXT_V1, "vpadd"}, {FPU_NEON_EXT_V1, "vpaddl"}, {FPU_NEON_EXT_V1, "vpmax"}, {FPU_NEON_EXT_V1, "vpmin"}, {FPU_NEON_EXT_V1, "vqabs"}, {FPU_NEON_EXT_V1, "vqadd"}, {FPU_NEON_EXT_V1, "vqdmlal"}, {FPU_NEON_EXT_V1, "vqdmlsl"}, {FPU_NEON_EXT_V1, "vqdmulh"}, {FPU_NEON_EXT_V1, "vqdmull"}, {FPU_NEON_EXT_V1, "vqmovn"}, {FPU_NEON_EXT_V1, "vqmovun"}, {FPU_NEON_EXT_V1, "vqneg"}, {FPU_NEON_EXT_V1, "vqrdmulh"}, {FPU_NEON_EXT_V1, "vqrshl"}, {FPU_NEON_EXT_V1, "vqrshrn"}, {FPU_NEON_EXT_V1, "vqrshrun"}, {FPU_NEON_EXT_V1, "vqshl"}, {FPU_NEON_EXT_V1, "vqshlu"}, {FPU_NEON_EXT_V1, "vqshrn"}, {FPU_NEON_EXT_V1, "vqshrun"}, {FPU_NEON_EXT_V1, "vqsub"}, {FPU_NEON_EXT_V1, "vraddhn"}, {FPU_NEON_EXT_V1, "vrecpe"}, {FPU_NEON_EXT_V1, "vrecps"}, {FPU_NEON_EXT_V1, "vrev16"}, {FPU_NEON_EXT_V1, "vrev32"}, {FPU_NEON_EXT_V1, "vrev64"}, {FPU_NEON_EXT_V1, "vrhadd"}, {FPU_NEON_EXT_V1, "vrshl"}, {FPU_NEON_EXT_V1, "vrshr"}, {FPU_NEON_EXT_V1, "vrshrn"}, {FPU_NEON_EXT_V1, "vrsqrte"}, {FPU_NEON_EXT_V1, "vrsqrts"}, {FPU_NEON_EXT_V1, "vrsra"}, {FPU_NEON_EXT_V1, "vrsubhn"}, {FPU_NEON_EXT_V1, "vshl"}, {FPU_NEON_EXT_V1, "vshll"}, {FPU_NEON_EXT_V1, "vshr"}, {FPU_NEON_EXT_V1, "vshrn"}, {FPU_NEON_EXT_V1, "vsli"}, {FPU_NEON_EXT_V1, "vsra"}, {FPU_NEON_EXT_V1, "vsri"}, {FPU_NEON_EXT_V1, "vsub"}, {FPU_NEON_EXT_V1, "vsubhn"}, {FPU_NEON_EXT_V1, "vsubl"}, {FPU_NEON_EXT_V1, "vsubw"}, {FPU_NEON_EXT_V1, "vswp"}, {FPU_NEON_EXT_V1, "vtbl"}, {FPU_NEON_EXT_V1, "vtbx"}, {FPU_NEON_EXT_V1, "vtrn"}, {FPU_NEON_EXT_V1, "vtst"}, {FPU_NEON_EXT_V1, "vuzp"}, {FPU_NEON_EXT_V1, "vzip"}, {FPU_VFP_EXT_FMA, "vfma"}, {FPU_VFP_EXT_FMA, "vfms"}, {FPU_VFP_EXT_FMA, "vfnma"}, {FPU_VFP_EXT_FMA, "vfnms"}, {FPU_VFP_EXT_FP16, "vcvt"}, {FPU_VFP_EXT_V1, "vabs"}, {FPU_VFP_EXT_V1, "vadd"}, {FPU_VFP_EXT_V1, "vcmp"}, {FPU_VFP_EXT_V1, "vcvt"}, {FPU_VFP_EXT_V1, "vdiv"}, {FPU_VFP_EXT_V1, "vmla"}, {FPU_VFP_EXT_V1, "vmls"}, {FPU_VFP_EXT_V1, "vmov"}, {FPU_VFP_EXT_V1, "vmul"}, {FPU_VFP_EXT_V1, "vneg"}, {FPU_VFP_EXT_V1, "vnmla"}, {FPU_VFP_EXT_V1, "vnmls"}, {FPU_VFP_EXT_V1, "vnmul"}, {FPU_VFP_EXT_V1, "vsqrt"}, {FPU_VFP_EXT_V1, "vsub"}, {FPU_VFP_EXT_V1xD, "fldmdbx"}, {FPU_VFP_EXT_V1xD, "fldmiax"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vldmdb"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vldmia"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vldr"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vpop"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vpush"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vstmdb"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vstmia"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, "vstr"}, {FPU_VFP_EXT_V1xD, "fstmdbx"}, {FPU_VFP_EXT_V1xD, "fstmiax"}, {FPU_VFP_EXT_V1xD, "vabs"}, {FPU_VFP_EXT_V1xD, "vadd"}, {FPU_VFP_EXT_V1xD, "vcmp"}, {FPU_VFP_EXT_V1xD, "vcvt"}, {FPU_VFP_EXT_V1xD, "vdiv"}, {FPU_VFP_EXT_V1xD, "vldmdb"}, {FPU_VFP_EXT_V1xD, "vldmia"}, {FPU_VFP_EXT_V1xD, "vldr"}, {FPU_VFP_EXT_V1xD, "vmla"}, {FPU_VFP_EXT_V1xD, "vmls"}, {FPU_VFP_EXT_V1xD, "vmov"}, {FPU_VFP_EXT_V1xD, "vmrs"}, {FPU_VFP_EXT_V1xD, "vmsr"}, {FPU_VFP_EXT_V1xD, "vmul"}, {FPU_VFP_EXT_V1xD, "vneg"}, {FPU_VFP_EXT_V1xD, "vnmla"}, {FPU_VFP_EXT_V1xD, "vnmls"}, {FPU_VFP_EXT_V1xD, "vnmul"}, {FPU_VFP_EXT_V1xD, "vpop"}, {FPU_VFP_EXT_V1xD, "vpush"}, {FPU_VFP_EXT_V1xD, "vsqrt"}, {FPU_VFP_EXT_V1xD, "vstmdb"}, {FPU_VFP_EXT_V1xD, "vstmia"}, {FPU_VFP_EXT_V1xD, "vstr"}, {FPU_VFP_EXT_V1xD, "vsub"}, {FPU_VFP_EXT_V2, "vmov"}, {FPU_VFP_EXT_V3, "vcvt"}, {FPU_VFP_EXT_V3, "vmov"}, {FPU_VFP_EXT_V3xD, "vcvt"}, {FPU_VFP_EXT_V3xD, "vmov"}, {0, 0} };