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-rw-r--r--arch/m68k/include/asm/Kbuild2
-rw-r--r--arch/m68k/include/asm/MC68328.h1266
-rw-r--r--arch/m68k/include/asm/MC68332.h152
-rw-r--r--arch/m68k/include/asm/MC68EZ328.h1253
-rw-r--r--arch/m68k/include/asm/MC68VZ328.h1349
-rw-r--r--arch/m68k/include/asm/a.out-core.h67
-rw-r--r--arch/m68k/include/asm/a.out.h20
-rw-r--r--arch/m68k/include/asm/adb_iop.h44
-rw-r--r--arch/m68k/include/asm/amigahw.h349
-rw-r--r--arch/m68k/include/asm/amigaints.h113
-rw-r--r--arch/m68k/include/asm/amigayle.h113
-rw-r--r--arch/m68k/include/asm/amipcmcia.h110
-rw-r--r--arch/m68k/include/asm/apollodma.h248
-rw-r--r--arch/m68k/include/asm/apollohw.h108
-rw-r--r--arch/m68k/include/asm/asm-offsets.h1
-rw-r--r--arch/m68k/include/asm/atafd.h12
-rw-r--r--arch/m68k/include/asm/atafdreg.h79
-rw-r--r--arch/m68k/include/asm/atari_joystick.h22
-rw-r--r--arch/m68k/include/asm/atari_stdma.h22
-rw-r--r--arch/m68k/include/asm/atari_stram.h16
-rw-r--r--arch/m68k/include/asm/atarihw.h809
-rw-r--r--arch/m68k/include/asm/atariints.h204
-rw-r--r--arch/m68k/include/asm/atarikb.h44
-rw-r--r--arch/m68k/include/asm/atomic.h218
-rw-r--r--arch/m68k/include/asm/auxvec.h4
-rw-r--r--arch/m68k/include/asm/bitops.h530
-rw-r--r--arch/m68k/include/asm/bitsperlong.h1
-rw-r--r--arch/m68k/include/asm/blinken.h32
-rw-r--r--arch/m68k/include/asm/bootinfo.h378
-rw-r--r--arch/m68k/include/asm/bootstd.h132
-rw-r--r--arch/m68k/include/asm/bug.h30
-rw-r--r--arch/m68k/include/asm/bugs.h20
-rw-r--r--arch/m68k/include/asm/bvme6000hw.h150
-rw-r--r--arch/m68k/include/asm/byteorder.h6
-rw-r--r--arch/m68k/include/asm/cache.h13
-rw-r--r--arch/m68k/include/asm/cachectl.h14
-rw-r--r--arch/m68k/include/asm/cacheflush.h5
-rw-r--r--arch/m68k/include/asm/cacheflush_mm.h235
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h79
-rw-r--r--arch/m68k/include/asm/checksum.h149
-rw-r--r--arch/m68k/include/asm/coldfire.h49
-rw-r--r--arch/m68k/include/asm/commproc.h703
-rw-r--r--arch/m68k/include/asm/contregs.h53
-rw-r--r--arch/m68k/include/asm/cputime.h6
-rw-r--r--arch/m68k/include/asm/current.h28
-rw-r--r--arch/m68k/include/asm/dbg.h6
-rw-r--r--arch/m68k/include/asm/delay.h96
-rw-r--r--arch/m68k/include/asm/device.h7
-rw-r--r--arch/m68k/include/asm/div64.h34
-rw-r--r--arch/m68k/include/asm/dma-mapping.h102
-rw-r--r--arch/m68k/include/asm/dma.h491
-rw-r--r--arch/m68k/include/asm/dsp56k.h35
-rw-r--r--arch/m68k/include/asm/dvma.h240
-rw-r--r--arch/m68k/include/asm/elf.h118
-rw-r--r--arch/m68k/include/asm/emergency-restart.h6
-rw-r--r--arch/m68k/include/asm/entry.h262
-rw-r--r--arch/m68k/include/asm/errno.h6
-rw-r--r--arch/m68k/include/asm/fb.h38
-rw-r--r--arch/m68k/include/asm/fbio.h330
-rw-r--r--arch/m68k/include/asm/fcntl.h11
-rw-r--r--arch/m68k/include/asm/flat.h16
-rw-r--r--arch/m68k/include/asm/floppy.h254
-rw-r--r--arch/m68k/include/asm/fpu.h23
-rw-r--r--arch/m68k/include/asm/ftrace.h1
-rw-r--r--arch/m68k/include/asm/futex.h6
-rw-r--r--arch/m68k/include/asm/gpio.h244
-rw-r--r--arch/m68k/include/asm/hardirq.h39
-rw-r--r--arch/m68k/include/asm/hp300hw.h25
-rw-r--r--arch/m68k/include/asm/hw_irq.h6
-rw-r--r--arch/m68k/include/asm/hwtest.h15
-rw-r--r--arch/m68k/include/asm/ide.h66
-rw-r--r--arch/m68k/include/asm/idprom.h27
-rw-r--r--arch/m68k/include/asm/intersil.h48
-rw-r--r--arch/m68k/include/asm/io.h5
-rw-r--r--arch/m68k/include/asm/io_mm.h336
-rw-r--r--arch/m68k/include/asm/io_no.h183
-rw-r--r--arch/m68k/include/asm/ioctl.h1
-rw-r--r--arch/m68k/include/asm/ioctls.h8
-rw-r--r--arch/m68k/include/asm/ipcbuf.h1
-rw-r--r--arch/m68k/include/asm/irq.h76
-rw-r--r--arch/m68k/include/asm/irq_regs.h1
-rw-r--r--arch/m68k/include/asm/irqflags.h78
-rw-r--r--arch/m68k/include/asm/kdebug.h1
-rw-r--r--arch/m68k/include/asm/kmap_types.h6
-rw-r--r--arch/m68k/include/asm/linkage.h7
-rw-r--r--arch/m68k/include/asm/local.h6
-rw-r--r--arch/m68k/include/asm/local64.h1
-rw-r--r--arch/m68k/include/asm/m5206sim.h147
-rw-r--r--arch/m68k/include/asm/m520xsim.h167
-rw-r--r--arch/m68k/include/asm/m523xsim.h177
-rw-r--r--arch/m68k/include/asm/m5249sim.h255
-rw-r--r--arch/m68k/include/asm/m5272sim.h136
-rw-r--r--arch/m68k/include/asm/m527xsim.h295
-rw-r--r--arch/m68k/include/asm/m528xsim.h288
-rw-r--r--arch/m68k/include/asm/m52xxacr.h94
-rw-r--r--arch/m68k/include/asm/m5307sim.h181
-rw-r--r--arch/m68k/include/asm/m532xsim.h2234
-rw-r--r--arch/m68k/include/asm/m53xxacr.h101
-rw-r--r--arch/m68k/include/asm/m5407sim.h144
-rw-r--r--arch/m68k/include/asm/m54xxacr.h127
-rw-r--r--arch/m68k/include/asm/m54xxgpt.h90
-rw-r--r--arch/m68k/include/asm/m54xxsim.h80
-rw-r--r--arch/m68k/include/asm/m68360.h13
-rw-r--r--arch/m68k/include/asm/m68360_enet.h177
-rw-r--r--arch/m68k/include/asm/m68360_pram.h431
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h362
-rw-r--r--arch/m68k/include/asm/m68360_regs.h408
-rw-r--r--arch/m68k/include/asm/mac_asc.h27
-rw-r--r--arch/m68k/include/asm/mac_baboon.h38
-rw-r--r--arch/m68k/include/asm/mac_iop.h164
-rw-r--r--arch/m68k/include/asm/mac_mouse.h23
-rw-r--r--arch/m68k/include/asm/mac_oss.h79
-rw-r--r--arch/m68k/include/asm/mac_psc.h252
-rw-r--r--arch/m68k/include/asm/mac_via.h276
-rw-r--r--arch/m68k/include/asm/machdep.h44
-rw-r--r--arch/m68k/include/asm/machines.h85
-rw-r--r--arch/m68k/include/asm/machw.h24
-rw-r--r--arch/m68k/include/asm/macintosh.h138
-rw-r--r--arch/m68k/include/asm/macints.h143
-rw-r--r--arch/m68k/include/asm/math-emu.h315
-rw-r--r--arch/m68k/include/asm/mc146818rtc.h26
-rw-r--r--arch/m68k/include/asm/mcf_pgalloc.h102
-rw-r--r--arch/m68k/include/asm/mcf_pgtable.h426
-rw-r--r--arch/m68k/include/asm/mcfdma.h121
-rw-r--r--arch/m68k/include/asm/mcfgpio.h40
-rw-r--r--arch/m68k/include/asm/mcfintc.h89
-rw-r--r--arch/m68k/include/asm/mcfmbus.h77
-rw-r--r--arch/m68k/include/asm/mcfmmu.h112
-rw-r--r--arch/m68k/include/asm/mcfne.h242
-rw-r--r--arch/m68k/include/asm/mcfpit.h50
-rw-r--r--arch/m68k/include/asm/mcfqspi.h66
-rw-r--r--arch/m68k/include/asm/mcfsim.h49
-rw-r--r--arch/m68k/include/asm/mcfslt.h44
-rw-r--r--arch/m68k/include/asm/mcftimer.h57
-rw-r--r--arch/m68k/include/asm/mcfuart.h185
-rw-r--r--arch/m68k/include/asm/mcfwdebug.h118
-rw-r--r--arch/m68k/include/asm/mman.h1
-rw-r--r--arch/m68k/include/asm/mmu.h13
-rw-r--r--arch/m68k/include/asm/mmu_context.h327
-rw-r--r--arch/m68k/include/asm/mmzone.h9
-rw-r--r--arch/m68k/include/asm/module.h43
-rw-r--r--arch/m68k/include/asm/motorola_pgalloc.h109
-rw-r--r--arch/m68k/include/asm/motorola_pgtable.h290
-rw-r--r--arch/m68k/include/asm/movs.h55
-rw-r--r--arch/m68k/include/asm/msgbuf.h31
-rw-r--r--arch/m68k/include/asm/mutex.h9
-rw-r--r--arch/m68k/include/asm/mvme147hw.h113
-rw-r--r--arch/m68k/include/asm/mvme16xhw.h111
-rw-r--r--arch/m68k/include/asm/natfeat.h22
-rw-r--r--arch/m68k/include/asm/nettel.h108
-rw-r--r--arch/m68k/include/asm/nubus.h46
-rw-r--r--arch/m68k/include/asm/openprom.h312
-rw-r--r--arch/m68k/include/asm/oplib.h291
-rw-r--r--arch/m68k/include/asm/page.h53
-rw-r--r--arch/m68k/include/asm/page_mm.h179
-rw-r--r--arch/m68k/include/asm/page_no.h40
-rw-r--r--arch/m68k/include/asm/page_offset.h9
-rw-r--r--arch/m68k/include/asm/param.h12
-rw-r--r--arch/m68k/include/asm/parport.h26
-rw-r--r--arch/m68k/include/asm/pci.h12
-rw-r--r--arch/m68k/include/asm/percpu.h6
-rw-r--r--arch/m68k/include/asm/pgalloc.h21
-rw-r--r--arch/m68k/include/asm/pgtable.h5
-rw-r--r--arch/m68k/include/asm/pgtable_mm.h183
-rw-r--r--arch/m68k/include/asm/pgtable_no.h72
-rw-r--r--arch/m68k/include/asm/pinmux.h30
-rw-r--r--arch/m68k/include/asm/poll.h9
-rw-r--r--arch/m68k/include/asm/posix_types.h61
-rw-r--r--arch/m68k/include/asm/processor.h185
-rw-r--r--arch/m68k/include/asm/ptrace.h97
-rw-r--r--arch/m68k/include/asm/q40_master.h69
-rw-r--r--arch/m68k/include/asm/q40ints.h26
-rw-r--r--arch/m68k/include/asm/quicc_simple.h52
-rw-r--r--arch/m68k/include/asm/raw_io.h347
-rw-r--r--arch/m68k/include/asm/resource.h6
-rw-r--r--arch/m68k/include/asm/rtc.h79
-rw-r--r--arch/m68k/include/asm/sbus.h45
-rw-r--r--arch/m68k/include/asm/scatterlist.h6
-rw-r--r--arch/m68k/include/asm/sections.h8
-rw-r--r--arch/m68k/include/asm/segment.h65
-rw-r--r--arch/m68k/include/asm/sembuf.h25
-rw-r--r--arch/m68k/include/asm/serial.h35
-rw-r--r--arch/m68k/include/asm/setup.h390
-rw-r--r--arch/m68k/include/asm/shm.h31
-rw-r--r--arch/m68k/include/asm/shmbuf.h42
-rw-r--r--arch/m68k/include/asm/shmparam.h6
-rw-r--r--arch/m68k/include/asm/sigcontext.h24
-rw-r--r--arch/m68k/include/asm/siginfo.h6
-rw-r--r--arch/m68k/include/asm/signal.h212
-rw-r--r--arch/m68k/include/asm/smp.h1
-rw-r--r--arch/m68k/include/asm/socket.h68
-rw-r--r--arch/m68k/include/asm/sockios.h13
-rw-r--r--arch/m68k/include/asm/spinlock.h6
-rw-r--r--arch/m68k/include/asm/stat.h77
-rw-r--r--arch/m68k/include/asm/statfs.h6
-rw-r--r--arch/m68k/include/asm/string.h119
-rw-r--r--arch/m68k/include/asm/sun3-head.h10
-rw-r--r--arch/m68k/include/asm/sun3_pgalloc.h102
-rw-r--r--arch/m68k/include/asm/sun3_pgtable.h231
-rw-r--r--arch/m68k/include/asm/sun3ints.h37
-rw-r--r--arch/m68k/include/asm/sun3mmu.h171
-rw-r--r--arch/m68k/include/asm/sun3x.h27
-rw-r--r--arch/m68k/include/asm/sun3xflop.h263
-rw-r--r--arch/m68k/include/asm/sun3xprom.h43
-rw-r--r--arch/m68k/include/asm/swab.h27
-rw-r--r--arch/m68k/include/asm/system.h193
-rw-r--r--arch/m68k/include/asm/termbits.h201
-rw-r--r--arch/m68k/include/asm/termios.h92
-rw-r--r--arch/m68k/include/asm/thread_info.h81
-rw-r--r--arch/m68k/include/asm/timex.h31
-rw-r--r--arch/m68k/include/asm/tlb.h20
-rw-r--r--arch/m68k/include/asm/tlbflush.h278
-rw-r--r--arch/m68k/include/asm/topology.h6
-rw-r--r--arch/m68k/include/asm/traps.h272
-rw-r--r--arch/m68k/include/asm/types.h22
-rw-r--r--arch/m68k/include/asm/uaccess.h5
-rw-r--r--arch/m68k/include/asm/uaccess_mm.h390
-rw-r--r--arch/m68k/include/asm/uaccess_no.h181
-rw-r--r--arch/m68k/include/asm/ucontext.h30
-rw-r--r--arch/m68k/include/asm/unaligned.h25
-rw-r--r--arch/m68k/include/asm/unistd.h396
-rw-r--r--arch/m68k/include/asm/user.h86
-rw-r--r--arch/m68k/include/asm/virtconvert.h47
-rw-r--r--arch/m68k/include/asm/xor.h1
-rw-r--r--arch/m68k/include/asm/zorro.h45
225 files changed, 29786 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
new file mode 100644
index 00000000000..1a922fad76f
--- /dev/null
+++ b/arch/m68k/include/asm/Kbuild
@@ -0,0 +1,2 @@
+include include/asm-generic/Kbuild.asm
+header-y += cachectl.h
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h
new file mode 100644
index 00000000000..a337e56d09b
--- /dev/null
+++ b/arch/m68k/include/asm/MC68328.h
@@ -0,0 +1,1266 @@
+
+/* include/asm-m68knommu/MC68328.h: '328 control registers
+ *
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bear & Hare Software, Inc.
+ *
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ *
+ */
+
+#ifndef _MC68328_H_
+#define _MC68328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Mask Revision Register
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * Group Base Address Registers
+ */
+#define GRPBASEA_ADDR 0xfffff100
+#define GRPBASEB_ADDR 0xfffff102
+#define GRPBASEC_ADDR 0xfffff104
+#define GRPBASED_ADDR 0xfffff106
+
+#define GRPBASEA WORD_REF(GRPBASEA_ADDR)
+#define GRPBASEB WORD_REF(GRPBASEB_ADDR)
+#define GRPBASEC WORD_REF(GRPBASEC_ADDR)
+#define GRPBASED WORD_REF(GRPBASED_ADDR)
+
+#define GRPBASE_V 0x0001 /* Valid */
+#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
+
+/*
+ * Group Base Address Mask Registers
+ */
+#define GRPMASKA_ADDR 0xfffff108
+#define GRPMASKB_ADDR 0xfffff10a
+#define GRPMASKC_ADDR 0xfffff10c
+#define GRPMASKD_ADDR 0xfffff10e
+
+#define GRPMASKA WORD_REF(GRPMASKA_ADDR)
+#define GRPMASKB WORD_REF(GRPMASKB_ADDR)
+#define GRPMASKC WORD_REF(GRPMASKC_ADDR)
+#define GRPMASKD WORD_REF(GRPMASKD_ADDR)
+
+#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
+
+/*
+ * Chip-Select Option Registers (group A)
+ */
+#define CSA0_ADDR 0xfffff110
+#define CSA1_ADDR 0xfffff114
+#define CSA2_ADDR 0xfffff118
+#define CSA3_ADDR 0xfffff11c
+
+#define CSA0 LONG_REF(CSA0_ADDR)
+#define CSA1 LONG_REF(CSA1_ADDR)
+#define CSA2 LONG_REF(CSA2_ADDR)
+#define CSA3 LONG_REF(CSA3_ADDR)
+
+#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSA_WAIT_SHIFT 0
+#define CSA_RO 0x00000008 /* Read-Only */
+#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
+#define CSA_AM_SHIFT 8
+#define CSA_BUSW 0x00010000 /* Bus Width Select */
+#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
+#define CSA_AC_SHIFT 24
+
+/*
+ * Chip-Select Option Registers (group B)
+ */
+#define CSB0_ADDR 0xfffff120
+#define CSB1_ADDR 0xfffff124
+#define CSB2_ADDR 0xfffff128
+#define CSB3_ADDR 0xfffff12c
+
+#define CSB0 LONG_REF(CSB0_ADDR)
+#define CSB1 LONG_REF(CSB1_ADDR)
+#define CSB2 LONG_REF(CSB2_ADDR)
+#define CSB3 LONG_REF(CSB3_ADDR)
+
+#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSB_WAIT_SHIFT 0
+#define CSB_RO 0x00000008 /* Read-Only */
+#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
+#define CSB_AM_SHIFT 8
+#define CSB_BUSW 0x00010000 /* Bus Width Select */
+#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
+#define CSB_AC_SHIFT 24
+
+/*
+ * Chip-Select Option Registers (group C)
+ */
+#define CSC0_ADDR 0xfffff130
+#define CSC1_ADDR 0xfffff134
+#define CSC2_ADDR 0xfffff138
+#define CSC3_ADDR 0xfffff13c
+
+#define CSC0 LONG_REF(CSC0_ADDR)
+#define CSC1 LONG_REF(CSC1_ADDR)
+#define CSC2 LONG_REF(CSC2_ADDR)
+#define CSC3 LONG_REF(CSC3_ADDR)
+
+#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSC_WAIT_SHIFT 0
+#define CSC_RO 0x00000008 /* Read-Only */
+#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
+#define CSC_AM_SHIFT 4
+#define CSC_BUSW 0x00010000 /* Bus Width Select */
+#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
+#define CSC_AC_SHIFT 20
+
+/*
+ * Chip-Select Option Registers (group D)
+ */
+#define CSD0_ADDR 0xfffff140
+#define CSD1_ADDR 0xfffff144
+#define CSD2_ADDR 0xfffff148
+#define CSD3_ADDR 0xfffff14c
+
+#define CSD0 LONG_REF(CSD0_ADDR)
+#define CSD1 LONG_REF(CSD1_ADDR)
+#define CSD2 LONG_REF(CSD2_ADDR)
+#define CSD3 LONG_REF(CSD3_ADDR)
+
+#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSD_WAIT_SHIFT 0
+#define CSD_RO 0x00000008 /* Read-Only */
+#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
+#define CSD_AM_SHIFT 4
+#define CSD_BUSW 0x00010000 /* Bus Width Select */
+#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
+#define CSD_AC_SHIFT 20
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_PIXCLK_SEL_SHIFT 11
+
+/* 'EZ328-compatible definitions */
+#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
+#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADRR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
+#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
+#define UART_IRQ_NUM 2 /* UART interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define INT4_IRQ_NUM 12 /* External INT4 */
+#define INT5_IRQ_NUM 13 /* External INT5 */
+#define INT6_IRQ_NUM 14 /* External INT6 */
+#define INT7_IRQ_NUM 15 /* External INT7 */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define PEN_IRQ_NUM 20 /* Pen Interrupt */
+#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
+#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
+#define IRQ7_IRQ_NUM 23 /* IRQ7 */
+
+/* '328-compatible definitions */
+#define SPI_IRQ_NUM SPIM_IRQ_NUM
+#define TMR_IRQ_NUM TMR1_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */
+#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
+#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
+#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
+#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
+#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
+#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
+#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define IMR_MSPI IMR_MSPIM
+#define IMR_MTMR IMR_MTMR1
+
+/*
+ * Interrupt Wake-Up Enable Register
+ */
+#define IWR_ADDR 0xfffff308
+#define IWR LONG_REF(IWR_ADDR)
+
+#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
+#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
+#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define ISR_SPI ISR_SPIM
+#define ISR_TMR ISR_TMR1
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff310
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
+#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define IPR_SPI IPR_SPIM
+#define IPR_TMR IPR_TMR1
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PASEL_ADDR 0xfffff403 /* Port A Select register */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PASEL BYTE_REF(PASEL_ADDR)
+
+#define PA(x) (1 << (x))
+#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
+
+#define PA_A16 PA(0) /* Use A16 as PA(0) */
+#define PA_A17 PA(1) /* Use A17 as PA(1) */
+#define PA_A18 PA(2) /* Use A18 as PA(2) */
+#define PA_A19 PA(3) /* Use A19 as PA(3) */
+#define PA_A20 PA(4) /* Use A20 as PA(4) */
+#define PA_A21 PA(5) /* Use A21 as PA(5) */
+#define PA_A22 PA(6) /* Use A22 as PA(6) */
+#define PA_A23 PA(7) /* Use A23 as PA(7) */
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+#define PB_D(x) PB(x) /* This is specific to port B only */
+
+#define PB_D0 PB(0) /* Use D0 as PB(0) */
+#define PB_D1 PB(1) /* Use D1 as PB(1) */
+#define PB_D2 PB(2) /* Use D2 as PB(2) */
+#define PB_D3 PB(3) /* Use D3 as PB(3) */
+#define PB_D4 PB(4) /* Use D4 as PB(4) */
+#define PB_D5 PB(5) /* Use D5 as PB(5) */
+#define PB_D6 PB(6) /* Use D6 as PB(6) */
+#define PB_D7 PB(7) /* Use D7 as PB(7) */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_WE PC(6) /* Use WE as PC(6) */
+#define PC_DTACK PC(5) /* Use DTACK as PC(5) */
+#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
+#define PC_LDS PC(2) /* Use LDS as PC(2) */
+#define PC_UDS PC(1) /* Use UDS as PC(1) */
+#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+#define PD_KB(x) PD(x) /* This is specific for Port D only */
+
+#define PD_KB0 PD(0) /* Use KB0 as PD(0) */
+#define PD_KB1 PD(1) /* Use KB1 as PD(1) */
+#define PD_KB2 PD(2) /* Use KB2 as PD(2) */
+#define PD_KB3 PD(3) /* Use KB3 as PD(3) */
+#define PD_KB4 PD(4) /* Use KB4 as PD(4) */
+#define PD_KB5 PD(5) /* Use KB5 as PD(5) */
+#define PD_KB6 PD(6) /* Use KB6 as PD(6) */
+#define PD_KB7 PD(7) /* Use KB7 as PD(7) */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
+#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
+#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
+#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
+#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
+#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
+#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+#define PF_A(x) PF((x) - 24) /* This is Port F specific only */
+
+#define PF_A24 PF(0) /* Use A24 as PF(0) */
+#define PF_A25 PF(1) /* Use A25 as PF(1) */
+#define PF_A26 PF(2) /* Use A26 as PF(2) */
+#define PF_A27 PF(3) /* Use A27 as PF(3) */
+#define PF_A28 PF(4) /* Use A28 as PF(4) */
+#define PF_A29 PF(5) /* Use A29 as PF(5) */
+#define PF_A30 PF(6) /* Use A30 as PF(6) */
+#define PF_A31 PF(7) /* Use A31 as PF(7) */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
+#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
+#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
+#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
+#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
+#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
+#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
+#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
+
+/*
+ * Port J
+ */
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
+
+/*
+ * Port K
+ */
+#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
+#define PKDATA_ADDR 0xfffff441 /* Port K data register */
+#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
+#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
+
+#define PKDIR BYTE_REF(PKDIR_ADDR)
+#define PKDATA BYTE_REF(PKDATA_ADDR)
+#define PKPUEN BYTE_REF(PKPUEN_ADDR)
+#define PKSEL BYTE_REF(PKSEL_ADDR)
+
+#define PK(x) (1 << (x))
+
+/*
+ * Port M
+ */
+#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
+#define PMDATA_ADDR 0xfffff439 /* Port M data register */
+#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
+#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
+
+#define PMDIR BYTE_REF(PMDIR_ADDR)
+#define PMDATA BYTE_REF(PMDATA_ADDR)
+#define PMPUEN BYTE_REF(PMPUEN_ADDR)
+#define PMSEL BYTE_REF(PMSEL_ADDR)
+
+#define PM(x) (1 << (x))
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_PWMEN 0x0010 /* Enable PWM */
+#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
+#define PWMC_PIN 0x0080 /* Current PWM output pin status */
+#define PWMC_LOAD 0x0100 /* Force a new period */
+#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* 'EZ328-compatible definitions */
+#define PWMC_EN PWMC_PWMEN
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff502
+#define PWMP WORD_REF(PWMP_ADDR)
+
+/*
+ * PWM Width Register
+ */
+#define PWMW_ADDR 0xfffff504
+#define PWMW WORD_REF(PWMW_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff506
+#define PWMCNT WORD_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timers
+ *
+ **********/
+
+/*
+ * Timer Unit 1 and 2 Control Registers
+ */
+#define TCTL1_ADDR 0xfffff600
+#define TCTL1 WORD_REF(TCTL1_ADDR)
+#define TCTL2_ADDR 0xfffff60c
+#define TCTL2 WORD_REF(TCTL2_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* 'EZ328-compatible definitions */
+#define TCTL_ADDR TCTL1_ADDR
+#define TCTL TCTL1
+
+/*
+ * Timer Unit 1 and 2 Prescaler Registers
+ */
+#define TPRER1_ADDR 0xfffff602
+#define TPRER1 WORD_REF(TPRER1_ADDR)
+#define TPRER2_ADDR 0xfffff60e
+#define TPRER2 WORD_REF(TPRER2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TPRER_ADDR TPRER1_ADDR
+#define TPRER TPRER1
+
+/*
+ * Timer Unit 1 and 2 Compare Registers
+ */
+#define TCMP1_ADDR 0xfffff604
+#define TCMP1 WORD_REF(TCMP1_ADDR)
+#define TCMP2_ADDR 0xfffff610
+#define TCMP2 WORD_REF(TCMP2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCMP_ADDR TCMP1_ADDR
+#define TCMP TCMP1
+
+/*
+ * Timer Unit 1 and 2 Capture Registers
+ */
+#define TCR1_ADDR 0xfffff606
+#define TCR1 WORD_REF(TCR1_ADDR)
+#define TCR2_ADDR 0xfffff612
+#define TCR2 WORD_REF(TCR2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCR_ADDR TCR1_ADDR
+#define TCR TCR1
+
+/*
+ * Timer Unit 1 and 2 Counter Registers
+ */
+#define TCN1_ADDR 0xfffff608
+#define TCN1 WORD_REF(TCN1_ADDR)
+#define TCN2_ADDR 0xfffff614
+#define TCN2 WORD_REF(TCN2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCN_ADDR TCN1_ADDR
+#define TCN TCN
+
+/*
+ * Timer Unit 1 and 2 Status Registers
+ */
+#define TSTAT1_ADDR 0xfffff60a
+#define TSTAT1 WORD_REF(TSTAT1_ADDR)
+#define TSTAT2_ADDR 0xfffff616
+#define TSTAT2 WORD_REF(TSTAT2_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* 'EZ328-compatible definitions */
+#define TSTAT_ADDR TSTAT1_ADDR
+#define TSTAT TSTAT1
+
+/*
+ * Watchdog Compare Register
+ */
+#define WRR_ADDR 0xfffff61a
+#define WRR WORD_REF(WRR_ADDR)
+
+/*
+ * Watchdog Counter Register
+ */
+#define WCN_ADDR 0xfffff61c
+#define WCN WORD_REF(WCN_ADDR)
+
+/*
+ * Watchdog Control and Status Register
+ */
+#define WCSR_ADDR 0xfffff618
+#define WCSR WORD_REF(WCSR_ADDR)
+
+#define WCSR_WDEN 0x0001 /* Watchdog Enable */
+#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
+#define WCSR_WRST 0x0004 /* Watchdog Reset */
+
+/**********
+ *
+ * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
+ *
+ **********/
+
+/*
+ * SPI Slave Register
+ */
+#define SPISR_ADDR 0xfffff700
+#define SPISR WORD_REF(SPISR_ADDR)
+
+#define SPISR_DATA_ADDR 0xfffff701
+#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
+
+#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
+#define SPISR_DATA_SHIFT 0
+#define SPISR_SPISEN 0x0100 /* SPIS module enable */
+#define SPISR_POL 0x0200 /* SPSCLK polarity control */
+#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
+#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
+#define SPISR_DATARDY 0x1000 /* Data ready */
+#define SPISR_ENPOL 0x2000 /* Enable Polarity */
+#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
+#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* 'EZ328-compatible definitions */
+#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
+#define SPIMCONT_ENABLE SPIMCONT_SPIMEN
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
+#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
+#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
+#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
+#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
+#define USTCNT_PARITYEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UARTEN 0x8000 /* UART Enable */
+
+/* 'EZ328-compatible definitions */
+#define USTCNT_TXAE USTCNT_TXAVAILEN
+#define USTCNT_TXHE USTCNT_TXHALFEN
+#define USTCNT_TXEE USTCNT_TXEMPTYEN
+#define USTCNT_RXRE USTCNT_RXREADYEN
+#define USTCNT_RXHE USTCNT_RXHALFEN
+#define USTCNT_RXFE USTCNT_RXFULLEN
+#define USTCNT_CTSD USTCNT_CTSDELTAEN
+#define USTCNT_ODD USTCNT_ODD_EVEN
+#define USTCNT_PEN USTCNT_PARITYEN
+#define USTCNT_CLKM USTCNT_CLKMODE
+#define USTCNT_UEN USTCNT_UARTEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_GPIOSRC 0x1000 /* GPIO source */
+#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
+#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
+#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STATUS 0x0200 /* CTS State */
+#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* 'EZ328-compatible definitions */
+#define UTX_CTS_STAT UTX_CTS_STATUS
+#define UTX_NOCTS UTX_IGNORE_CTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef volatile struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int pad1;
+ volatile unsigned short int pad2;
+ volatile unsigned short int pad3;
+} __attribute__((packed)) m68328_uart;
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with 'EZ328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x02
+#define LPICF_PBSIZ_4 0x04
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
+#define LCKCON_DWIDTH 0x02 /* Display Memory Width */
+#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 2
+#define LCKCON_DMA16 0x40 /* DMA burst length */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* 'EZ328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Last Buffer Address Register
+ */
+#define LLBAR_ADDR 0xfffffa29
+#define LLBAR BYTE_REF(LLBAR_ADDR)
+
+#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
+#define LLBAR_LBAR_SHIFT 0
+
+/*
+ * LCD Octet Terminal Count Register
+ */
+#define LOTCR_ADDR 0xfffffa2b
+#define LOTCR BYTE_REF(LOTCR_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
+#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa32
+#define LGPMR WORD_REF(LGPMR_ADDR)
+
+#define LGPMR_GLEVEL3_MASK 0x000f
+#define LGPMR_GLEVEL3_SHIFT 0
+#define LGPMR_GLEVEL2_MASK 0x00f0
+#define LGPMR_GLEVEL2_SHIFT 4
+#define LGPMR_GLEVEL0_MASK 0x0f00
+#define LGPMR_GLEVEL0_SHIFT 8
+#define LGPMR_GLEVEL1_MASK 0xf000
+#define LGPMR_GLEVEL1_SHIFT 12
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_384 0x0020 /* Crystal Selection */
+#define RTCCTL_ENABLE 0x0080 /* RTC Enable */
+
+/* 'EZ328-compatible definitions */
+#define RTCCTL_XTL RTCCTL_384
+#define RTCCTL_EN RTCCTL_ENABLE
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH)
+
+#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+#endif /* _MC68328_H_ */
diff --git a/arch/m68k/include/asm/MC68332.h b/arch/m68k/include/asm/MC68332.h
new file mode 100644
index 00000000000..6bb8f02685a
--- /dev/null
+++ b/arch/m68k/include/asm/MC68332.h
@@ -0,0 +1,152 @@
+
+/* include/asm-m68knommu/MC68332.h: '332 control registers
+ *
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ *
+ */
+
+#ifndef _MC68332_H_
+#define _MC68332_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+
+#define PORTE_ADDR 0xfffa11
+#define PORTE BYTE_REF(PORTE_ADDR)
+#define DDRE_ADDR 0xfffa15
+#define DDRE BYTE_REF(DDRE_ADDR)
+#define PEPAR_ADDR 0xfffa17
+#define PEPAR BYTE_REF(PEPAR_ADDR)
+
+#define PORTF_ADDR 0xfffa19
+#define PORTF BYTE_REF(PORTF_ADDR)
+#define DDRF_ADDR 0xfffa1d
+#define DDRF BYTE_REF(DDRF_ADDR)
+#define PFPAR_ADDR 0xfffa1f
+#define PFPAR BYTE_REF(PFPAR_ADDR)
+
+#define PORTQS_ADDR 0xfffc15
+#define PORTQS BYTE_REF(PORTQS_ADDR)
+#define DDRQS_ADDR 0xfffc17
+#define DDRQS BYTE_REF(DDRQS_ADDR)
+#define PQSPAR_ADDR 0xfffc16
+#define PQSPAR BYTE_REF(PQSPAR_ADDR)
+
+#define CSPAR0_ADDR 0xFFFA44
+#define CSPAR0 WORD_REF(CSPAR0_ADDR)
+#define CSPAR1_ADDR 0xFFFA46
+#define CSPAR1 WORD_REF(CSPAR1_ADDR)
+#define CSARBT_ADDR 0xFFFA48
+#define CSARBT WORD_REF(CSARBT_ADDR)
+#define CSOPBT_ADDR 0xFFFA4A
+#define CSOPBT WORD_REF(CSOPBT_ADDR)
+#define CSBAR0_ADDR 0xFFFA4C
+#define CSBAR0 WORD_REF(CSBAR0_ADDR)
+#define CSOR0_ADDR 0xFFFA4E
+#define CSOR0 WORD_REF(CSOR0_ADDR)
+#define CSBAR1_ADDR 0xFFFA50
+#define CSBAR1 WORD_REF(CSBAR1_ADDR)
+#define CSOR1_ADDR 0xFFFA52
+#define CSOR1 WORD_REF(CSOR1_ADDR)
+#define CSBAR2_ADDR 0xFFFA54
+#define CSBAR2 WORD_REF(CSBAR2_ADDR)
+#define CSOR2_ADDR 0xFFFA56
+#define CSOR2 WORD_REF(CSOR2_ADDR)
+#define CSBAR3_ADDR 0xFFFA58
+#define CSBAR3 WORD_REF(CSBAR3_ADDR)
+#define CSOR3_ADDR 0xFFFA5A
+#define CSOR3 WORD_REF(CSOR3_ADDR)
+#define CSBAR4_ADDR 0xFFFA5C
+#define CSBAR4 WORD_REF(CSBAR4_ADDR)
+#define CSOR4_ADDR 0xFFFA5E
+#define CSOR4 WORD_REF(CSOR4_ADDR)
+#define CSBAR5_ADDR 0xFFFA60
+#define CSBAR5 WORD_REF(CSBAR5_ADDR)
+#define CSOR5_ADDR 0xFFFA62
+#define CSOR5 WORD_REF(CSOR5_ADDR)
+#define CSBAR6_ADDR 0xFFFA64
+#define CSBAR6 WORD_REF(CSBAR6_ADDR)
+#define CSOR6_ADDR 0xFFFA66
+#define CSOR6 WORD_REF(CSOR6_ADDR)
+#define CSBAR7_ADDR 0xFFFA68
+#define CSBAR7 WORD_REF(CSBAR7_ADDR)
+#define CSOR7_ADDR 0xFFFA6A
+#define CSOR7 WORD_REF(CSOR7_ADDR)
+#define CSBAR8_ADDR 0xFFFA6C
+#define CSBAR8 WORD_REF(CSBAR8_ADDR)
+#define CSOR8_ADDR 0xFFFA6E
+#define CSOR8 WORD_REF(CSOR8_ADDR)
+#define CSBAR9_ADDR 0xFFFA70
+#define CSBAR9 WORD_REF(CSBAR9_ADDR)
+#define CSOR9_ADDR 0xFFFA72
+#define CSOR9 WORD_REF(CSOR9_ADDR)
+#define CSBAR10_ADDR 0xFFFA74
+#define CSBAR10 WORD_REF(CSBAR10_ADDR)
+#define CSOR10_ADDR 0xFFFA76
+#define CSOR10 WORD_REF(CSOR10_ADDR)
+
+#define CSOR_MODE_ASYNC 0x0000
+#define CSOR_MODE_SYNC 0x8000
+#define CSOR_MODE_MASK 0x8000
+#define CSOR_BYTE_DISABLE 0x0000
+#define CSOR_BYTE_UPPER 0x4000
+#define CSOR_BYTE_LOWER 0x2000
+#define CSOR_BYTE_BOTH 0x6000
+#define CSOR_BYTE_MASK 0x6000
+#define CSOR_RW_RSVD 0x0000
+#define CSOR_RW_READ 0x0800
+#define CSOR_RW_WRITE 0x1000
+#define CSOR_RW_BOTH 0x1800
+#define CSOR_RW_MASK 0x1800
+#define CSOR_STROBE_DS 0x0400
+#define CSOR_STROBE_AS 0x0000
+#define CSOR_STROBE_MASK 0x0400
+#define CSOR_DSACK_WAIT(x) (wait << 6)
+#define CSOR_DSACK_FTERM (14 << 6)
+#define CSOR_DSACK_EXTERNAL (15 << 6)
+#define CSOR_DSACK_MASK 0x03c0
+#define CSOR_SPACE_CPU 0x0000
+#define CSOR_SPACE_USER 0x0010
+#define CSOR_SPACE_SU 0x0020
+#define CSOR_SPACE_BOTH 0x0030
+#define CSOR_SPACE_MASK 0x0030
+#define CSOR_IPL_ALL 0x0000
+#define CSOR_IPL_PRIORITY(x) (x << 1)
+#define CSOR_IPL_MASK 0x000e
+#define CSOR_AVEC_ON 0x0001
+#define CSOR_AVEC_OFF 0x0000
+#define CSOR_AVEC_MASK 0x0001
+
+#define CSBAR_ADDR(x) ((addr >> 11) << 3)
+#define CSBAR_ADDR_MASK 0xfff8
+#define CSBAR_BLKSIZE_2K 0x0000
+#define CSBAR_BLKSIZE_8K 0x0001
+#define CSBAR_BLKSIZE_16K 0x0002
+#define CSBAR_BLKSIZE_64K 0x0003
+#define CSBAR_BLKSIZE_128K 0x0004
+#define CSBAR_BLKSIZE_256K 0x0005
+#define CSBAR_BLKSIZE_512K 0x0006
+#define CSBAR_BLKSIZE_1M 0x0007
+#define CSBAR_BLKSIZE_MASK 0x0007
+
+#define CSPAR_DISC 0
+#define CSPAR_ALT 1
+#define CSPAR_CS8 2
+#define CSPAR_CS16 3
+#define CSPAR_MASK 3
+
+#define CSPAR0_CSBOOT(x) (x << 0)
+#define CSPAR0_CS0(x) (x << 2)
+#define CSPAR0_CS1(x) (x << 4)
+#define CSPAR0_CS2(x) (x << 6)
+#define CSPAR0_CS3(x) (x << 8)
+#define CSPAR0_CS4(x) (x << 10)
+#define CSPAR0_CS5(x) (x << 12)
+
+#define CSPAR1_CS6(x) (x << 0)
+#define CSPAR1_CS7(x) (x << 2)
+#define CSPAR1_CS8(x) (x << 4)
+#define CSPAR1_CS9(x) (x << 6)
+#define CSPAR1_CS10(x) (x << 8)
+
+#endif
diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h
new file mode 100644
index 00000000000..d1bde58ab0d
--- /dev/null
+++ b/arch/m68k/include/asm/MC68EZ328.h
@@ -0,0 +1,1253 @@
+
+/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
+ *
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bear & Hare Software, Inc.
+ *
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ */
+
+#ifndef _MC68EZ328_H_
+#define _MC68EZ328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/*
+ * Chip Select Group Base Registers
+ */
+#define CSGBA_ADDR 0xfffff100
+#define CSGBB_ADDR 0xfffff102
+
+#define CSGBC_ADDR 0xfffff104
+#define CSGBD_ADDR 0xfffff106
+
+#define CSGBA WORD_REF(CSGBA_ADDR)
+#define CSGBB WORD_REF(CSGBB_ADDR)
+#define CSGBC WORD_REF(CSGBC_ADDR)
+#define CSGBD WORD_REF(CSGBD_ADDR)
+
+/*
+ * Chip Select Registers
+ */
+#define CSA_ADDR 0xfffff110
+#define CSB_ADDR 0xfffff112
+#define CSC_ADDR 0xfffff114
+#define CSD_ADDR 0xfffff116
+
+#define CSA WORD_REF(CSA_ADDR)
+#define CSB WORD_REF(CSB_ADDR)
+#define CSC WORD_REF(CSC_ADDR)
+#define CSD WORD_REF(CSD_ADDR)
+
+#define CSA_EN 0x0001 /* Chip-Select Enable */
+#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSA_SIZ_SHIFT 1
+#define CSA_WS_MASK 0x0070 /* Wait State */
+#define CSA_WS_SHIFT 4
+#define CSA_BSW 0x0080 /* Data Bus Width */
+#define CSA_FLASH 0x0100 /* FLASH Memory Support */
+#define CSA_RO 0x8000 /* Read-Only */
+
+#define CSB_EN 0x0001 /* Chip-Select Enable */
+#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSB_SIZ_SHIFT 1
+#define CSB_WS_MASK 0x0070 /* Wait State */
+#define CSB_WS_SHIFT 4
+#define CSB_BSW 0x0080 /* Data Bus Width */
+#define CSB_FLASH 0x0100 /* FLASH Memory Support */
+#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSB_UPSIZ_SHIFT 11
+#define CSB_ROP 0x2000 /* Readonly if protected */
+#define CSB_SOP 0x4000 /* Supervisor only if protected */
+#define CSB_RO 0x8000 /* Read-Only */
+
+#define CSC_EN 0x0001 /* Chip-Select Enable */
+#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSC_SIZ_SHIFT 1
+#define CSC_WS_MASK 0x0070 /* Wait State */
+#define CSC_WS_SHIFT 4
+#define CSC_BSW 0x0080 /* Data Bus Width */
+#define CSC_FLASH 0x0100 /* FLASH Memory Support */
+#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSC_UPSIZ_SHIFT 11
+#define CSC_ROP 0x2000 /* Readonly if protected */
+#define CSC_SOP 0x4000 /* Supervisor only if protected */
+#define CSC_RO 0x8000 /* Read-Only */
+
+#define CSD_EN 0x0001 /* Chip-Select Enable */
+#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSD_SIZ_SHIFT 1
+#define CSD_WS_MASK 0x0070 /* Wait State */
+#define CSD_WS_SHIFT 4
+#define CSD_BSW 0x0080 /* Data Bus Width */
+#define CSD_FLASH 0x0100 /* FLASH Memory Support */
+#define CSD_DRAM 0x0200 /* Dram Selection */
+#define CSD_COMB 0x0400 /* Combining */
+#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSD_UPSIZ_SHIFT 11
+#define CSD_ROP 0x2000 /* Readonly if protected */
+#define CSD_SOP 0x4000 /* Supervisor only if protected */
+#define CSD_RO 0x8000 /* Read-Only */
+
+/*
+ * Emulation Chip-Select Register
+ */
+#define EMUCS_ADDR 0xfffff118
+#define EMUCS WORD_REF(EMUCS_ADDR)
+
+#define EMUCS_WS_MASK 0x0070
+#define EMUCS_WS_SHIFT 4
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_PRESC 0x0020 /* VCO prescaler */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_LCDCLK_SEL_SHIFT 11
+
+/* '328-compatible definitions */
+#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
+#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADDR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPI_IRQ_NUM 0 /* SPI interrupt */
+#define TMR_IRQ_NUM 1 /* Timer interrupt */
+#define UART_IRQ_NUM 2 /* UART interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define IRQ5_IRQ_NUM 20 /* IRQ5 */
+#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
+#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define SPIM_IRQ_NUM SPI_IRQ_NUM
+#define TMR1_IRQ_NUM TMR_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
+#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
+#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
+#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IMR_MSPIM IMR_MSPI
+#define IMR_MTMR1 IMR_MTMR
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define ISR_SPIM ISR_SPI
+#define ISR_TMR1 ISR_TMR
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff30c
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IPR_SPIM IPR_SPI
+#define IPR_TMR1 IPR_TMR
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PAPUEN BYTE_REF(PAPUEN_ADDR)
+
+#define PA(x) (1 << (x))
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBPUEN BYTE_REF(PBPUEN_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+
+#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
+#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
+#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
+#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
+#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
+#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
+#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
+#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCPDEN BYTE_REF(PCPDEN_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_LD0 0x01 /* Use LD0 as PC[0] */
+#define PC_LD1 0x02 /* Use LD1 as PC[1] */
+#define PC_LD2 0x04 /* Use LD2 as PC[2] */
+#define PC_LD3 0x08 /* Use LD3 as PC[3] */
+#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
+#define PC_LLP 0x20 /* Use LLP as PC[5] */
+#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
+#define PC_LACD 0x80 /* Use LACD as PC[7] */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDSEL BYTE_REF(PDSEL_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDKBEN BYTE_REF(PDKBEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+
+#define PD_INT0 0x01 /* Use INT0 as PD[0] */
+#define PD_INT1 0x02 /* Use INT1 as PD[1] */
+#define PD_INT2 0x04 /* Use INT2 as PD[2] */
+#define PD_INT3 0x08 /* Use INT3 as PD[3] */
+#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
+#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
+#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
+#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
+#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
+#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
+#define PE_DWE 0x08 /* Use DWE as PE[3] */
+#define PE_RXD 0x10 /* Use RXD as PE[4] */
+#define PE_TXD 0x20 /* Use TXD as PE[5] */
+#define PE_RTS 0x40 /* Use RTS as PE[6] */
+#define PE_CTS 0x80 /* Use CTS as PE[7] */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+
+#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
+#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
+#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
+#define PF_A20 0x08 /* Use A20 as PF[3] */
+#define PF_A21 0x10 /* Use A21 as PF[4] */
+#define PF_A22 0x20 /* Use A22 as PF[5] */
+#define PF_A23 0x40 /* Use A23 as PF[6] */
+#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
+#define PG_A0 0x02 /* Use A0 as PG[1] */
+#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
+#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
+#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
+#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
+#define PWMC_REPEAT_SHIFT 2
+#define PWMC_EN 0x0010 /* Enable PWM */
+#define PMNC_FIFOAV 0x0020 /* FIFO Available */
+#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
+#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
+#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
+#define PWMC_PRESCALER_SHIFT 8
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* '328-compatible definitions */
+#define PWMC_PWMEN PWMC_EN
+
+/*
+ * PWM Sample Register
+ */
+#define PWMS_ADDR 0xfffff502
+#define PWMS WORD_REF(PWMS_ADDR)
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff504
+#define PWMP BYTE_REF(PWMP_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff505
+#define PWMCNT BYTE_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timer
+ *
+ **********/
+
+/*
+ * Timer Control register
+ */
+#define TCTL_ADDR 0xfffff600
+#define TCTL WORD_REF(TCTL_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* '328-compatible definitions */
+#define TCTL1_ADDR TCTL_ADDR
+#define TCTL1 TCTL
+
+/*
+ * Timer Prescaler Register
+ */
+#define TPRER_ADDR 0xfffff602
+#define TPRER WORD_REF(TPRER_ADDR)
+
+/* '328-compatible definitions */
+#define TPRER1_ADDR TPRER_ADDR
+#define TPRER1 TPRER
+
+/*
+ * Timer Compare Register
+ */
+#define TCMP_ADDR 0xfffff604
+#define TCMP WORD_REF(TCMP_ADDR)
+
+/* '328-compatible definitions */
+#define TCMP1_ADDR TCMP_ADDR
+#define TCMP1 TCMP
+
+/*
+ * Timer Capture register
+ */
+#define TCR_ADDR 0xfffff606
+#define TCR WORD_REF(TCR_ADDR)
+
+/* '328-compatible definitions */
+#define TCR1_ADDR TCR_ADDR
+#define TCR1 TCR
+
+/*
+ * Timer Counter Register
+ */
+#define TCN_ADDR 0xfffff608
+#define TCN WORD_REF(TCN_ADDR)
+
+/* '328-compatible definitions */
+#define TCN1_ADDR TCN_ADDR
+#define TCN1 TCN
+
+/*
+ * Timer Status Register
+ */
+#define TSTAT_ADDR 0xfffff60a
+#define TSTAT WORD_REF(TSTAT_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* '328-compatible definitions */
+#define TSTAT1_ADDR TSTAT_ADDR
+#define TSTAT1 TSTAT
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* '328-compatible definitions */
+#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
+#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
+
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
+#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
+#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
+#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
+#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD 0x0400 /* Odd Parity */
+#define USTCNT_PEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UEN 0x8000 /* UART Enable */
+
+/* '328-compatible definitions */
+#define USTCNT_TXAVAILEN USTCNT_TXAE
+#define USTCNT_TXHALFEN USTCNT_TXHE
+#define USTCNT_TXEMPTYEN USTCNT_TXEE
+#define USTCNT_RXREADYEN USTCNT_RXRE
+#define USTCNT_RXHALFEN USTCNT_RXHE
+#define USTCNT_RXFULLEN USTCNT_RXFE
+#define USTCNT_CTSDELTAEN USTCNT_CTSD
+#define USTCNT_ODD_EVEN USTCNT_ODD
+#define USTCNT_PARITYEN USTCNT_PEN
+#define USTCNT_CLKMODE USTCNT_CLKM
+#define USTCNT_UARTEN USTCNT_UEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STAT 0x0200 /* CTS State */
+#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
+#define UTX_NOCTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* '328-compatible definitions */
+#define UTX_CTS_STATUS UTX_CTS_STAT
+#define UTX_IGNORE_CTS UTX_NOCTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
+#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
+
+/*
+ * UART Non-integer Prescaler Register
+ */
+#define NIPR_ADDR 0xfffff90a
+#define NIPR WORD_REF(NIPR_ADDR)
+
+#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
+#define NIPR_STEP_VALUE_SHIFT 0
+#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
+#define NIPR_SELECT_SHIFT 8
+#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef volatile struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int nipr;
+ volatile unsigned short int pad1;
+ volatile unsigned short int pad2;
+} __attribute__((packed)) m68328_uart;
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with '328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_GS_GRAY_16 0x02
+#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x04
+#define LPICF_PBSIZ_4 0x08
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 0
+#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* '328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Refresh Rate Adjustment Register
+ */
+#define LRRA_ADDR 0xfffffa29
+#define LRRA BYTE_REF(LRRA_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa33
+#define LGPMR BYTE_REF(LGPMR_ADDR)
+
+#define LGPMR_G1_MASK 0x0f
+#define LGPMR_G1_SHIFT 0
+#define LGPMR_G2_MASK 0xf0
+#define LGPMR_G2_SHIFT 4
+
+/*
+ * PWM Contrast Control Register
+ */
+#define PWMR_ADDR 0xfffffa36
+#define PWMR WORD_REF(PWMR_ADDR)
+
+#define PWMR_PW_MASK 0x00ff /* Pulse Width */
+#define PWMR_PW_SHIFT 0
+#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
+#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
+#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
+#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
+#define PWMR_SRC_LCD 0x4000 /* LCD clock */
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * Watchdog Timer Register
+ */
+#define WATCHDOG_ADDR 0xfffffb0a
+#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
+
+#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
+#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
+#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
+#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
+#define WATCHDOG_CNT_SHIFT 8
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_XTL 0x0020 /* Crystal Selection */
+#define RTCCTL_EN 0x0080 /* RTC Enable */
+
+/* '328-compatible definitions */
+#define RTCCTL_384 RTCCTL_XTL
+#define RTCCTL_ENABLE RTCCTL_EN
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
+#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
+#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
+#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
+#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
+#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
+#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
+#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
+#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
+#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
+#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
+#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
+#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
+#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
+#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
+#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
+#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH)
+
+#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+/*
+ * RTC Day Count Register
+ */
+#define DAYR_ADDR 0xfffffb1a
+#define DAYR WORD_REF(DAYR_ADDR)
+
+#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
+#define DAYR_DAYS_SHIFT 0
+
+/*
+ * RTC Day Alarm Register
+ */
+#define DAYALARM_ADDR 0xfffffb1c
+#define DAYALARM WORD_REF(DAYALARM_ADDR)
+
+#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
+#define DAYALARM_DAYSAL_SHIFT 0
+
+/**********
+ *
+ * 0xFFFFFCxx -- DRAM Controller
+ *
+ **********/
+
+/*
+ * DRAM Memory Configuration Register
+ */
+#define DRAMMC_ADDR 0xfffffc00
+#define DRAMMC WORD_REF(DRAMMC_ADDR)
+
+#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
+#define DRAMMC_ROW12_PA10 0x0000
+#define DRAMMC_ROW12_PA21 0x4000
+#define DRAMMC_ROW12_PA23 0x8000
+#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
+#define DRAMMC_ROW0_PA11 0x0000
+#define DRAMMC_ROW0_PA22 0x1000
+#define DRAMMC_ROW0_PA23 0x2000
+#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
+#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
+#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
+#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
+#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
+#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
+#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
+#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
+#define DRAMMC_REF_SHIFT 0
+
+/*
+ * DRAM Control Register
+ */
+#define DRAMC_ADDR 0xfffffc02
+#define DRAMC WORD_REF(DRAMC_ADDR)
+
+#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
+#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
+#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
+#define DRAMC_SLW 0x0008 /* Slow RAM */
+#define DRAMC_LSP 0x0010 /* Light Sleep */
+#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
+#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
+#define DRAMC_WS_SHIFT 6
+#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
+#define DRAMC_PGSZ_SHIFT 8
+#define DRAMC_PGSZ_256K 0x0000
+#define DRAMC_PGSZ_512K 0x0100
+#define DRAMC_PGSZ_1024K 0x0200
+#define DRAMC_PGSZ_2048K 0x0300
+#define DRAMC_EDO 0x0400 /* EDO DRAM */
+#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
+#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
+#define DRAMC_BC_SHIFT 12
+#define DRAMC_RM 0x4000 /* Refresh Mode */
+#define DRAMC_EN 0x8000 /* DRAM Controller enable */
+
+
+/**********
+ *
+ * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
+ *
+ **********/
+
+/*
+ * ICE Module Address Compare Register
+ */
+#define ICEMACR_ADDR 0xfffffd00
+#define ICEMACR LONG_REF(ICEMACR_ADDR)
+
+/*
+ * ICE Module Address Mask Register
+ */
+#define ICEMAMR_ADDR 0xfffffd04
+#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
+
+/*
+ * ICE Module Control Compare Register
+ */
+#define ICEMCCR_ADDR 0xfffffd08
+#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
+
+#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
+#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
+
+/*
+ * ICE Module Control Mask Register
+ */
+#define ICEMCMR_ADDR 0xfffffd0a
+#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
+
+#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
+#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
+
+/*
+ * ICE Module Control Register
+ */
+#define ICEMCR_ADDR 0xfffffd0c
+#define ICEMCR WORD_REF(ICEMCR_ADDR)
+
+#define ICEMCR_CEN 0x0001 /* Compare Enable */
+#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
+#define ICEMCR_SB 0x0004 /* Single Breakpoint */
+#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
+#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
+
+/*
+ * ICE Module Status Register
+ */
+#define ICEMSR_ADDR 0xfffffd0e
+#define ICEMSR WORD_REF(ICEMSR_ADDR)
+
+#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
+#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
+#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
+#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
+
+#endif /* _MC68EZ328_H_ */
diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h
new file mode 100644
index 00000000000..6bd1bf1f85e
--- /dev/null
+++ b/arch/m68k/include/asm/MC68VZ328.h
@@ -0,0 +1,1349 @@
+
+/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
+ *
+ * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
+ * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bare & Hare Software, Inc.
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
+ * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
+ */
+
+#ifndef _MC68VZ328_H_
+#define _MC68VZ328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/*
+ * Chip Select Group Base Registers
+ */
+#define CSGBA_ADDR 0xfffff100
+#define CSGBB_ADDR 0xfffff102
+
+#define CSGBC_ADDR 0xfffff104
+#define CSGBD_ADDR 0xfffff106
+
+#define CSGBA WORD_REF(CSGBA_ADDR)
+#define CSGBB WORD_REF(CSGBB_ADDR)
+#define CSGBC WORD_REF(CSGBC_ADDR)
+#define CSGBD WORD_REF(CSGBD_ADDR)
+
+/*
+ * Chip Select Registers
+ */
+#define CSA_ADDR 0xfffff110
+#define CSB_ADDR 0xfffff112
+#define CSC_ADDR 0xfffff114
+#define CSD_ADDR 0xfffff116
+
+#define CSA WORD_REF(CSA_ADDR)
+#define CSB WORD_REF(CSB_ADDR)
+#define CSC WORD_REF(CSC_ADDR)
+#define CSD WORD_REF(CSD_ADDR)
+
+#define CSA_EN 0x0001 /* Chip-Select Enable */
+#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSA_SIZ_SHIFT 1
+#define CSA_WS_MASK 0x0070 /* Wait State */
+#define CSA_WS_SHIFT 4
+#define CSA_BSW 0x0080 /* Data Bus Width */
+#define CSA_FLASH 0x0100 /* FLASH Memory Support */
+#define CSA_RO 0x8000 /* Read-Only */
+
+#define CSB_EN 0x0001 /* Chip-Select Enable */
+#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSB_SIZ_SHIFT 1
+#define CSB_WS_MASK 0x0070 /* Wait State */
+#define CSB_WS_SHIFT 4
+#define CSB_BSW 0x0080 /* Data Bus Width */
+#define CSB_FLASH 0x0100 /* FLASH Memory Support */
+#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSB_UPSIZ_SHIFT 11
+#define CSB_ROP 0x2000 /* Readonly if protected */
+#define CSB_SOP 0x4000 /* Supervisor only if protected */
+#define CSB_RO 0x8000 /* Read-Only */
+
+#define CSC_EN 0x0001 /* Chip-Select Enable */
+#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSC_SIZ_SHIFT 1
+#define CSC_WS_MASK 0x0070 /* Wait State */
+#define CSC_WS_SHIFT 4
+#define CSC_BSW 0x0080 /* Data Bus Width */
+#define CSC_FLASH 0x0100 /* FLASH Memory Support */
+#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSC_UPSIZ_SHIFT 11
+#define CSC_ROP 0x2000 /* Readonly if protected */
+#define CSC_SOP 0x4000 /* Supervisor only if protected */
+#define CSC_RO 0x8000 /* Read-Only */
+
+#define CSD_EN 0x0001 /* Chip-Select Enable */
+#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSD_SIZ_SHIFT 1
+#define CSD_WS_MASK 0x0070 /* Wait State */
+#define CSD_WS_SHIFT 4
+#define CSD_BSW 0x0080 /* Data Bus Width */
+#define CSD_FLASH 0x0100 /* FLASH Memory Support */
+#define CSD_DRAM 0x0200 /* Dram Selection */
+#define CSD_COMB 0x0400 /* Combining */
+#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSD_UPSIZ_SHIFT 11
+#define CSD_ROP 0x2000 /* Readonly if protected */
+#define CSD_SOP 0x4000 /* Supervisor only if protected */
+#define CSD_RO 0x8000 /* Read-Only */
+
+/*
+ * Emulation Chip-Select Register
+ */
+#define EMUCS_ADDR 0xfffff118
+#define EMUCS WORD_REF(EMUCS_ADDR)
+
+#define EMUCS_WS_MASK 0x0070
+#define EMUCS_WS_SHIFT 4
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_PRESC 0x0020 /* VCO prescaler */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_LCDCLK_SEL_SHIFT 11
+
+/* '328-compatible definitions */
+#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
+#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADDR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
+#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
+#define UART1_IRQ_NUM 2 /* UART 1 interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define UART2_IRQ_NUM 12 /* UART 2 interrupt */
+#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define IRQ5_IRQ_NUM 20 /* IRQ5 */
+#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
+#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
+#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
+
+#define SPI_IRQ_NUM SPI2_IRQ_NUM
+
+/* '328-compatible definitions */
+#define SPIM_IRQ_NUM SPI_IRQ_NUM
+#define TMR1_IRQ_NUM TMR_IRQ_NUM
+#define UART_IRQ_NUM UART1_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
+#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
+#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
+#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IMR_MSPIM IMR_MSPI
+#define IMR_MTMR1 IMR_MTMR
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define ISR_SPIM ISR_SPI
+#define ISR_TMR1 ISR_TMR
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff30c
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IPR_SPIM IPR_SPI
+#define IPR_TMR1 IPR_TMR
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PAPUEN BYTE_REF(PAPUEN_ADDR)
+
+#define PA(x) (1 << (x))
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBPUEN BYTE_REF(PBPUEN_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+
+#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
+#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
+#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
+#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
+#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
+#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
+#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
+#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCPDEN BYTE_REF(PCPDEN_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_LD0 0x01 /* Use LD0 as PC[0] */
+#define PC_LD1 0x02 /* Use LD1 as PC[1] */
+#define PC_LD2 0x04 /* Use LD2 as PC[2] */
+#define PC_LD3 0x08 /* Use LD3 as PC[3] */
+#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
+#define PC_LLP 0x20 /* Use LLP as PC[5] */
+#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
+#define PC_LACD 0x80 /* Use LACD as PC[7] */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDSEL BYTE_REF(PDSEL_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDKBEN BYTE_REF(PDKBEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+
+#define PD_INT0 0x01 /* Use INT0 as PD[0] */
+#define PD_INT1 0x02 /* Use INT1 as PD[1] */
+#define PD_INT2 0x04 /* Use INT2 as PD[2] */
+#define PD_INT3 0x08 /* Use INT3 as PD[3] */
+#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
+#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
+#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
+#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
+#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
+#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
+#define PE_DWE 0x08 /* Use DWE as PE[3] */
+#define PE_RXD 0x10 /* Use RXD as PE[4] */
+#define PE_TXD 0x20 /* Use TXD as PE[5] */
+#define PE_RTS 0x40 /* Use RTS as PE[6] */
+#define PE_CTS 0x80 /* Use CTS as PE[7] */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+
+#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
+#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
+#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
+#define PF_A20 0x08 /* Use A20 as PF[3] */
+#define PF_A21 0x10 /* Use A21 as PF[4] */
+#define PF_A22 0x20 /* Use A22 as PF[5] */
+#define PF_A23 0x40 /* Use A23 as PF[6] */
+#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
+#define PG_A0 0x02 /* Use A0 as PG[1] */
+#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
+#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
+#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
+#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
+
+/*
+ * Port J
+ */
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
+#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJPUEN BYTE_REF(PJPUEN_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+/*
+ * Port K
+ */
+#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
+#define PKDATA_ADDR 0xfffff441 /* Port K data register */
+#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
+#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
+
+#define PKDIR BYTE_REF(PKDIR_ADDR)
+#define PKDATA BYTE_REF(PKDATA_ADDR)
+#define PKPUEN BYTE_REF(PKPUEN_ADDR)
+#define PKSEL BYTE_REF(PKSEL_ADDR)
+
+#define PK(x) (1 << (x))
+
+#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
+#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
+#define PK_R_W 0x02 /* Use R/W as PK[1] */
+#define PK_LDS 0x04 /* Use /LDS as PK[2] */
+#define PK_UDS 0x08 /* Use /UDS as PK[3] */
+#define PK_LD4 0x10 /* Use LD4 as PK[4] */
+#define PK_LD5 0x20 /* Use LD5 as PK[5] */
+#define PK_LD6 0x40 /* Use LD6 as PK[6] */
+#define PK_LD7 0x80 /* Use LD7 as PK[7] */
+
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
+#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJPUEN BYTE_REF(PJPUEN_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
+#define PJ_MISO 0x02 /* Use MISO as PJ[1] */
+#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
+#define PJ_SS 0x08 /* Use SS as PJ[3] */
+#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
+#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
+#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
+#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
+
+/*
+ * Port M
+ */
+#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
+#define PMDATA_ADDR 0xfffff449 /* Port M data register */
+#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
+#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
+
+#define PMDIR BYTE_REF(PMDIR_ADDR)
+#define PMDATA BYTE_REF(PMDATA_ADDR)
+#define PMPUEN BYTE_REF(PMPUEN_ADDR)
+#define PMSEL BYTE_REF(PMSEL_ADDR)
+
+#define PM(x) (1 << (x))
+
+#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
+#define PM_SDCE 0x02 /* Use SDCE as PM[1] */
+#define PM_DQMH 0x04 /* Use DQMH as PM[2] */
+#define PM_DQML 0x08 /* Use DQML as PM[3] */
+#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
+#define PM_DMOE 0x20 /* Use DMOE as PM[5] */
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
+#define PWMC_REPEAT_SHIFT 2
+#define PWMC_EN 0x0010 /* Enable PWM */
+#define PMNC_FIFOAV 0x0020 /* FIFO Available */
+#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
+#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
+#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
+#define PWMC_PRESCALER_SHIFT 8
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* '328-compatible definitions */
+#define PWMC_PWMEN PWMC_EN
+
+/*
+ * PWM Sample Register
+ */
+#define PWMS_ADDR 0xfffff502
+#define PWMS WORD_REF(PWMS_ADDR)
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff504
+#define PWMP BYTE_REF(PWMP_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff505
+#define PWMCNT BYTE_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timer
+ *
+ **********/
+
+/*
+ * Timer Control register
+ */
+#define TCTL_ADDR 0xfffff600
+#define TCTL WORD_REF(TCTL_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* '328-compatible definitions */
+#define TCTL1_ADDR TCTL_ADDR
+#define TCTL1 TCTL
+
+/*
+ * Timer Prescaler Register
+ */
+#define TPRER_ADDR 0xfffff602
+#define TPRER WORD_REF(TPRER_ADDR)
+
+/* '328-compatible definitions */
+#define TPRER1_ADDR TPRER_ADDR
+#define TPRER1 TPRER
+
+/*
+ * Timer Compare Register
+ */
+#define TCMP_ADDR 0xfffff604
+#define TCMP WORD_REF(TCMP_ADDR)
+
+/* '328-compatible definitions */
+#define TCMP1_ADDR TCMP_ADDR
+#define TCMP1 TCMP
+
+/*
+ * Timer Capture register
+ */
+#define TCR_ADDR 0xfffff606
+#define TCR WORD_REF(TCR_ADDR)
+
+/* '328-compatible definitions */
+#define TCR1_ADDR TCR_ADDR
+#define TCR1 TCR
+
+/*
+ * Timer Counter Register
+ */
+#define TCN_ADDR 0xfffff608
+#define TCN WORD_REF(TCN_ADDR)
+
+/* '328-compatible definitions */
+#define TCN1_ADDR TCN_ADDR
+#define TCN1 TCN
+
+/*
+ * Timer Status Register
+ */
+#define TSTAT_ADDR 0xfffff60a
+#define TSTAT WORD_REF(TSTAT_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* '328-compatible definitions */
+#define TSTAT1_ADDR TSTAT_ADDR
+#define TSTAT1 TSTAT
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* '328-compatible definitions */
+#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
+#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
+
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
+#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
+#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
+#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
+#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD 0x0400 /* Odd Parity */
+#define USTCNT_PEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UEN 0x8000 /* UART Enable */
+
+/* '328-compatible definitions */
+#define USTCNT_TXAVAILEN USTCNT_TXAE
+#define USTCNT_TXHALFEN USTCNT_TXHE
+#define USTCNT_TXEMPTYEN USTCNT_TXEE
+#define USTCNT_RXREADYEN USTCNT_RXRE
+#define USTCNT_RXHALFEN USTCNT_RXHE
+#define USTCNT_RXFULLEN USTCNT_RXFE
+#define USTCNT_CTSDELTAEN USTCNT_CTSD
+#define USTCNT_ODD_EVEN USTCNT_ODD
+#define USTCNT_PARITYEN USTCNT_PEN
+#define USTCNT_CLKMODE USTCNT_CLKM
+#define USTCNT_UARTEN USTCNT_UEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STAT 0x0200 /* CTS State */
+#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
+#define UTX_NOCTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* '328-compatible definitions */
+#define UTX_CTS_STATUS UTX_CTS_STAT
+#define UTX_IGNORE_CTS UTX_NOCTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
+#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
+
+/*
+ * UART Non-integer Prescaler Register
+ */
+#define NIPR_ADDR 0xfffff90a
+#define NIPR WORD_REF(NIPR_ADDR)
+
+#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
+#define NIPR_STEP_VALUE_SHIFT 0
+#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
+#define NIPR_SELECT_SHIFT 8
+#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int nipr;
+ volatile unsigned short int hmark;
+ volatile unsigned short int unused;
+} __attribute__((packed)) m68328_uart;
+
+
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with '328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_GS_GRAY_16 0x02
+#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x04
+#define LPICF_PBSIZ_4 0x08
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 0
+#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* '328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Refresh Rate Adjustment Register
+ */
+#define LRRA_ADDR 0xfffffa29
+#define LRRA BYTE_REF(LRRA_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa33
+#define LGPMR BYTE_REF(LGPMR_ADDR)
+
+#define LGPMR_G1_MASK 0x0f
+#define LGPMR_G1_SHIFT 0
+#define LGPMR_G2_MASK 0xf0
+#define LGPMR_G2_SHIFT 4
+
+/*
+ * PWM Contrast Control Register
+ */
+#define PWMR_ADDR 0xfffffa36
+#define PWMR WORD_REF(PWMR_ADDR)
+
+#define PWMR_PW_MASK 0x00ff /* Pulse Width */
+#define PWMR_PW_SHIFT 0
+#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
+#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
+#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
+#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
+#define PWMR_SRC_LCD 0x4000 /* LCD clock */
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * Watchdog Timer Register
+ */
+#define WATCHDOG_ADDR 0xfffffb0a
+#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
+
+#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
+#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
+#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
+#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
+#define WATCHDOG_CNT_SHIFT 8
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_XTL 0x0020 /* Crystal Selection */
+#define RTCCTL_EN 0x0080 /* RTC Enable */
+
+/* '328-compatible definitions */
+#define RTCCTL_384 RTCCTL_XTL
+#define RTCCTL_ENABLE RTCCTL_EN
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
+#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
+#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
+#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
+#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
+#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
+#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
+#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
+#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
+#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
+#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
+#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
+#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
+#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
+#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
+#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
+#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH_ADDR)
+
+#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+/*
+ * RTC Day Count Register
+ */
+#define DAYR_ADDR 0xfffffb1a
+#define DAYR WORD_REF(DAYR_ADDR)
+
+#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
+#define DAYR_DAYS_SHIFT 0
+
+/*
+ * RTC Day Alarm Register
+ */
+#define DAYALARM_ADDR 0xfffffb1c
+#define DAYALARM WORD_REF(DAYALARM_ADDR)
+
+#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
+#define DAYALARM_DAYSAL_SHIFT 0
+
+/**********
+ *
+ * 0xFFFFFCxx -- DRAM Controller
+ *
+ **********/
+
+/*
+ * DRAM Memory Configuration Register
+ */
+#define DRAMMC_ADDR 0xfffffc00
+#define DRAMMC WORD_REF(DRAMMC_ADDR)
+
+#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
+#define DRAMMC_ROW12_PA10 0x0000
+#define DRAMMC_ROW12_PA21 0x4000
+#define DRAMMC_ROW12_PA23 0x8000
+#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
+#define DRAMMC_ROW0_PA11 0x0000
+#define DRAMMC_ROW0_PA22 0x1000
+#define DRAMMC_ROW0_PA23 0x2000
+#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
+#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
+#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
+#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
+#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
+#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
+#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
+#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
+#define DRAMMC_REF_SHIFT 0
+
+/*
+ * DRAM Control Register
+ */
+#define DRAMC_ADDR 0xfffffc02
+#define DRAMC WORD_REF(DRAMC_ADDR)
+
+#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
+#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
+#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
+#define DRAMC_SLW 0x0008 /* Slow RAM */
+#define DRAMC_LSP 0x0010 /* Light Sleep */
+#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
+#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
+#define DRAMC_WS_SHIFT 6
+#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
+#define DRAMC_PGSZ_SHIFT 8
+#define DRAMC_PGSZ_256K 0x0000
+#define DRAMC_PGSZ_512K 0x0100
+#define DRAMC_PGSZ_1024K 0x0200
+#define DRAMC_PGSZ_2048K 0x0300
+#define DRAMC_EDO 0x0400 /* EDO DRAM */
+#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
+#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
+#define DRAMC_BC_SHIFT 12
+#define DRAMC_RM 0x4000 /* Refresh Mode */
+#define DRAMC_EN 0x8000 /* DRAM Controller enable */
+
+
+/**********
+ *
+ * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
+ *
+ **********/
+
+/*
+ * ICE Module Address Compare Register
+ */
+#define ICEMACR_ADDR 0xfffffd00
+#define ICEMACR LONG_REF(ICEMACR_ADDR)
+
+/*
+ * ICE Module Address Mask Register
+ */
+#define ICEMAMR_ADDR 0xfffffd04
+#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
+
+/*
+ * ICE Module Control Compare Register
+ */
+#define ICEMCCR_ADDR 0xfffffd08
+#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
+
+#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
+#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
+
+/*
+ * ICE Module Control Mask Register
+ */
+#define ICEMCMR_ADDR 0xfffffd0a
+#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
+
+#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
+#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
+
+/*
+ * ICE Module Control Register
+ */
+#define ICEMCR_ADDR 0xfffffd0c
+#define ICEMCR WORD_REF(ICEMCR_ADDR)
+
+#define ICEMCR_CEN 0x0001 /* Compare Enable */
+#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
+#define ICEMCR_SB 0x0004 /* Single Breakpoint */
+#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
+#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
+
+/*
+ * ICE Module Status Register
+ */
+#define ICEMSR_ADDR 0xfffffd0e
+#define ICEMSR WORD_REF(ICEMSR_ADDR)
+
+#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
+#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
+#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
+#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
+
+#endif /* _MC68VZ328_H_ */
diff --git a/arch/m68k/include/asm/a.out-core.h b/arch/m68k/include/asm/a.out-core.h
new file mode 100644
index 00000000000..f6bfc1d63ff
--- /dev/null
+++ b/arch/m68k/include/asm/a.out-core.h
@@ -0,0 +1,67 @@
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+#include <linux/elfcore.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ struct switch_stack *sw;
+
+/* changed the size calculations - should hopefully work better. lbt */
+ dump->magic = CMAGIC;
+ dump->start_code = 0;
+ dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
+ dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
+ dump->u_dsize = ((unsigned long) (current->mm->brk +
+ (PAGE_SIZE-1))) >> PAGE_SHIFT;
+ dump->u_dsize -= dump->u_tsize;
+ dump->u_ssize = 0;
+
+ if (dump->start_stack < TASK_SIZE)
+ dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
+
+ dump->u_ar0 = offsetof(struct user, regs);
+ sw = ((struct switch_stack *)regs) - 1;
+ dump->regs.d1 = regs->d1;
+ dump->regs.d2 = regs->d2;
+ dump->regs.d3 = regs->d3;
+ dump->regs.d4 = regs->d4;
+ dump->regs.d5 = regs->d5;
+ dump->regs.d6 = sw->d6;
+ dump->regs.d7 = sw->d7;
+ dump->regs.a0 = regs->a0;
+ dump->regs.a1 = regs->a1;
+ dump->regs.a2 = regs->a2;
+ dump->regs.a3 = sw->a3;
+ dump->regs.a4 = sw->a4;
+ dump->regs.a5 = sw->a5;
+ dump->regs.a6 = sw->a6;
+ dump->regs.d0 = regs->d0;
+ dump->regs.orig_d0 = regs->orig_d0;
+ dump->regs.stkadj = regs->stkadj;
+ dump->regs.sr = regs->sr;
+ dump->regs.pc = regs->pc;
+ dump->regs.fmtvec = (regs->format << 12) | regs->vector;
+ /* dump floating point stuff */
+ dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
diff --git a/arch/m68k/include/asm/a.out.h b/arch/m68k/include/asm/a.out.h
new file mode 100644
index 00000000000..3885fe43432
--- /dev/null
+++ b/arch/m68k/include/asm/a.out.h
@@ -0,0 +1,20 @@
+#ifndef __M68K_A_OUT_H__
+#define __M68K_A_OUT_H__
+
+struct exec
+{
+ unsigned long a_info; /* Use macros N_MAGIC, etc for access */
+ unsigned a_text; /* length of text, in bytes */
+ unsigned a_data; /* length of data, in bytes */
+ unsigned a_bss; /* length of uninitialized data area for file, in bytes */
+ unsigned a_syms; /* length of symbol table data in file, in bytes */
+ unsigned a_entry; /* start address */
+ unsigned a_trsize; /* length of relocation info for text, in bytes */
+ unsigned a_drsize; /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a) ((a).a_trsize)
+#define N_DRSIZE(a) ((a).a_drsize)
+#define N_SYMSIZE(a) ((a).a_syms)
+
+#endif /* __M68K_A_OUT_H__ */
diff --git a/arch/m68k/include/asm/adb_iop.h b/arch/m68k/include/asm/adb_iop.h
new file mode 100644
index 00000000000..8a48e56f2d6
--- /dev/null
+++ b/arch/m68k/include/asm/adb_iop.h
@@ -0,0 +1,44 @@
+/*
+ * ADB through the IOP
+ * Written by Joshua M. Thompson
+ */
+
+/* IOP number and channel number for ADB */
+
+#define ADB_IOP IOP_NUM_ISM
+#define ADB_CHAN 2
+
+/* From the A/UX headers...maybe important, maybe not */
+
+#define ADB_IOP_LISTEN 0x01
+#define ADB_IOP_TALK 0x02
+#define ADB_IOP_EXISTS 0x04
+#define ADB_IOP_FLUSH 0x08
+#define ADB_IOP_RESET 0x10
+#define ADB_IOP_INT 0x20
+#define ADB_IOP_POLL 0x40
+#define ADB_IOP_UNINT 0x80
+
+#define AIF_RESET 0x00
+#define AIF_FLUSH 0x01
+#define AIF_LISTEN 0x08
+#define AIF_TALK 0x0C
+
+/* Flag bits in struct adb_iopmsg */
+
+#define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */
+#define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */
+#define ADB_IOP_SRQ 0x04 /* SRQ detected */
+#define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */
+
+#ifndef __ASSEMBLY__
+
+struct adb_iopmsg {
+ __u8 flags; /* ADB flags */
+ __u8 count; /* no. of data bytes */
+ __u8 cmd; /* ADB command */
+ __u8 data[8]; /* ADB data */
+ __u8 spare[21]; /* spare */
+};
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/amigahw.h b/arch/m68k/include/asm/amigahw.h
new file mode 100644
index 00000000000..7a19b5686a4
--- /dev/null
+++ b/arch/m68k/include/asm/amigahw.h
@@ -0,0 +1,349 @@
+/*
+** asm-m68k/amigahw.h -- This header defines some macros and pointers for
+** the various Amiga custom hardware registers.
+** The naming conventions used here conform to those
+** used in the Amiga Hardware Reference Manual, 3rd Edition
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 9/24/92 by Greg Harp
+*/
+
+#ifndef _M68K_AMIGAHW_H
+#define _M68K_AMIGAHW_H
+
+#include <linux/ioport.h>
+
+ /*
+ * Different Amiga models
+ */
+
+#define AMI_UNKNOWN (0)
+#define AMI_500 (1)
+#define AMI_500PLUS (2)
+#define AMI_600 (3)
+#define AMI_1000 (4)
+#define AMI_1200 (5)
+#define AMI_2000 (6)
+#define AMI_2500 (7)
+#define AMI_3000 (8)
+#define AMI_3000T (9)
+#define AMI_3000PLUS (10)
+#define AMI_4000 (11)
+#define AMI_4000T (12)
+#define AMI_CDTV (13)
+#define AMI_CD32 (14)
+#define AMI_DRACO (15)
+
+
+ /*
+ * Chipsets
+ */
+
+extern unsigned long amiga_chipset;
+
+#define CS_STONEAGE (0)
+#define CS_OCS (1)
+#define CS_ECS (2)
+#define CS_AGA (3)
+
+
+ /*
+ * Miscellaneous
+ */
+
+extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */
+extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */
+extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */
+extern unsigned char amiga_vblank; /* VBLANK Frequency */
+
+
+#define AMIGAHW_DECLARE(name) unsigned name : 1
+#define AMIGAHW_SET(name) (amiga_hw_present.name = 1)
+#define AMIGAHW_PRESENT(name) (amiga_hw_present.name)
+
+struct amiga_hw_present {
+ /* video hardware */
+ AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
+ AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
+ AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
+ /* sound hardware */
+ AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
+ /* disk storage interfaces */
+ AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
+ AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
+ AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
+ AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
+ AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
+ AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
+ /* other I/O hardware */
+ AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
+ AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
+ AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
+ AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
+ /* real time clocks */
+ AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
+ AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
+ /* supporting hardware */
+ AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
+ AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
+ AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
+ AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
+ AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
+ AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
+ AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
+ AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
+ AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
+ AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
+ AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
+ AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
+ AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */
+ AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
+ AMIGAHW_DECLARE(ZORRO3); /* Zorro III */
+};
+
+extern struct amiga_hw_present amiga_hw_present;
+
+struct CUSTOM {
+ unsigned short bltddat;
+ unsigned short dmaconr;
+ unsigned short vposr;
+ unsigned short vhposr;
+ unsigned short dskdatr;
+ unsigned short joy0dat;
+ unsigned short joy1dat;
+ unsigned short clxdat;
+ unsigned short adkconr;
+ unsigned short pot0dat;
+ unsigned short pot1dat;
+ unsigned short potgor;
+ unsigned short serdatr;
+ unsigned short dskbytr;
+ unsigned short intenar;
+ unsigned short intreqr;
+ unsigned char *dskptr;
+ unsigned short dsklen;
+ unsigned short dskdat;
+ unsigned short refptr;
+ unsigned short vposw;
+ unsigned short vhposw;
+ unsigned short copcon;
+ unsigned short serdat;
+ unsigned short serper;
+ unsigned short potgo;
+ unsigned short joytest;
+ unsigned short strequ;
+ unsigned short strvbl;
+ unsigned short strhor;
+ unsigned short strlong;
+ unsigned short bltcon0;
+ unsigned short bltcon1;
+ unsigned short bltafwm;
+ unsigned short bltalwm;
+ unsigned char *bltcpt;
+ unsigned char *bltbpt;
+ unsigned char *bltapt;
+ unsigned char *bltdpt;
+ unsigned short bltsize;
+ unsigned char pad2d;
+ unsigned char bltcon0l;
+ unsigned short bltsizv;
+ unsigned short bltsizh;
+ unsigned short bltcmod;
+ unsigned short bltbmod;
+ unsigned short bltamod;
+ unsigned short bltdmod;
+ unsigned short spare2[4];
+ unsigned short bltcdat;
+ unsigned short bltbdat;
+ unsigned short bltadat;
+ unsigned short spare3[3];
+ unsigned short deniseid;
+ unsigned short dsksync;
+ unsigned short *cop1lc;
+ unsigned short *cop2lc;
+ unsigned short copjmp1;
+ unsigned short copjmp2;
+ unsigned short copins;
+ unsigned short diwstrt;
+ unsigned short diwstop;
+ unsigned short ddfstrt;
+ unsigned short ddfstop;
+ unsigned short dmacon;
+ unsigned short clxcon;
+ unsigned short intena;
+ unsigned short intreq;
+ unsigned short adkcon;
+ struct {
+ unsigned short *audlc;
+ unsigned short audlen;
+ unsigned short audper;
+ unsigned short audvol;
+ unsigned short auddat;
+ unsigned short audspare[2];
+ } aud[4];
+ unsigned char *bplpt[8];
+ unsigned short bplcon0;
+ unsigned short bplcon1;
+ unsigned short bplcon2;
+ unsigned short bplcon3;
+ unsigned short bpl1mod;
+ unsigned short bpl2mod;
+ unsigned short bplcon4;
+ unsigned short clxcon2;
+ unsigned short bpldat[8];
+ unsigned char *sprpt[8];
+ struct {
+ unsigned short pos;
+ unsigned short ctl;
+ unsigned short dataa;
+ unsigned short datab;
+ } spr[8];
+ unsigned short color[32];
+ unsigned short htotal;
+ unsigned short hsstop;
+ unsigned short hbstrt;
+ unsigned short hbstop;
+ unsigned short vtotal;
+ unsigned short vsstop;
+ unsigned short vbstrt;
+ unsigned short vbstop;
+ unsigned short sprhstrt;
+ unsigned short sprhstop;
+ unsigned short bplhstrt;
+ unsigned short bplhstop;
+ unsigned short hhposw;
+ unsigned short hhposr;
+ unsigned short beamcon0;
+ unsigned short hsstrt;
+ unsigned short vsstrt;
+ unsigned short hcenter;
+ unsigned short diwhigh;
+ unsigned short spare4[11];
+ unsigned short fmode;
+};
+
+/*
+ * DMA register bits
+ */
+#define DMAF_SETCLR (0x8000)
+#define DMAF_AUD0 (0x0001)
+#define DMAF_AUD1 (0x0002)
+#define DMAF_AUD2 (0x0004)
+#define DMAF_AUD3 (0x0008)
+#define DMAF_DISK (0x0010)
+#define DMAF_SPRITE (0x0020)
+#define DMAF_BLITTER (0x0040)
+#define DMAF_COPPER (0x0080)
+#define DMAF_RASTER (0x0100)
+#define DMAF_MASTER (0x0200)
+#define DMAF_BLITHOG (0x0400)
+#define DMAF_BLTNZERO (0x2000)
+#define DMAF_BLTDONE (0x4000)
+#define DMAF_ALL (0x01FF)
+
+struct CIA {
+ unsigned char pra; char pad0[0xff];
+ unsigned char prb; char pad1[0xff];
+ unsigned char ddra; char pad2[0xff];
+ unsigned char ddrb; char pad3[0xff];
+ unsigned char talo; char pad4[0xff];
+ unsigned char tahi; char pad5[0xff];
+ unsigned char tblo; char pad6[0xff];
+ unsigned char tbhi; char pad7[0xff];
+ unsigned char todlo; char pad8[0xff];
+ unsigned char todmid; char pad9[0xff];
+ unsigned char todhi; char pada[0x1ff];
+ unsigned char sdr; char padb[0xff];
+ unsigned char icr; char padc[0xff];
+ unsigned char cra; char padd[0xff];
+ unsigned char crb; char pade[0xff];
+};
+
+#define zTwoBase (0x80000000)
+#define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase)
+#define ZTWO_VADDR(x) (((unsigned long)(x))+zTwoBase)
+
+#define CUSTOM_PHYSADDR (0xdff000)
+#define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR)))
+
+#define CIAA_PHYSADDR (0xbfe001)
+#define CIAB_PHYSADDR (0xbfd000)
+#define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR)))
+#define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR)))
+
+#define CHIP_PHYSADDR (0x000000)
+
+void amiga_chip_init (void);
+void *amiga_chip_alloc(unsigned long size, const char *name);
+void *amiga_chip_alloc_res(unsigned long size, struct resource *res);
+void amiga_chip_free(void *ptr);
+unsigned long amiga_chip_avail( void ); /*MILAN*/
+extern volatile unsigned short amiga_audio_min_period;
+
+static inline void amifb_video_off(void)
+{
+ if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) {
+ /* program Denise/Lisa for a higher maximum play rate */
+ amiga_custom.htotal = 113; /* 31 kHz */
+ amiga_custom.vtotal = 223; /* 70 Hz */
+ amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */
+ /* suspend the monitor */
+ amiga_custom.hsstrt = amiga_custom.hsstop = 116;
+ amiga_custom.vsstrt = amiga_custom.vsstop = 226;
+ amiga_audio_min_period = 57;
+ }
+}
+
+struct tod3000 {
+ unsigned int :28, second2:4; /* lower digit */
+ unsigned int :28, second1:4; /* upper digit */
+ unsigned int :28, minute2:4; /* lower digit */
+ unsigned int :28, minute1:4; /* upper digit */
+ unsigned int :28, hour2:4; /* lower digit */
+ unsigned int :28, hour1:4; /* upper digit */
+ unsigned int :28, weekday:4;
+ unsigned int :28, day2:4; /* lower digit */
+ unsigned int :28, day1:4; /* upper digit */
+ unsigned int :28, month2:4; /* lower digit */
+ unsigned int :28, month1:4; /* upper digit */
+ unsigned int :28, year2:4; /* lower digit */
+ unsigned int :28, year1:4; /* upper digit */
+ unsigned int :28, cntrl1:4; /* control-byte 1 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl3:4; /* control-byte 3 */
+};
+#define TOD3000_CNTRL1_HOLD 0
+#define TOD3000_CNTRL1_FREE 9
+#define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000)))
+
+struct tod2000 {
+ unsigned int :28, second2:4; /* lower digit */
+ unsigned int :28, second1:4; /* upper digit */
+ unsigned int :28, minute2:4; /* lower digit */
+ unsigned int :28, minute1:4; /* upper digit */
+ unsigned int :28, hour2:4; /* lower digit */
+ unsigned int :28, hour1:4; /* upper digit */
+ unsigned int :28, day2:4; /* lower digit */
+ unsigned int :28, day1:4; /* upper digit */
+ unsigned int :28, month2:4; /* lower digit */
+ unsigned int :28, month1:4; /* upper digit */
+ unsigned int :28, year2:4; /* lower digit */
+ unsigned int :28, year1:4; /* upper digit */
+ unsigned int :28, weekday:4;
+ unsigned int :28, cntrl1:4; /* control-byte 1 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl3:4; /* control-byte 3 */
+};
+
+#define TOD2000_CNTRL1_HOLD (1<<0)
+#define TOD2000_CNTRL1_BUSY (1<<1)
+#define TOD2000_CNTRL3_24HMODE (1<<2)
+#define TOD2000_HOUR1_PM (1<<2)
+#define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000)))
+
+#endif /* _M68K_AMIGAHW_H */
diff --git a/arch/m68k/include/asm/amigaints.h b/arch/m68k/include/asm/amigaints.h
new file mode 100644
index 00000000000..b1bcdb835ab
--- /dev/null
+++ b/arch/m68k/include/asm/amigaints.h
@@ -0,0 +1,113 @@
+/*
+** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created 10/2/92 by Greg Harp
+*/
+
+#ifndef _ASMm68k_AMIGAINTS_H_
+#define _ASMm68k_AMIGAINTS_H_
+
+#include <asm/irq.h>
+
+/*
+** Amiga Interrupt sources.
+**
+*/
+
+#define AUTO_IRQS (8)
+#define AMI_STD_IRQS (14)
+#define CIA_IRQS (5)
+#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
+
+/* builtin serial port interrupts */
+#define IRQ_AMIGA_TBE (IRQ_USER+0)
+#define IRQ_AMIGA_RBF (IRQ_USER+11)
+
+/* floppy disk interrupts */
+#define IRQ_AMIGA_DSKBLK (IRQ_USER+1)
+#define IRQ_AMIGA_DSKSYN (IRQ_USER+12)
+
+/* software interrupts */
+#define IRQ_AMIGA_SOFT (IRQ_USER+2)
+
+/* interrupts from external hardware */
+#define IRQ_AMIGA_PORTS IRQ_AUTO_2
+#define IRQ_AMIGA_EXTER IRQ_AUTO_6
+
+/* copper interrupt */
+#define IRQ_AMIGA_COPPER (IRQ_USER+4)
+
+/* vertical blanking interrupt */
+#define IRQ_AMIGA_VERTB (IRQ_USER+5)
+
+/* Blitter done interrupt */
+#define IRQ_AMIGA_BLIT (IRQ_USER+6)
+
+/* Audio interrupts */
+#define IRQ_AMIGA_AUD0 (IRQ_USER+7)
+#define IRQ_AMIGA_AUD1 (IRQ_USER+8)
+#define IRQ_AMIGA_AUD2 (IRQ_USER+9)
+#define IRQ_AMIGA_AUD3 (IRQ_USER+10)
+
+/* CIA interrupt sources */
+#define IRQ_AMIGA_CIAA (IRQ_USER+14)
+#define IRQ_AMIGA_CIAA_TA (IRQ_USER+14)
+#define IRQ_AMIGA_CIAA_TB (IRQ_USER+15)
+#define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16)
+#define IRQ_AMIGA_CIAA_SP (IRQ_USER+17)
+#define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18)
+#define IRQ_AMIGA_CIAB (IRQ_USER+19)
+#define IRQ_AMIGA_CIAB_TA (IRQ_USER+19)
+#define IRQ_AMIGA_CIAB_TB (IRQ_USER+20)
+#define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21)
+#define IRQ_AMIGA_CIAB_SP (IRQ_USER+22)
+#define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23)
+
+
+/* INTREQR masks */
+#define IF_SETCLR 0x8000 /* set/clr bit */
+#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
+#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
+#define IF_DSKSYN 0x1000 /* disk sync interrupt */
+#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
+#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
+#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
+#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
+#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
+#define IF_BLIT 0x0040 /* blitter done interrupt */
+#define IF_VERTB 0x0020 /* vertical blanking interrupt */
+#define IF_COPER 0x0010 /* copper interrupt */
+#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
+#define IF_SOFT 0x0004 /* software initiated interrupt */
+#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
+#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
+
+/* CIA interrupt control register bits */
+
+#define CIA_ICR_TA 0x01
+#define CIA_ICR_TB 0x02
+#define CIA_ICR_ALRM 0x04
+#define CIA_ICR_SP 0x08
+#define CIA_ICR_FLG 0x10
+#define CIA_ICR_ALL 0x1f
+#define CIA_ICR_SETCLR 0x80
+
+extern void amiga_init_IRQ(void);
+
+/* to access the interrupt control registers of CIA's use only
+** these functions, they behave exactly like the amiga os routines
+*/
+
+extern struct ciabase ciaa_base, ciab_base;
+
+extern void cia_init_IRQ(struct ciabase *base);
+extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask);
+extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask);
+
+#endif /* asm-m68k/amigaints.h */
diff --git a/arch/m68k/include/asm/amigayle.h b/arch/m68k/include/asm/amigayle.h
new file mode 100644
index 00000000000..a01453d9c23
--- /dev/null
+++ b/arch/m68k/include/asm/amigayle.h
@@ -0,0 +1,113 @@
+/*
+** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip
+** found on the Amiga 1200
+** This information was found by disassembling card.resource,
+** so the definitions may not be 100% correct
+** anyone has an official doc ?
+**
+** Copyright 1997 by Alain Malek
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 11/28/97 by Alain Malek
+*/
+
+#ifndef _M68K_AMIGAYLE_H_
+#define _M68K_AMIGAYLE_H_
+
+#include <linux/types.h>
+#include <asm/amigahw.h>
+
+/* memory layout */
+
+#define GAYLE_RAM (0x600000+zTwoBase)
+#define GAYLE_RAMSIZE (0x400000)
+#define GAYLE_ATTRIBUTE (0xa00000+zTwoBase)
+#define GAYLE_ATTRIBUTESIZE (0x020000)
+#define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */
+#define GAYLE_IOSIZE (0x010000)
+#define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */
+
+/* offset for accessing odd IO registers */
+#define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1)
+
+/* GAYLE registers */
+
+struct GAYLE {
+ u_char cardstatus;
+ u_char pad0[0x1000-1];
+
+ u_char intreq;
+ u_char pad1[0x1000-1];
+
+ u_char inten;
+ u_char pad2[0x1000-1];
+
+ u_char config;
+ u_char pad3[0x1000-1];
+};
+
+#define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */
+
+#define GAYLE_RESET (0xa40000) /* write 0x00 to start reset,
+ read 1 byte to stop reset */
+
+#define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS))
+#define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET))
+
+#define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE))
+
+#if 0
+#define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
+#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
+
+#define gayle_inw(a) readw( GAYLE_IO+(a) )
+#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
+#endif
+
+/* GAYLE_CARDSTATUS bit def */
+
+#define GAYLE_CS_CCDET 0x40 /* credit card detect */
+#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
+#define GAYLE_CS_SC 0x20 /* credit card status change */
+#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
+#define GAYLE_CS_DA 0x10 /* digital audio */
+#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
+#define GAYLE_CS_BSY 0x04 /* credit card busy */
+#define GAYLE_CS_IRQ 0x04 /* interrupt request */
+
+/* GAYLE_IRQ bit def */
+
+#define GAYLE_IRQ_IDE 0x80
+#define GAYLE_IRQ_CCDET 0x40
+#define GAYLE_IRQ_BVD1 0x20
+#define GAYLE_IRQ_SC 0x20
+#define GAYLE_IRQ_BVD2 0x10
+#define GAYLE_IRQ_DA 0x10
+#define GAYLE_IRQ_WR 0x08
+#define GAYLE_IRQ_BSY 0x04
+#define GAYLE_IRQ_IRQ 0x04
+#define GAYLE_IRQ_IDEACK1 0x02
+#define GAYLE_IRQ_IDEACK0 0x01
+
+/* GAYLE_CONFIG bit def
+ (bit 0-1 for program voltage, bit 2-3 for access speed */
+
+#define GAYLE_CFG_0V 0x00
+#define GAYLE_CFG_5V 0x01
+#define GAYLE_CFG_12V 0x02
+
+#define GAYLE_CFG_100NS 0x08
+#define GAYLE_CFG_150NS 0x04
+#define GAYLE_CFG_250NS 0x00
+#define GAYLE_CFG_720NS 0x0c
+
+struct gayle_ide_platform_data {
+ unsigned long base;
+ unsigned long irqport;
+ int explicit_ack; /* A1200 IDE needs explicit ack */
+};
+
+#endif /* asm-m68k/amigayle.h */
diff --git a/arch/m68k/include/asm/amipcmcia.h b/arch/m68k/include/asm/amipcmcia.h
new file mode 100644
index 00000000000..6f1ec1887d8
--- /dev/null
+++ b/arch/m68k/include/asm/amipcmcia.h
@@ -0,0 +1,110 @@
+/*
+** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
+**
+** Copyright 1997 by Alain Malek
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 12/10/97 by Alain Malek
+*/
+
+#ifndef __AMIGA_PCMCIA_H__
+#define __AMIGA_PCMCIA_H__
+
+#include <asm/amigayle.h>
+
+/* prototypes */
+
+void pcmcia_reset(void);
+int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
+void pcmcia_program_voltage(int voltage);
+void pcmcia_access_speed(int speed);
+void pcmcia_write_enable(void);
+void pcmcia_write_disable(void);
+
+static inline u_char pcmcia_read_status(void)
+{
+ return (gayle.cardstatus & 0x7c);
+}
+
+static inline u_char pcmcia_get_intreq(void)
+{
+ return (gayle.intreq);
+}
+
+static inline void pcmcia_ack_int(u_char intreq)
+{
+ gayle.intreq = 0xf8;
+}
+
+static inline void pcmcia_enable_irq(void)
+{
+ gayle.inten |= GAYLE_IRQ_IRQ;
+}
+
+static inline void pcmcia_disable_irq(void)
+{
+ gayle.inten &= ~GAYLE_IRQ_IRQ;
+}
+
+#define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET)
+
+/* valid voltages for pcmcia_ProgramVoltage */
+
+#define PCMCIA_0V 0
+#define PCMCIA_5V 5
+#define PCMCIA_12V 12
+
+/* valid speeds for pcmcia_AccessSpeed */
+
+#define PCMCIA_SPEED_100NS 100
+#define PCMCIA_SPEED_150NS 150
+#define PCMCIA_SPEED_250NS 250
+#define PCMCIA_SPEED_720NS 720
+
+/* PCMCIA Tuple codes */
+
+#define CISTPL_NULL 0x00
+#define CISTPL_DEVICE 0x01
+#define CISTPL_LONGLINK_CB 0x02
+#define CISTPL_CONFIG_CB 0x04
+#define CISTPL_CFTABLE_ENTRY_CB 0x05
+#define CISTPL_LONGLINK_MFC 0x06
+#define CISTPL_BAR 0x07
+#define CISTPL_CHECKSUM 0x10
+#define CISTPL_LONGLINK_A 0x11
+#define CISTPL_LONGLINK_C 0x12
+#define CISTPL_LINKTARGET 0x13
+#define CISTPL_NO_LINK 0x14
+#define CISTPL_VERS_1 0x15
+#define CISTPL_ALTSTR 0x16
+#define CISTPL_DEVICE_A 0x17
+#define CISTPL_JEDEC_C 0x18
+#define CISTPL_JEDEC_A 0x19
+#define CISTPL_CONFIG 0x1a
+#define CISTPL_CFTABLE_ENTRY 0x1b
+#define CISTPL_DEVICE_OC 0x1c
+#define CISTPL_DEVICE_OA 0x1d
+#define CISTPL_DEVICE_GEO 0x1e
+#define CISTPL_DEVICE_GEO_A 0x1f
+#define CISTPL_MANFID 0x20
+#define CISTPL_FUNCID 0x21
+#define CISTPL_FUNCE 0x22
+#define CISTPL_SWIL 0x23
+#define CISTPL_END 0xff
+
+/* FUNCID */
+
+#define CISTPL_FUNCID_MULTI 0x00
+#define CISTPL_FUNCID_MEMORY 0x01
+#define CISTPL_FUNCID_SERIAL 0x02
+#define CISTPL_FUNCID_PARALLEL 0x03
+#define CISTPL_FUNCID_FIXED 0x04
+#define CISTPL_FUNCID_VIDEO 0x05
+#define CISTPL_FUNCID_NETWORK 0x06
+#define CISTPL_FUNCID_AIMS 0x07
+#define CISTPL_FUNCID_SCSI 0x08
+
+#endif
diff --git a/arch/m68k/include/asm/apollodma.h b/arch/m68k/include/asm/apollodma.h
new file mode 100644
index 00000000000..954adc851ad
--- /dev/null
+++ b/arch/m68k/include/asm/apollodma.h
@@ -0,0 +1,248 @@
+/*
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ */
+
+#ifndef _ASM_APOLLO_DMA_H
+#define _ASM_APOLLO_DMA_H
+
+#include <asm/apollohw.h> /* need byte IO */
+#include <linux/spinlock.h> /* And spinlocks */
+#include <linux/delay.h>
+
+
+#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
+#define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE)))
+
+/*
+ * NOTES about DMA transfers:
+ *
+ * controller 1: channels 0-3, byte operations, ports 00-1F
+ * controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ * - ALL registers are 8 bits only, regardless of transfer size
+ * - channel 4 is not used - cascades 1 into 2.
+ * - channels 0-3 are byte - addresses/counts are for physical bytes
+ * - channels 5-7 are word - addresses/counts are for physical words
+ * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ * - transfer count loaded to registers is 1 less than actual count
+ * - controller 2 offsets are all even (2x offsets for controller 1)
+ * - page registers for 5-7 don't use data bit 0, represent 128K pages
+ * - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ * Address mapping for channels 0-3:
+ *
+ * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
+ * | ... | | ... | | ... |
+ * | ... | | ... | | ... |
+ * | ... | | ... | | ... |
+ * P7 ... P0 A7 ... A0 A7 ... A0
+ * | Page | Addr MSB | Addr LSB | (DMA registers)
+ *
+ * Address mapping for channels 5-7:
+ *
+ * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
+ * | ... | \ \ ... \ \ \ ... \ \
+ * | ... | \ \ ... \ \ \ ... \ (not used)
+ * | ... | \ \ ... \ \ \ ... \
+ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
+ * | Page | Addr MSB | Addr LSB | (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+#define MAX_DMA_CHANNELS 8
+
+/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
+#define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
+#define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
+#define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
+#define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
+#define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
+#define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
+#define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
+
+#define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
+#define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
+#define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
+#define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
+#define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
+#define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
+#define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
+#define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
+
+#define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
+#define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
+#define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
+#define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
+#define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
+#define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
+#define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
+#define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
+
+#define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
+#define DMA_CNT_1 (IO_DMA1_BASE+0x03)
+#define DMA_CNT_2 (IO_DMA1_BASE+0x05)
+#define DMA_CNT_3 (IO_DMA1_BASE+0x07)
+#define DMA_CNT_4 (IO_DMA2_BASE+0x02)
+#define DMA_CNT_5 (IO_DMA2_BASE+0x06)
+#define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
+#define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
+
+#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT 0x10
+
+#define DMA_8BIT 0
+#define DMA_16BIT 1
+#define DMA_BUSMASTER 2
+
+extern spinlock_t dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_spin_lock, flags);
+ return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+ if (dmanr<=3)
+ dma_outb(dmanr, DMA1_MASK_REG);
+ else
+ dma_outb(dmanr & 3, DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ if (dmanr<=3)
+ dma_outb(dmanr | 4, DMA1_MASK_REG);
+ else
+ dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+ if (dmanr<=3)
+ dma_outb(0, DMA1_CLEAR_FF_REG);
+ else
+ dma_outb(0, DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+ if (dmanr<=3)
+ dma_outb(mode | dmanr, DMA1_MODE_REG);
+ else
+ dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
+}
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+ if (dmanr <= 3) {
+ dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+ dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+ } else {
+ dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+ dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+ }
+}
+
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ count--;
+ if (dmanr <= 3) {
+ dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+ dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+ } else {
+ dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+ dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+ }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+ unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+ : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+ /* using short to get 16-bit wrap around */
+ unsigned short count;
+
+ count = 1 + dma_inb(io_port);
+ count += dma_inb(io_port) << 8;
+
+ return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr); /* release it again */
+
+/* These are in arch/m68k/apollo/dma.c: */
+extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
+extern void dma_unmap_page(unsigned short dma_addr);
+
+#endif /* _ASM_APOLLO_DMA_H */
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h
new file mode 100644
index 00000000000..a1373b9aa28
--- /dev/null
+++ b/arch/m68k/include/asm/apollohw.h
@@ -0,0 +1,108 @@
+/* apollohw.h : some structures to access apollo HW */
+
+#ifndef _ASMm68k_APOLLOHW_H_
+#define _ASMm68k_APOLLOHW_H_
+
+#include <linux/types.h>
+
+/*
+ apollo models
+*/
+
+extern u_long apollo_model;
+
+#define APOLLO_UNKNOWN (0)
+#define APOLLO_DN3000 (1)
+#define APOLLO_DN3010 (2)
+#define APOLLO_DN3500 (3)
+#define APOLLO_DN4000 (4)
+#define APOLLO_DN4500 (5)
+
+/*
+ see scn2681 data sheet for more info.
+ member names are read_write.
+*/
+
+#define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x
+
+struct SCN2681 {
+
+ DECLARE_2681_FIELD(mra);
+ DECLARE_2681_FIELD(sra_csra);
+ DECLARE_2681_FIELD(BRGtest_cra);
+ DECLARE_2681_FIELD(rhra_thra);
+ DECLARE_2681_FIELD(ipcr_acr);
+ DECLARE_2681_FIELD(isr_imr);
+ DECLARE_2681_FIELD(ctu_ctur);
+ DECLARE_2681_FIELD(ctl_ctlr);
+ DECLARE_2681_FIELD(mrb);
+ DECLARE_2681_FIELD(srb_csrb);
+ DECLARE_2681_FIELD(tst_crb);
+ DECLARE_2681_FIELD(rhrb_thrb);
+ DECLARE_2681_FIELD(reserved);
+ DECLARE_2681_FIELD(ip_opcr);
+ DECLARE_2681_FIELD(startCnt_setOutBit);
+ DECLARE_2681_FIELD(stopCnt_resetOutBit);
+
+};
+
+#if 0
+struct mc146818 {
+
+ unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4,
+ minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4;
+ unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4,
+ day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4;
+ unsigned int month1:4, month2:4, year1:4, year2:4, :16;
+
+};
+#endif
+
+struct mc146818 {
+ unsigned char second, alarm_second;
+ unsigned char minute, alarm_minute;
+ unsigned char hours, alarm_hours;
+ unsigned char day_of_week, day_of_month;
+ unsigned char month, year;
+};
+
+
+#define IO_BASE 0x80000000
+
+extern u_long sio01_physaddr;
+extern u_long sio23_physaddr;
+extern u_long rtc_physaddr;
+extern u_long pica_physaddr;
+extern u_long picb_physaddr;
+extern u_long cpuctrl_physaddr;
+extern u_long timer_physaddr;
+
+#define SAU7_SIO01_PHYSADDR 0x10400
+#define SAU7_SIO23_PHYSADDR 0x10500
+#define SAU7_RTC_PHYSADDR 0x10900
+#define SAU7_PICA 0x11000
+#define SAU7_PICB 0x11100
+#define SAU7_CPUCTRL 0x10100
+#define SAU7_TIMER 0x010800
+
+#define SAU8_SIO01_PHYSADDR 0x8400
+#define SAU8_RTC_PHYSADDR 0x8900
+#define SAU8_PICA 0x9400
+#define SAU8_PICB 0x9500
+#define SAU8_CPUCTRL 0x8100
+#define SAU8_TIMER 0x8800
+
+#define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
+#define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
+#define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
+#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
+#define pica (IO_BASE + pica_physaddr)
+#define picb (IO_BASE + picb_physaddr)
+#define timer (IO_BASE + timer_physaddr)
+#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
+
+#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
+
+#define IRQ_APOLLO IRQ_USER
+
+#endif
diff --git a/arch/m68k/include/asm/asm-offsets.h b/arch/m68k/include/asm/asm-offsets.h
new file mode 100644
index 00000000000..d370ee36a18
--- /dev/null
+++ b/arch/m68k/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/m68k/include/asm/atafd.h b/arch/m68k/include/asm/atafd.h
new file mode 100644
index 00000000000..8456889ee7d
--- /dev/null
+++ b/arch/m68k/include/asm/atafd.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_M68K_FD_H
+#define _ASM_M68K_FD_H
+
+/* Definitions for the Atari Floppy driver */
+
+struct atari_format_descr {
+ int track; /* to be formatted */
+ int head; /* "" "" */
+ int sect_offset; /* offset of first sector */
+};
+
+#endif
diff --git a/arch/m68k/include/asm/atafdreg.h b/arch/m68k/include/asm/atafdreg.h
new file mode 100644
index 00000000000..bbf80949fd9
--- /dev/null
+++ b/arch/m68k/include/asm/atafdreg.h
@@ -0,0 +1,79 @@
+#ifndef _LINUX_FDREG_H
+#define _LINUX_FDREG_H
+
+/*
+** WD1772 stuff
+ */
+
+/* register codes */
+
+#define FDCSELREG_STP (0x80) /* command/status register */
+#define FDCSELREG_TRA (0x82) /* track register */
+#define FDCSELREG_SEC (0x84) /* sector register */
+#define FDCSELREG_DTA (0x86) /* data register */
+
+/* register names for FDC_READ/WRITE macros */
+
+#define FDCREG_CMD 0
+#define FDCREG_STATUS 0
+#define FDCREG_TRACK 2
+#define FDCREG_SECTOR 4
+#define FDCREG_DATA 6
+
+/* command opcodes */
+
+#define FDCCMD_RESTORE (0x00) /* - */
+#define FDCCMD_SEEK (0x10) /* | */
+#define FDCCMD_STEP (0x20) /* | TYP 1 Commands */
+#define FDCCMD_STIN (0x40) /* | */
+#define FDCCMD_STOT (0x60) /* - */
+#define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */
+#define FDCCMD_WRSEC (0xa0) /* - " */
+#define FDCCMD_RDADR (0xc0) /* - */
+#define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */
+#define FDCCMD_WRTRA (0xf0) /* - */
+#define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */
+
+/* command modifier bits */
+
+#define FDCCMDADD_SR6 (0x00) /* step rate settings */
+#define FDCCMDADD_SR12 (0x01)
+#define FDCCMDADD_SR2 (0x02)
+#define FDCCMDADD_SR3 (0x03)
+#define FDCCMDADD_V (0x04) /* verify */
+#define FDCCMDADD_H (0x08) /* wait for spin-up */
+#define FDCCMDADD_U (0x10) /* update track register */
+#define FDCCMDADD_M (0x10) /* multiple sector access */
+#define FDCCMDADD_E (0x04) /* head settling flag */
+#define FDCCMDADD_P (0x02) /* precompensation off */
+#define FDCCMDADD_A0 (0x01) /* DAM flag */
+
+/* status register bits */
+
+#define FDCSTAT_MOTORON (0x80) /* motor on */
+#define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */
+#define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */
+#define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
+#define FDCSTAT_RECNF (0x10) /* record not found */
+#define FDCSTAT_CRC (0x08) /* CRC error */
+#define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */
+#define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */
+#define FDCSTAT_IDX (0x02) /* Index status (Type I) */
+#define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */
+#define FDCSTAT_BUSY (0x01) /* FDC is busy */
+
+
+/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
+#define DSKSIDE (0x01)
+
+#define DSKDRVNONE (0x06)
+#define DSKDRV0 (0x02)
+#define DSKDRV1 (0x04)
+
+/* step rates */
+#define FDCSTEP_6 0x00
+#define FDCSTEP_12 0x01
+#define FDCSTEP_2 0x02
+#define FDCSTEP_3 0x03
+
+#endif
diff --git a/arch/m68k/include/asm/atari_joystick.h b/arch/m68k/include/asm/atari_joystick.h
new file mode 100644
index 00000000000..93be7da9f2c
--- /dev/null
+++ b/arch/m68k/include/asm/atari_joystick.h
@@ -0,0 +1,22 @@
+#ifndef _LINUX_ATARI_JOYSTICK_H
+#define _LINUX_ATARI_JOYSTICK_H
+
+/*
+ * linux/include/linux/atari_joystick.h
+ * header file for Atari Joystick driver
+ * by Robert de Vries (robert@and.nl) on 19Jul93
+ */
+
+void atari_joystick_interrupt(char*);
+int atari_joystick_init(void);
+extern int atari_mouse_buttons;
+
+struct joystick_status {
+ char fire;
+ char dir;
+ int ready;
+ int active;
+ wait_queue_head_t wait;
+};
+
+#endif
diff --git a/arch/m68k/include/asm/atari_stdma.h b/arch/m68k/include/asm/atari_stdma.h
new file mode 100644
index 00000000000..8e389b7fa70
--- /dev/null
+++ b/arch/m68k/include/asm/atari_stdma.h
@@ -0,0 +1,22 @@
+
+#ifndef _atari_stdma_h
+#define _atari_stdma_h
+
+
+#include <linux/interrupt.h>
+
+
+/***************************** Prototypes *****************************/
+
+void stdma_lock(irq_handler_t handler, void *data);
+void stdma_release( void );
+int stdma_others_waiting( void );
+int stdma_islocked( void );
+void *stdma_locked_by( void );
+void stdma_init( void );
+
+/************************* End of Prototypes **************************/
+
+
+
+#endif /* _atari_stdma_h */
diff --git a/arch/m68k/include/asm/atari_stram.h b/arch/m68k/include/asm/atari_stram.h
new file mode 100644
index 00000000000..62e27598af9
--- /dev/null
+++ b/arch/m68k/include/asm/atari_stram.h
@@ -0,0 +1,16 @@
+#ifndef _M68K_ATARI_STRAM_H
+#define _M68K_ATARI_STRAM_H
+
+/*
+ * Functions for Atari ST-RAM management
+ */
+
+/* public interface */
+void *atari_stram_alloc(unsigned long size, const char *owner);
+void atari_stram_free(void *);
+
+/* functions called internally by other parts of the kernel */
+void atari_stram_init(void);
+void atari_stram_reserve_pages(void *start_mem);
+
+#endif /*_M68K_ATARI_STRAM_H */
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
new file mode 100644
index 00000000000..c0cb3635077
--- /dev/null
+++ b/arch/m68k/include/asm/atarihw.h
@@ -0,0 +1,809 @@
+/*
+** linux/atarihw.h -- This header defines some macros and pointers for
+** the various Atari custom hardware registers.
+**
+** Copyright 1994 by Björn Brauel
+**
+** 5/1/94 Roman Hodek:
+** Added definitions for TT specific chips.
+**
+** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
+** Finally added definitions for the matrix/codec and the DSP56001 host
+** interface.
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _LINUX_ATARIHW_H_
+#define _LINUX_ATARIHW_H_
+
+#include <linux/types.h>
+#include <asm/bootinfo.h>
+#include <asm/raw_io.h>
+
+extern u_long atari_mch_cookie;
+extern u_long atari_mch_type;
+extern u_long atari_switches;
+extern int atari_rtc_year_offset;
+extern int atari_dont_touch_floppy_select;
+
+extern int atari_SCC_reset_done;
+
+/* convenience macros for testing machine type */
+#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
+#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
+ (atari_mch_cookie & 0xffff) == 0)
+#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
+ (atari_mch_cookie & 0xffff) == 0x10)
+#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
+#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
+#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
+#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
+
+/* values for atari_switches */
+#define ATARI_SWITCH_IKBD 0x01
+#define ATARI_SWITCH_MIDI 0x02
+#define ATARI_SWITCH_SND6 0x04
+#define ATARI_SWITCH_SND7 0x08
+#define ATARI_SWITCH_OVSC_SHIFT 16
+#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_MASK 0xffff0000
+
+/*
+ * Define several Hardware-Chips for indication so that for the ATARI we do
+ * no longer decide whether it is a Falcon or other machine . It's just
+ * important what hardware the machine uses
+ */
+
+/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
+
+#define ATARIHW_DECLARE(name) unsigned name : 1
+#define ATARIHW_SET(name) (atari_hw_present.name = 1)
+#define ATARIHW_PRESENT(name) (atari_hw_present.name)
+
+struct atari_hw_present {
+ /* video hardware */
+ ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
+ ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
+ ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
+ ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
+ /* sound hardware */
+ ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
+ ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
+ ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
+ /* disk storage interfaces */
+ ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
+ ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
+ ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
+ ATARIHW_DECLARE(IDE); /* IDE Interface */
+ ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
+ /* other I/O hardware */
+ ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
+ without it... but who knows?) */
+ ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
+ ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
+ ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
+ ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
+ and Falcon */
+ ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
+ /* DMA */
+ ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
+ ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
+ ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
+ ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
+ /* real time clocks */
+ ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
+ ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
+ /* supporting hardware */
+ ATARIHW_DECLARE(SCU); /* System Control Unit */
+ ATARIHW_DECLARE(BLITTER); /* Blitter */
+ ATARIHW_DECLARE(VME); /* VME Bus */
+ ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
+};
+
+extern struct atari_hw_present atari_hw_present;
+
+
+/* Reading the MFP port register gives a machine independent delay, since the
+ * MFP always has a 8 MHz clock. This avoids problems with the varying length
+ * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
+ */
+#define MFPDELAY() \
+ __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
+
+/* Do cache push/invalidate for DMA read/write. This function obeys the
+ * snooping on some machines (Medusa) and processors: The Medusa itself can
+ * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
+ * reads from memory). Both '040 and '060 invalidate cache entries on snooped
+ * DMA reads (i.e., writes to memory).
+ */
+
+
+#define atari_readb raw_inb
+#define atari_writeb raw_outb
+
+#define atari_inb_p raw_inb
+#define atari_outb_p raw_outb
+
+
+
+#include <linux/mm.h>
+#include <asm/cacheflush.h>
+
+static inline void dma_cache_maintenance( unsigned long paddr,
+ unsigned long len,
+ int writeflag )
+
+{
+ if (writeflag) {
+ if (!MACH_IS_MEDUSA || CPU_IS_060)
+ cache_push( paddr, len );
+ }
+ else {
+ if (!MACH_IS_MEDUSA)
+ cache_clear( paddr, len );
+ }
+}
+
+
+/*
+** Shifter
+ */
+#define ST_LOW 0
+#define ST_MID 1
+#define ST_HIGH 2
+#define TT_LOW 7
+#define TT_MID 4
+#define TT_HIGH 6
+
+#define SHF_BAS (0xffff8200)
+struct SHIFTER
+ {
+ u_char pad1;
+ u_char bas_hi;
+ u_char pad2;
+ u_char bas_md;
+ u_char pad3;
+ u_char volatile vcounthi;
+ u_char pad4;
+ u_char volatile vcountmid;
+ u_char pad5;
+ u_char volatile vcountlow;
+ u_char volatile syncmode;
+ u_char pad6;
+ u_char pad7;
+ u_char bas_lo;
+ };
+# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
+
+#define SHF_FBAS (0xffff820e)
+struct SHIFTER_F030
+ {
+ u_short off_next;
+ u_short scn_width;
+ };
+# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
+
+
+#define SHF_TBAS (0xffff8200)
+struct SHIFTER_TT {
+ u_char char_dummy0;
+ u_char bas_hi; /* video mem base addr, high and mid byte */
+ u_char char_dummy1;
+ u_char bas_md;
+ u_char char_dummy2;
+ u_char vcount_hi; /* pointer to currently displayed byte */
+ u_char char_dummy3;
+ u_char vcount_md;
+ u_char char_dummy4;
+ u_char vcount_lo;
+ u_short st_sync; /* ST compatible sync mode register, unused */
+ u_char char_dummy5;
+ u_char bas_lo; /* video mem addr, low byte */
+ u_char char_dummy6[2+3*16];
+ /* $ffff8240: */
+ u_short color_reg[16]; /* 16 color registers */
+ u_char st_shiftmode; /* ST compatible shift mode register, unused */
+ u_char char_dummy7;
+ u_short tt_shiftmode; /* TT shift mode register */
+
+
+};
+#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
+
+/* values for shifter_tt->tt_shiftmode */
+#define TT_SHIFTER_STLOW 0x0000
+#define TT_SHIFTER_STMID 0x0100
+#define TT_SHIFTER_STHIGH 0x0200
+#define TT_SHIFTER_TTLOW 0x0700
+#define TT_SHIFTER_TTMID 0x0400
+#define TT_SHIFTER_TTHIGH 0x0600
+#define TT_SHIFTER_MODEMASK 0x0700
+#define TT_SHIFTER_NUMMODE 0x0008
+#define TT_SHIFTER_PALETTE_MASK 0x000f
+#define TT_SHIFTER_GRAYMODE 0x1000
+
+/* 256 TT palette registers */
+#define TT_PALETTE_BASE (0xffff8400)
+#define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
+
+#define TT_PALETTE_RED_MASK 0x0f00
+#define TT_PALETTE_GREEN_MASK 0x00f0
+#define TT_PALETTE_BLUE_MASK 0x000f
+
+/*
+** Falcon030 VIDEL Video Controller
+** for description see File 'linux\tools\atari\hardware.txt
+ */
+#define f030_col ((u_long *) 0xffff9800)
+#define f030_xreg ((u_short*) 0xffff8282)
+#define f030_yreg ((u_short*) 0xffff82a2)
+#define f030_creg ((u_short*) 0xffff82c0)
+#define f030_sreg ((u_short*) 0xffff8260)
+#define f030_mreg ((u_short*) 0xffff820a)
+#define f030_linewidth ((u_short*) 0xffff820e)
+#define f030_hscroll ((u_char*) 0xffff8265)
+
+#define VIDEL_BAS (0xffff8260)
+struct VIDEL {
+ u_short st_shift;
+ u_short pad1;
+ u_char xoffset_s;
+ u_char xoffset;
+ u_short f_shift;
+ u_char pad2[0x1a];
+ u_short hht;
+ u_short hbb;
+ u_short hbe;
+ u_short hdb;
+ u_short hde;
+ u_short hss;
+ u_char pad3[0x14];
+ u_short vft;
+ u_short vbb;
+ u_short vbe;
+ u_short vdb;
+ u_short vde;
+ u_short vss;
+ u_char pad4[0x12];
+ u_short control;
+ u_short mode;
+};
+#define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
+
+/*
+** DMA/WD1772 Disk Controller
+ */
+
+#define FWD_BAS (0xffff8604)
+struct DMA_WD
+ {
+ u_short fdc_acces_seccount;
+ u_short dma_mode_status;
+ u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
+ u_char dma_hi;
+ u_char char_dummy2;
+ u_char dma_md;
+ u_char char_dummy3;
+ u_char dma_lo;
+ u_short fdc_speed;
+ };
+# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
+/* alias */
+#define st_dma dma_wd
+/* The two highest bytes of an extended DMA as a short; this is a must
+ * for the Medusa.
+ */
+#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
+
+/*
+** YM2149 Sound Chip
+** access in bytes
+ */
+
+#define YM_BAS (0xffff8800)
+struct SOUND_YM
+ {
+ u_char rd_data_reg_sel;
+ u_char char_dummy1;
+ u_char wd_data;
+ };
+#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
+
+/* TT SCSI DMA */
+
+#define TT_SCSI_DMA_BAS (0xffff8700)
+struct TT_DMA {
+ u_char char_dummy0;
+ u_char dma_addr_hi;
+ u_char char_dummy1;
+ u_char dma_addr_hmd;
+ u_char char_dummy2;
+ u_char dma_addr_lmd;
+ u_char char_dummy3;
+ u_char dma_addr_lo;
+ u_char char_dummy4;
+ u_char dma_cnt_hi;
+ u_char char_dummy5;
+ u_char dma_cnt_hmd;
+ u_char char_dummy6;
+ u_char dma_cnt_lmd;
+ u_char char_dummy7;
+ u_char dma_cnt_lo;
+ u_long dma_restdata;
+ u_short dma_ctrl;
+};
+#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
+
+/* TT SCSI Controller 5380 */
+
+#define TT_5380_BAS (0xffff8781)
+struct TT_5380 {
+ u_char scsi_data;
+ u_char char_dummy1;
+ u_char scsi_icr;
+ u_char char_dummy2;
+ u_char scsi_mode;
+ u_char char_dummy3;
+ u_char scsi_tcr;
+ u_char char_dummy4;
+ u_char scsi_idstat;
+ u_char char_dummy5;
+ u_char scsi_dmastat;
+ u_char char_dummy6;
+ u_char scsi_targrcv;
+ u_char char_dummy7;
+ u_char scsi_inircv;
+};
+#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
+#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
+
+
+/*
+** Falcon DMA Sound Subsystem
+ */
+
+#define MATRIX_BASE (0xffff8930)
+struct MATRIX
+{
+ u_short source;
+ u_short destination;
+ u_char external_frequency_divider;
+ u_char internal_frequency_divider;
+};
+#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
+
+#define CODEC_BASE (0xffff8936)
+struct CODEC
+{
+ u_char tracks;
+ u_char input_source;
+#define CODEC_SOURCE_ADC 1
+#define CODEC_SOURCE_MATRIX 2
+ u_char adc_source;
+#define ADC_SOURCE_RIGHT_PSG 1
+#define ADC_SOURCE_LEFT_PSG 2
+ u_char gain;
+#define CODEC_GAIN_RIGHT 0x0f
+#define CODEC_GAIN_LEFT 0xf0
+ u_char attenuation;
+#define CODEC_ATTENUATION_RIGHT 0x0f
+#define CODEC_ATTENUATION_LEFT 0xf0
+ u_char unused1;
+ u_char status;
+#define CODEC_OVERFLOW_RIGHT 1
+#define CODEC_OVERFLOW_LEFT 2
+ u_char unused2, unused3, unused4, unused5;
+ u_char gpio_directions;
+#define CODEC_GPIO_IN 0
+#define CODEC_GPIO_OUT 1
+ u_char unused6;
+ u_char gpio_data;
+};
+#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
+
+/*
+** Falcon Blitter
+*/
+
+#define BLT_BAS (0xffff8a00)
+
+struct BLITTER
+ {
+ u_short halftone[16];
+ u_short src_x_inc;
+ u_short src_y_inc;
+ u_long src_address;
+ u_short endmask1;
+ u_short endmask2;
+ u_short endmask3;
+ u_short dst_x_inc;
+ u_short dst_y_inc;
+ u_long dst_address;
+ u_short wd_per_line;
+ u_short ln_per_bb;
+ u_short hlf_op_reg;
+ u_short log_op_reg;
+ u_short lin_nm_reg;
+ u_short skew_reg;
+ };
+# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
+
+
+/*
+** SCC Z8530
+ */
+
+#define SCC_BAS (0xffff8c81)
+struct SCC
+ {
+ u_char cha_a_ctrl;
+ u_char char_dummy1;
+ u_char cha_a_data;
+ u_char char_dummy2;
+ u_char cha_b_ctrl;
+ u_char char_dummy3;
+ u_char cha_b_data;
+ };
+# define atari_scc ((*(volatile struct SCC*)SCC_BAS))
+
+/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
+# define st_escc ((*(volatile struct SCC*)0xfffffa31))
+# define st_escc_dsr ((*(volatile char *)0xfffffa39))
+
+/* TT SCC DMA Controller (same chip as SCSI DMA) */
+
+#define TT_SCC_DMA_BAS (0xffff8c00)
+#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
+
+/*
+** VIDEL Palette Register
+ */
+
+#define FPL_BAS (0xffff9800)
+struct VIDEL_PALETTE
+ {
+ u_long reg[256];
+ };
+# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
+
+
+/*
+** Falcon DSP Host Interface
+ */
+
+#define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
+struct DSP56K_HOST_INTERFACE {
+ u_char icr;
+#define DSP56K_ICR_RREQ 0x01
+#define DSP56K_ICR_TREQ 0x02
+#define DSP56K_ICR_HF0 0x08
+#define DSP56K_ICR_HF1 0x10
+#define DSP56K_ICR_HM0 0x20
+#define DSP56K_ICR_HM1 0x40
+#define DSP56K_ICR_INIT 0x80
+
+ u_char cvr;
+#define DSP56K_CVR_HV_MASK 0x1f
+#define DSP56K_CVR_HC 0x80
+
+ u_char isr;
+#define DSP56K_ISR_RXDF 0x01
+#define DSP56K_ISR_TXDE 0x02
+#define DSP56K_ISR_TRDY 0x04
+#define DSP56K_ISR_HF2 0x08
+#define DSP56K_ISR_HF3 0x10
+#define DSP56K_ISR_DMA 0x40
+#define DSP56K_ISR_HREQ 0x80
+
+ u_char ivr;
+
+ union {
+ u_char b[4];
+ u_short w[2];
+ u_long l;
+ } data;
+};
+#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
+
+/*
+** MFP 68901
+ */
+
+#define MFP_BAS (0xfffffa01)
+struct MFP
+ {
+ u_char par_dt_reg;
+ u_char char_dummy1;
+ u_char active_edge;
+ u_char char_dummy2;
+ u_char data_dir;
+ u_char char_dummy3;
+ u_char int_en_a;
+ u_char char_dummy4;
+ u_char int_en_b;
+ u_char char_dummy5;
+ u_char int_pn_a;
+ u_char char_dummy6;
+ u_char int_pn_b;
+ u_char char_dummy7;
+ u_char int_sv_a;
+ u_char char_dummy8;
+ u_char int_sv_b;
+ u_char char_dummy9;
+ u_char int_mk_a;
+ u_char char_dummy10;
+ u_char int_mk_b;
+ u_char char_dummy11;
+ u_char vec_adr;
+ u_char char_dummy12;
+ u_char tim_ct_a;
+ u_char char_dummy13;
+ u_char tim_ct_b;
+ u_char char_dummy14;
+ u_char tim_ct_cd;
+ u_char char_dummy15;
+ u_char tim_dt_a;
+ u_char char_dummy16;
+ u_char tim_dt_b;
+ u_char char_dummy17;
+ u_char tim_dt_c;
+ u_char char_dummy18;
+ u_char tim_dt_d;
+ u_char char_dummy19;
+ u_char sync_char;
+ u_char char_dummy20;
+ u_char usart_ctr;
+ u_char char_dummy21;
+ u_char rcv_stat;
+ u_char char_dummy22;
+ u_char trn_stat;
+ u_char char_dummy23;
+ u_char usart_dta;
+ };
+# define st_mfp ((*(volatile struct MFP*)MFP_BAS))
+
+/* TT's second MFP */
+
+#define TT_MFP_BAS (0xfffffa81)
+# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
+
+
+/* TT System Control Unit */
+
+#define TT_SCU_BAS (0xffff8e01)
+struct TT_SCU {
+ u_char sys_mask;
+ u_char char_dummy1;
+ u_char sys_stat;
+ u_char char_dummy2;
+ u_char softint;
+ u_char char_dummy3;
+ u_char vmeint;
+ u_char char_dummy4;
+ u_char gp_reg1;
+ u_char char_dummy5;
+ u_char gp_reg2;
+ u_char char_dummy6;
+ u_char vme_mask;
+ u_char char_dummy7;
+ u_char vme_stat;
+};
+#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
+
+/* TT real time clock */
+
+#define TT_RTC_BAS (0xffff8961)
+struct TT_RTC {
+ u_char regsel;
+ u_char dummy;
+ u_char data;
+};
+#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
+
+
+/*
+** ACIA 6850
+ */
+/* constants for the ACIA registers */
+
+/* baudrate selection and reset (Baudrate = clock/factor) */
+#define ACIA_DIV1 0
+#define ACIA_DIV16 1
+#define ACIA_DIV64 2
+#define ACIA_RESET 3
+
+/* character format */
+#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
+#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
+#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
+#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
+#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
+#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
+#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
+#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
+
+/* transmit control */
+#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
+#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
+#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
+#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
+
+/* receive control */
+#define ACIA_RID (0<<7) /* RxINT disabled */
+#define ACIA_RIE (1<<7) /* RxINT enabled */
+
+/* status fields of the ACIA */
+#define ACIA_RDRF 1 /* Receive Data Register Full */
+#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
+#define ACIA_DCD (1<<2) /* Data Carrier Detect */
+#define ACIA_CTS (1<<3) /* Clear To Send */
+#define ACIA_FE (1<<4) /* Framing Error */
+#define ACIA_OVRN (1<<5) /* Receiver Overrun */
+#define ACIA_PE (1<<6) /* Parity Error */
+#define ACIA_IRQ (1<<7) /* Interrupt Request */
+
+#define ACIA_BAS (0xfffffc00)
+struct ACIA
+ {
+ u_char key_ctrl;
+ u_char char_dummy1;
+ u_char key_data;
+ u_char char_dummy2;
+ u_char mid_ctrl;
+ u_char char_dummy3;
+ u_char mid_data;
+ };
+# define acia ((*(volatile struct ACIA*)ACIA_BAS))
+
+#define TT_DMASND_BAS (0xffff8900)
+struct TT_DMASND {
+ u_char int_ctrl; /* Falcon: Interrupt control */
+ u_char ctrl;
+ u_char pad2;
+ u_char bas_hi;
+ u_char pad3;
+ u_char bas_mid;
+ u_char pad4;
+ u_char bas_low;
+ u_char pad5;
+ u_char addr_hi;
+ u_char pad6;
+ u_char addr_mid;
+ u_char pad7;
+ u_char addr_low;
+ u_char pad8;
+ u_char end_hi;
+ u_char pad9;
+ u_char end_mid;
+ u_char pad10;
+ u_char end_low;
+ u_char pad11[12];
+ u_char track_select; /* Falcon */
+ u_char mode;
+ u_char pad12[14];
+ /* Falcon only: */
+ u_short cbar_src;
+ u_short cbar_dst;
+ u_char ext_div;
+ u_char int_div;
+ u_char rec_track_select;
+ u_char dac_src;
+ u_char adc_src;
+ u_char input_gain;
+ u_short output_atten;
+};
+# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
+
+#define DMASND_MFP_INT_REPLAY 0x01
+#define DMASND_MFP_INT_RECORD 0x02
+#define DMASND_TIMERA_INT_REPLAY 0x04
+#define DMASND_TIMERA_INT_RECORD 0x08
+
+#define DMASND_CTRL_OFF 0x00
+#define DMASND_CTRL_ON 0x01
+#define DMASND_CTRL_REPEAT 0x02
+#define DMASND_CTRL_RECORD_ON 0x10
+#define DMASND_CTRL_RECORD_OFF 0x00
+#define DMASND_CTRL_RECORD_REPEAT 0x20
+#define DMASND_CTRL_SELECT_REPLAY 0x00
+#define DMASND_CTRL_SELECT_RECORD 0x80
+#define DMASND_MODE_MONO 0x80
+#define DMASND_MODE_STEREO 0x00
+#define DMASND_MODE_8BIT 0x00
+#define DMASND_MODE_16BIT 0x40 /* Falcon only */
+#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
+#define DMASND_MODE_12KHZ 0x01
+#define DMASND_MODE_25KHZ 0x02
+#define DMASND_MODE_50KHZ 0x03
+
+
+#define DMASNDSetBase(bufstart) \
+ do { \
+ tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
+ tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
+ tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
+ } while( 0 )
+
+#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
+ (tt_dmasnd.addr_mid << 8) + \
+ (tt_dmasnd.addr_low))
+
+#define DMASNDSetEnd(bufend) \
+ do { \
+ tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
+ tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
+ tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
+ } while( 0 )
+
+
+#define TT_MICROWIRE_BAS (0xffff8922)
+struct TT_MICROWIRE {
+ u_short data;
+ u_short mask;
+};
+# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
+
+#define MW_LM1992_ADDR 0x0400
+
+#define MW_LM1992_VOLUME(dB) \
+ (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
+#define MW_LM1992_BALLEFT(dB) \
+ (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
+#define MW_LM1992_BALRIGHT(dB) \
+ (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
+#define MW_LM1992_TREBLE(dB) \
+ (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
+#define MW_LM1992_BASS(dB) \
+ (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
+
+#define MW_LM1992_PSG_LOW 0x000
+#define MW_LM1992_PSG_HIGH 0x001
+#define MW_LM1992_PSG_OFF 0x002
+
+#define MSTE_RTC_BAS (0xfffffc21)
+
+struct MSTE_RTC {
+ u_char sec_ones;
+ u_char dummy1;
+ u_char sec_tens;
+ u_char dummy2;
+ u_char min_ones;
+ u_char dummy3;
+ u_char min_tens;
+ u_char dummy4;
+ u_char hr_ones;
+ u_char dummy5;
+ u_char hr_tens;
+ u_char dummy6;
+ u_char weekday;
+ u_char dummy7;
+ u_char day_ones;
+ u_char dummy8;
+ u_char day_tens;
+ u_char dummy9;
+ u_char mon_ones;
+ u_char dummy10;
+ u_char mon_tens;
+ u_char dummy11;
+ u_char year_ones;
+ u_char dummy12;
+ u_char year_tens;
+ u_char dummy13;
+ u_char mode;
+ u_char dummy14;
+ u_char test;
+ u_char dummy15;
+ u_char reset;
+};
+
+#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
+
+#endif /* linux/atarihw.h */
+
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
new file mode 100644
index 00000000000..656bbbf5a6f
--- /dev/null
+++ b/arch/m68k/include/asm/atariints.h
@@ -0,0 +1,204 @@
+/*
+** atariints.h -- Atari Linux interrupt handling structs and prototypes
+**
+** Copyright 1994 by Björn Brauel
+**
+** 5/2/94 Roman Hodek:
+** TT interrupt definitions added.
+**
+** 12/02/96: (Roman)
+** Adapted to new int handling scheme (see ataints.c); revised numbering
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _LINUX_ATARIINTS_H_
+#define _LINUX_ATARIINTS_H_
+
+#include <asm/irq.h>
+#include <asm/atarihw.h>
+
+/*
+** Atari Interrupt sources.
+**
+*/
+
+#define STMFP_SOURCE_BASE 8
+#define TTMFP_SOURCE_BASE 24
+#define SCC_SOURCE_BASE 40
+#define VME_SOURCE_BASE 56
+#define VME_MAX_SOURCES 16
+
+#define NUM_ATARI_SOURCES (VME_SOURCE_BASE+VME_MAX_SOURCES-STMFP_SOURCE_BASE)
+
+/* convert vector number to int source number */
+#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
+
+/* convert irq_handler index to vector number */
+#define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8)))
+
+/* interrupt service types */
+#define IRQ_TYPE_SLOW 0
+#define IRQ_TYPE_FAST 1
+#define IRQ_TYPE_PRIO 2
+
+/* ST-MFP interrupts */
+#define IRQ_MFP_BUSY (8)
+#define IRQ_MFP_DCD (9)
+#define IRQ_MFP_CTS (10)
+#define IRQ_MFP_GPU (11)
+#define IRQ_MFP_TIMD (12)
+#define IRQ_MFP_TIMC (13)
+#define IRQ_MFP_ACIA (14)
+#define IRQ_MFP_FDC (15)
+#define IRQ_MFP_ACSI IRQ_MFP_FDC
+#define IRQ_MFP_FSCSI IRQ_MFP_FDC
+#define IRQ_MFP_IDE IRQ_MFP_FDC
+#define IRQ_MFP_TIMB (16)
+#define IRQ_MFP_SERERR (17)
+#define IRQ_MFP_SEREMPT (18)
+#define IRQ_MFP_RECERR (19)
+#define IRQ_MFP_RECFULL (20)
+#define IRQ_MFP_TIMA (21)
+#define IRQ_MFP_RI (22)
+#define IRQ_MFP_MMD (23)
+
+/* TT-MFP interrupts */
+#define IRQ_TT_MFP_IO0 (24)
+#define IRQ_TT_MFP_IO1 (25)
+#define IRQ_TT_MFP_SCC (26)
+#define IRQ_TT_MFP_RI (27)
+#define IRQ_TT_MFP_TIMD (28)
+#define IRQ_TT_MFP_TIMC (29)
+#define IRQ_TT_MFP_DRVRDY (30)
+#define IRQ_TT_MFP_SCSIDMA (31)
+#define IRQ_TT_MFP_TIMB (32)
+#define IRQ_TT_MFP_SERERR (33)
+#define IRQ_TT_MFP_SEREMPT (34)
+#define IRQ_TT_MFP_RECERR (35)
+#define IRQ_TT_MFP_RECFULL (36)
+#define IRQ_TT_MFP_TIMA (37)
+#define IRQ_TT_MFP_RTC (38)
+#define IRQ_TT_MFP_SCSI (39)
+
+/* SCC interrupts */
+#define IRQ_SCCB_TX (40)
+#define IRQ_SCCB_STAT (42)
+#define IRQ_SCCB_RX (44)
+#define IRQ_SCCB_SPCOND (46)
+#define IRQ_SCCA_TX (48)
+#define IRQ_SCCA_STAT (50)
+#define IRQ_SCCA_RX (52)
+#define IRQ_SCCA_SPCOND (54)
+
+
+#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
+#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
+
+
+#define MFP_ENABLE 0
+#define MFP_PENDING 1
+#define MFP_SERVICE 2
+#define MFP_MASK 3
+
+/* Utility functions for setting/clearing bits in the interrupt registers of
+ * the MFP. 'type' should be constant, if 'irq' is constant, too, code size is
+ * reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */
+
+static inline int get_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = 1 << (irq & 7);
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ return( *reg & mask );
+}
+
+static inline void set_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = 1 << (irq & 7);
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ __asm__ __volatile__ ( "orb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+}
+
+static inline void clear_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = ~(1 << (irq & 7));
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ if (type == MFP_PENDING || type == MFP_SERVICE)
+ __asm__ __volatile__ ( "moveb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+ else
+ __asm__ __volatile__ ( "andb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+}
+
+/*
+ * {en,dis}able_irq have the usual semantics of temporary blocking the
+ * interrupt, but not losing requests that happen between disabling and
+ * enabling. This is done with the MFP mask registers.
+ */
+
+static inline void atari_enable_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ set_mfp_bit( irq, MFP_MASK );
+}
+
+static inline void atari_disable_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_MASK );
+}
+
+/*
+ * In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not
+ * "stored"
+ */
+
+static inline void atari_turnon_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ set_mfp_bit( irq, MFP_ENABLE );
+}
+
+static inline void atari_turnoff_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_ENABLE );
+ clear_mfp_bit( irq, MFP_PENDING );
+}
+
+static inline void atari_clear_pending_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_PENDING );
+}
+
+static inline int atari_irq_pending( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 );
+ return( get_mfp_bit( irq, MFP_PENDING ) );
+}
+
+unsigned long atari_register_vme_int( void );
+void atari_unregister_vme_int( unsigned long );
+
+#endif /* linux/atariints.h */
diff --git a/arch/m68k/include/asm/atarikb.h b/arch/m68k/include/asm/atarikb.h
new file mode 100644
index 00000000000..68f3622bf59
--- /dev/null
+++ b/arch/m68k/include/asm/atarikb.h
@@ -0,0 +1,44 @@
+/*
+** atarikb.h -- This header contains the prototypes of functions of
+** the intelligent keyboard of the Atari needed by the
+** mouse and joystick drivers.
+**
+** Copyright 1994 by Robert de Vries
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 20 Feb 1994 by Robert de Vries
+*/
+
+#ifndef _LINUX_ATARIKB_H
+#define _LINUX_ATARIKB_H
+
+void ikbd_write(const char *, int);
+void ikbd_mouse_button_action(int mode);
+void ikbd_mouse_rel_pos(void);
+void ikbd_mouse_abs_pos(int xmax, int ymax);
+void ikbd_mouse_kbd_mode(int dx, int dy);
+void ikbd_mouse_thresh(int x, int y);
+void ikbd_mouse_scale(int x, int y);
+void ikbd_mouse_pos_get(int *x, int *y);
+void ikbd_mouse_pos_set(int x, int y);
+void ikbd_mouse_y0_bot(void);
+void ikbd_mouse_y0_top(void);
+void ikbd_mouse_disable(void);
+void ikbd_joystick_event_on(void);
+void ikbd_joystick_event_off(void);
+void ikbd_joystick_get_state(void);
+void ikbd_joystick_disable(void);
+
+/* Hook for MIDI serial driver */
+extern void (*atari_MIDI_interrupt_hook) (void);
+/* Hook for keyboard inputdev driver */
+extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char);
+/* Hook for mouse inputdev driver */
+extern void (*atari_input_mouse_interrupt_hook) (char *);
+
+int atari_keyb_init(void);
+
+#endif /* _LINUX_ATARIKB_H */
diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h
new file mode 100644
index 00000000000..4eba796c00d
--- /dev/null
+++ b/arch/m68k/include/asm/atomic.h
@@ -0,0 +1,218 @@
+#ifndef __ARCH_M68K_ATOMIC__
+#define __ARCH_M68K_ATOMIC__
+
+#include <linux/types.h>
+#include <asm/system.h>
+
+/*
+ * Atomic operations that C can't guarantee us. Useful for
+ * resource counting etc..
+ */
+
+/*
+ * We do not have SMP m68k systems, so we don't have to deal with that.
+ */
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) (*(volatile int *)&(v)->counter)
+#define atomic_set(v, i) (((v)->counter) = i)
+
+/*
+ * The ColdFire parts cannot do some immediate to memory operations,
+ * so for them we do not specify the "i" asm constraint.
+ */
+#ifdef CONFIG_COLDFIRE
+#define ASM_DI "d"
+#else
+#define ASM_DI "di"
+#endif
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i));
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i));
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ __asm__ __volatile__("addql #1,%0" : "+m" (*v));
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ __asm__ __volatile__("subql #1,%0" : "+m" (*v));
+}
+
+static inline int atomic_dec_and_test(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
+ return c != 0;
+}
+
+static inline int atomic_dec_and_test_lt(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__(
+ "subql #1,%1; slt %0"
+ : "=d" (c), "=m" (*v)
+ : "m" (*v));
+ return c != 0;
+}
+
+static inline int atomic_inc_and_test(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
+ return c != 0;
+}
+
+#ifdef CONFIG_RMW_INSNS
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+ int t, tmp;
+
+ __asm__ __volatile__(
+ "1: movel %2,%1\n"
+ " addl %3,%1\n"
+ " casl %2,%1,%0\n"
+ " jne 1b"
+ : "+m" (*v), "=&d" (t), "=&d" (tmp)
+ : "g" (i), "2" (atomic_read(v)));
+ return t;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+ int t, tmp;
+
+ __asm__ __volatile__(
+ "1: movel %2,%1\n"
+ " subl %3,%1\n"
+ " casl %2,%1,%0\n"
+ " jne 1b"
+ : "+m" (*v), "=&d" (t), "=&d" (tmp)
+ : "g" (i), "2" (atomic_read(v)));
+ return t;
+}
+
+#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+#else /* !CONFIG_RMW_INSNS */
+
+static inline int atomic_add_return(int i, atomic_t * v)
+{
+ unsigned long flags;
+ int t;
+
+ local_irq_save(flags);
+ t = atomic_read(v);
+ t += i;
+ atomic_set(v, t);
+ local_irq_restore(flags);
+
+ return t;
+}
+
+static inline int atomic_sub_return(int i, atomic_t * v)
+{
+ unsigned long flags;
+ int t;
+
+ local_irq_save(flags);
+ t = atomic_read(v);
+ t -= i;
+ atomic_set(v, t);
+ local_irq_restore(flags);
+
+ return t;
+}
+
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+ unsigned long flags;
+ int prev;
+
+ local_irq_save(flags);
+ prev = atomic_read(v);
+ if (prev == old)
+ atomic_set(v, new);
+ local_irq_restore(flags);
+ return prev;
+}
+
+static inline int atomic_xchg(atomic_t *v, int new)
+{
+ unsigned long flags;
+ int prev;
+
+ local_irq_save(flags);
+ prev = atomic_read(v);
+ atomic_set(v, new);
+ local_irq_restore(flags);
+ return prev;
+}
+
+#endif /* !CONFIG_RMW_INSNS */
+
+#define atomic_dec_return(v) atomic_sub_return(1, (v))
+#define atomic_inc_return(v) atomic_add_return(1, (v))
+
+static inline int atomic_sub_and_test(int i, atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("subl %2,%1; seq %0"
+ : "=d" (c), "+m" (*v)
+ : ASM_DI (i));
+ return c != 0;
+}
+
+static inline int atomic_add_negative(int i, atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("addl %2,%1; smi %0"
+ : "=d" (c), "+m" (*v)
+ : ASM_DI (i));
+ return c != 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
+{
+ __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask)));
+}
+
+static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
+{
+ __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask));
+}
+
+static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ int c, old;
+ c = atomic_read(v);
+ for (;;) {
+ if (unlikely(c == (u)))
+ break;
+ old = atomic_cmpxchg((v), c, c + (a));
+ if (likely(old == c))
+ break;
+ c = old;
+ }
+ return c;
+}
+
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec() barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc() barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#endif /* __ARCH_M68K_ATOMIC __ */
diff --git a/arch/m68k/include/asm/auxvec.h b/arch/m68k/include/asm/auxvec.h
new file mode 100644
index 00000000000..844d6d52204
--- /dev/null
+++ b/arch/m68k/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMm68k_AUXVEC_H
+#define __ASMm68k_AUXVEC_H
+
+#endif
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
new file mode 100644
index 00000000000..c6baa913592
--- /dev/null
+++ b/arch/m68k/include/asm/bitops.h
@@ -0,0 +1,530 @@
+#ifndef _M68K_BITOPS_H
+#define _M68K_BITOPS_H
+/*
+ * Copyright 1992, Linus Torvalds.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+
+/*
+ * Bit access functions vary across the ColdFire and 68k families.
+ * So we will break them out here, and then macro in the ones we want.
+ *
+ * ColdFire - supports standard bset/bclr/bchg with register operand only
+ * 68000 - supports standard bset/bclr/bchg with memory operand
+ * >= 68020 - also supports the bfset/bfclr/bfchg instructions
+ *
+ * Although it is possible to use only the bset/bclr/bchg with register
+ * operands on all platforms you end up with larger generated code.
+ * So we use the best form possible on a given platform.
+ */
+
+static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bset %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bset %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfset %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define set_bit(nr, vaddr) bset_reg_set_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define set_bit(nr, vaddr) bset_mem_set_bit(nr, vaddr)
+#else
+#define set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bset_mem_set_bit(nr, vaddr) : \
+ bfset_mem_set_bit(nr, vaddr))
+#endif
+
+#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
+
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+
+static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bclr %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bclr %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfclr %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define clear_bit(nr, vaddr) bclr_reg_clear_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define clear_bit(nr, vaddr) bclr_mem_clear_bit(nr, vaddr)
+#else
+#define clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bclr_mem_clear_bit(nr, vaddr) : \
+ bfclr_mem_clear_bit(nr, vaddr))
+#endif
+
+#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
+
+
+static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bchg %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bchg %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfchg %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define change_bit(nr, vaddr) bchg_reg_change_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define change_bit(nr, vaddr) bchg_mem_change_bit(nr, vaddr)
+#else
+#define change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bchg_mem_change_bit(nr, vaddr) : \
+ bfchg_mem_change_bit(nr, vaddr))
+#endif
+
+#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
+
+
+static inline int test_bit(int nr, const unsigned long *vaddr)
+{
+ return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
+}
+
+
+static inline int bset_reg_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bset %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bset_mem_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bset %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfset_mem_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_set_bit(nr, vaddr) bset_reg_test_and_set_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_set_bit(nr, vaddr) bset_mem_test_and_set_bit(nr, vaddr)
+#else
+#define test_and_set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bset_mem_test_and_set_bit(nr, vaddr) : \
+ bfset_mem_test_and_set_bit(nr, vaddr))
+#endif
+
+#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
+
+
+static inline int bclr_reg_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bclr %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bclr_mem_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bclr %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfclr_mem_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_clear_bit(nr, vaddr) bclr_reg_test_and_clear_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_clear_bit(nr, vaddr) bclr_mem_test_and_clear_bit(nr, vaddr)
+#else
+#define test_and_clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bclr_mem_test_and_clear_bit(nr, vaddr) : \
+ bfclr_mem_test_and_clear_bit(nr, vaddr))
+#endif
+
+#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
+
+
+static inline int bchg_reg_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bchg %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bchg_mem_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bchg %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfchg_mem_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_change_bit(nr, vaddr) bchg_reg_test_and_change_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_change_bit(nr, vaddr) bchg_mem_test_and_change_bit(nr, vaddr)
+#else
+#define test_and_change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bchg_mem_test_and_change_bit(nr, vaddr) : \
+ bfchg_mem_test_and_change_bit(nr, vaddr))
+#endif
+
+#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
+
+
+/*
+ * The true 68020 and more advanced processors support the "bfffo"
+ * instruction for finding bits. ColdFire and simple 68000 parts
+ * (including CPU32) do not support this. They simply use the generic
+ * functions.
+ */
+#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ffz.h>
+#else
+
+static inline int find_first_zero_bit(const unsigned long *vaddr,
+ unsigned size)
+{
+ const unsigned long *p = vaddr;
+ int res = 32;
+ unsigned int words;
+ unsigned long num;
+
+ if (!size)
+ return 0;
+
+ words = (size + 31) >> 5;
+ while (!(num = ~*p++)) {
+ if (!--words)
+ goto out;
+ }
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ res ^= 31;
+out:
+ res += ((long)p - (long)vaddr - 4) * 8;
+ return res < size ? res : size;
+}
+#define find_first_zero_bit find_first_zero_bit
+
+static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
+ int offset)
+{
+ const unsigned long *p = vaddr + (offset >> 5);
+ int bit = offset & 31UL, res;
+
+ if (offset >= size)
+ return size;
+
+ if (bit) {
+ unsigned long num = ~*p++ & (~0UL << bit);
+ offset -= bit;
+
+ /* Look for zero in first longword */
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ if (res < 32) {
+ offset += res ^ 31;
+ return offset < size ? offset : size;
+ }
+ offset += 32;
+
+ if (offset >= size)
+ return size;
+ }
+ /* No zero yet, search remaining full bytes for a zero */
+ return offset + find_first_zero_bit(p, size - offset);
+}
+#define find_next_zero_bit find_next_zero_bit
+
+static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
+{
+ const unsigned long *p = vaddr;
+ int res = 32;
+ unsigned int words;
+ unsigned long num;
+
+ if (!size)
+ return 0;
+
+ words = (size + 31) >> 5;
+ while (!(num = *p++)) {
+ if (!--words)
+ goto out;
+ }
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ res ^= 31;
+out:
+ res += ((long)p - (long)vaddr - 4) * 8;
+ return res < size ? res : size;
+}
+#define find_first_bit find_first_bit
+
+static inline int find_next_bit(const unsigned long *vaddr, int size,
+ int offset)
+{
+ const unsigned long *p = vaddr + (offset >> 5);
+ int bit = offset & 31UL, res;
+
+ if (offset >= size)
+ return size;
+
+ if (bit) {
+ unsigned long num = *p++ & (~0UL << bit);
+ offset -= bit;
+
+ /* Look for one in first longword */
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ if (res < 32) {
+ offset += res ^ 31;
+ return offset < size ? offset : size;
+ }
+ offset += 32;
+
+ if (offset >= size)
+ return size;
+ }
+ /* No one yet, search remaining full bytes for a one */
+ return offset + find_first_bit(p, size - offset);
+}
+#define find_next_bit find_next_bit
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+ int res;
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (~word & -~word));
+ return res ^ 31;
+}
+
+#endif
+
+#ifdef __KERNEL__
+
+#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+
+/*
+ * The newer ColdFire family members support a "bitrev" instruction
+ * and we can use that to implement a fast ffs. Older Coldfire parts,
+ * and normal 68000 parts don't have anything special, so we use the
+ * generic functions for those.
+ */
+#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \
+ !defined(CONFIG_M68000) && !defined(CONFIG_MCPU32)
+static inline int __ffs(int x)
+{
+ __asm__ __volatile__ ("bitrev %0; ff1 %0"
+ : "=d" (x)
+ : "0" (x));
+ return x;
+}
+
+static inline int ffs(int x)
+{
+ if (!x)
+ return 0;
+ return __ffs(x) + 1;
+}
+
+#else
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/__ffs.h>
+#endif
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+
+#else
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+ int cnt;
+
+ __asm__ ("bfffo %1{#0:#0},%0"
+ : "=d" (cnt)
+ : "dm" (x & -x));
+ return 32 - cnt;
+}
+#define __ffs(x) (ffs(x) - 1)
+
+/*
+ * fls: find last bit set.
+ */
+static inline int fls(int x)
+{
+ int cnt;
+
+ __asm__ ("bfffo %1{#0,#0},%0"
+ : "=d" (cnt)
+ : "dm" (x));
+ return 32 - cnt;
+}
+
+static inline int __fls(int x)
+{
+ return fls(x) - 1;
+}
+
+#endif
+
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/le.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+#endif /* __KERNEL__ */
+
+#endif /* _M68K_BITOPS_H */
diff --git a/arch/m68k/include/asm/bitsperlong.h b/arch/m68k/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..6dc0bb0c13b
--- /dev/null
+++ b/arch/m68k/include/asm/bitsperlong.h
@@ -0,0 +1 @@
+#include <asm-generic/bitsperlong.h>
diff --git a/arch/m68k/include/asm/blinken.h b/arch/m68k/include/asm/blinken.h
new file mode 100644
index 00000000000..0626582a7db
--- /dev/null
+++ b/arch/m68k/include/asm/blinken.h
@@ -0,0 +1,32 @@
+/*
+** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
+**
+** (c) 1998 Phil Blundell <philb@gnu.org>
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _M68K_BLINKEN_H
+#define _M68K_BLINKEN_H
+
+#include <asm/setup.h>
+#include <asm/io.h>
+
+#define HP300_LEDS 0xf001ffff
+
+extern unsigned char hp300_ledstate;
+
+static __inline__ void blinken_leds(int on, int off)
+{
+ if (MACH_IS_HP300)
+ {
+ hp300_ledstate |= on;
+ hp300_ledstate &= ~off;
+ out_8(HP300_LEDS, ~hp300_ledstate);
+ }
+}
+
+#endif
diff --git a/arch/m68k/include/asm/bootinfo.h b/arch/m68k/include/asm/bootinfo.h
new file mode 100644
index 00000000000..67e7a78ad96
--- /dev/null
+++ b/arch/m68k/include/asm/bootinfo.h
@@ -0,0 +1,378 @@
+/*
+** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created 09/29/92 by Greg Harp
+**
+** 5/2/94 Roman Hodek:
+** Added bi_atari part of the machine dependent union bi_un; for now it
+** contains just a model field to distinguish between TT and Falcon.
+** 26/7/96 Roman Zippel:
+** Renamed to setup.h; added some useful macros to allow gcc some
+** optimizations if possible.
+** 5/10/96 Geert Uytterhoeven:
+** Redesign of the boot information structure; renamed to bootinfo.h again
+** 27/11/96 Geert Uytterhoeven:
+** Backwards compatibility with bootinfo interface version 1.0
+*/
+
+#ifndef _M68K_BOOTINFO_H
+#define _M68K_BOOTINFO_H
+
+
+ /*
+ * Bootinfo definitions
+ *
+ * This is an easily parsable and extendable structure containing all
+ * information to be passed from the bootstrap to the kernel.
+ *
+ * This way I hope to keep all future changes back/forewards compatible.
+ * Thus, keep your fingers crossed...
+ *
+ * This structure is copied right after the kernel bss by the bootstrap
+ * routine.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct bi_record {
+ unsigned short tag; /* tag ID */
+ unsigned short size; /* size of record (in bytes) */
+ unsigned long data[0]; /* data */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+ /*
+ * Tag Definitions
+ *
+ * Machine independent tags start counting from 0x0000
+ * Machine dependent tags start counting from 0x8000
+ */
+
+#define BI_LAST 0x0000 /* last record (sentinel) */
+#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
+#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
+#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
+#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
+#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
+ /* (struct mem_info) */
+#define BI_RAMDISK 0x0006 /* ramdisk address and size */
+ /* (struct mem_info) */
+#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
+ /* (string) */
+
+ /*
+ * Amiga-specific tags
+ */
+
+#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */
+#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */
+ /* (struct ConfigDev) */
+#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */
+#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */
+#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */
+#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */
+#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */
+#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */
+
+ /*
+ * Atari-specific tags
+ */
+
+#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */
+#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */
+ /* (values are ATARI_MACH_* defines */
+
+/* mch_cookie values (upper word) */
+#define ATARI_MCH_ST 0
+#define ATARI_MCH_STE 1
+#define ATARI_MCH_TT 2
+#define ATARI_MCH_FALCON 3
+
+/* mch_type values */
+#define ATARI_MACH_NORMAL 0 /* no special machine type */
+#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */
+#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */
+#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */
+
+ /*
+ * VME-specific tags
+ */
+
+#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */
+#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */
+
+/* BI_VME_TYPE codes */
+#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */
+#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */
+#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */
+#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */
+#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */
+#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */
+#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */
+#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */
+#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */
+
+/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on
+ * Motorola VME boards. Contains board number, Bug version, board
+ * configuration options, etc. See include/asm/mvme16xhw.h for details.
+ */
+
+
+ /*
+ * Macintosh-specific tags (all u_long)
+ */
+
+#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
+#define BI_MAC_VADDR 0x8001 /* Mac video base address */
+#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
+#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
+#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
+#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
+#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
+#define BI_MAC_BTIME 0x8007 /* Mac boot time */
+#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
+#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
+#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
+#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
+
+ /*
+ * Macintosh hardware profile data - unused, see macintosh.h for
+ * reasonable type values
+ */
+
+#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
+#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
+#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
+#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
+#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
+#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
+#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
+#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
+#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
+#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
+#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
+#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
+#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
+#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
+#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
+#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
+#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
+#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
+
+ /*
+ * Mac: compatibility with old booter data format (temporarily)
+ * Fields unused with the new bootinfo can be deleted now; instead of
+ * adding new fields the struct might be splitted into a hardware address
+ * part and a hardware type part
+ */
+
+#ifndef __ASSEMBLY__
+
+struct mac_booter_data
+{
+ unsigned long videoaddr;
+ unsigned long videorow;
+ unsigned long videodepth;
+ unsigned long dimensions;
+ unsigned long args;
+ unsigned long boottime;
+ unsigned long gmtbias;
+ unsigned long bootver;
+ unsigned long videological;
+ unsigned long sccbase;
+ unsigned long id;
+ unsigned long memsize;
+ unsigned long serialmf;
+ unsigned long serialhsk;
+ unsigned long serialgpi;
+ unsigned long printmf;
+ unsigned long printhsk;
+ unsigned long printgpi;
+ unsigned long cpuid;
+ unsigned long rombase;
+ unsigned long adbdelay;
+ unsigned long timedbra;
+};
+
+extern struct mac_booter_data
+ mac_bi_data;
+
+#endif
+
+ /*
+ * Apollo-specific tags
+ */
+
+#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */
+
+ /*
+ * HP300-specific tags
+ */
+
+#define BI_HP300_MODEL 0x8000 /* model (u_long) */
+#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */
+#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */
+
+ /*
+ * Stuff for bootinfo interface versioning
+ *
+ * At the start of kernel code, a 'struct bootversion' is located.
+ * bootstrap checks for a matching version of the interface before booting
+ * a kernel, to avoid user confusion if kernel and bootstrap don't work
+ * together :-)
+ *
+ * If incompatible changes are made to the bootinfo interface, the major
+ * number below should be stepped (and the minor reset to 0) for the
+ * appropriate machine. If a change is backward-compatible, the minor
+ * should be stepped. "Backwards-compatible" means that booting will work,
+ * but certain features may not.
+ */
+
+#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
+#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor))
+#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
+#define BI_VERSION_MINOR(v) ((v) & 0xffff)
+
+#ifndef __ASSEMBLY__
+
+struct bootversion {
+ unsigned short branch;
+ unsigned long magic;
+ struct {
+ unsigned long machtype;
+ unsigned long version;
+ } machversions[0];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 )
+#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 )
+
+#ifdef BOOTINFO_COMPAT_1_0
+
+ /*
+ * Backwards compatibility with bootinfo interface version 1.0
+ */
+
+#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
+#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
+#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
+
+#include <linux/zorro.h>
+
+#define COMPAT_NUM_AUTO 16
+
+struct compat_bi_Amiga {
+ int model;
+ int num_autocon;
+ struct ConfigDev autocon[COMPAT_NUM_AUTO];
+ unsigned long chip_size;
+ unsigned char vblank;
+ unsigned char psfreq;
+ unsigned long eclock;
+ unsigned long chipset;
+ unsigned long hw_present;
+};
+
+struct compat_bi_Atari {
+ unsigned long hw_present;
+ unsigned long mch_cookie;
+};
+
+#ifndef __ASSEMBLY__
+
+struct compat_bi_Macintosh
+{
+ unsigned long videoaddr;
+ unsigned long videorow;
+ unsigned long videodepth;
+ unsigned long dimensions;
+ unsigned long args;
+ unsigned long boottime;
+ unsigned long gmtbias;
+ unsigned long bootver;
+ unsigned long videological;
+ unsigned long sccbase;
+ unsigned long id;
+ unsigned long memsize;
+ unsigned long serialmf;
+ unsigned long serialhsk;
+ unsigned long serialgpi;
+ unsigned long printmf;
+ unsigned long printhsk;
+ unsigned long printgpi;
+ unsigned long cpuid;
+ unsigned long rombase;
+ unsigned long adbdelay;
+ unsigned long timedbra;
+};
+
+#endif
+
+struct compat_mem_info {
+ unsigned long addr;
+ unsigned long size;
+};
+
+#define COMPAT_NUM_MEMINFO 4
+
+#define COMPAT_CPUB_68020 0
+#define COMPAT_CPUB_68030 1
+#define COMPAT_CPUB_68040 2
+#define COMPAT_CPUB_68060 3
+#define COMPAT_FPUB_68881 5
+#define COMPAT_FPUB_68882 6
+#define COMPAT_FPUB_68040 7
+#define COMPAT_FPUB_68060 8
+
+#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020)
+#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030)
+#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040)
+#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060)
+#define COMPAT_CPU_MASK (31)
+#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881)
+#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882)
+#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040)
+#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060)
+#define COMPAT_FPU_MASK (0xfe0)
+
+#define COMPAT_CL_SIZE (256)
+
+struct compat_bootinfo {
+ unsigned long machtype;
+ unsigned long cputype;
+ struct compat_mem_info memory[COMPAT_NUM_MEMINFO];
+ int num_memory;
+ unsigned long ramdisk_size;
+ unsigned long ramdisk_addr;
+ char command_line[COMPAT_CL_SIZE];
+ union {
+ struct compat_bi_Amiga bi_ami;
+ struct compat_bi_Atari bi_ata;
+ struct compat_bi_Macintosh bi_mac;
+ } bi_un;
+};
+
+#define bi_amiga bi_un.bi_ami
+#define bi_atari bi_un.bi_ata
+#define bi_mac bi_un.bi_mac
+
+#endif /* BOOTINFO_COMPAT_1_0 */
+
+
+#endif /* _M68K_BOOTINFO_H */
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
new file mode 100644
index 00000000000..e518f5a575b
--- /dev/null
+++ b/arch/m68k/include/asm/bootstd.h
@@ -0,0 +1,132 @@
+/* bootstd.h: Bootloader system call interface
+ *
+ * (c) 1999, Rt-Control, Inc.
+ */
+
+#ifndef __BOOTSTD_H__
+#define __BOOTSTD_H__
+
+#define NR_BSC 21 /* last used bootloader system call */
+
+#define __BN_reset 0 /* reset and start the bootloader */
+#define __BN_test 1 /* tests the system call interface */
+#define __BN_exec 2 /* executes a bootloader image */
+#define __BN_exit 3 /* terminates a bootloader image */
+#define __BN_program 4 /* program FLASH from a chain */
+#define __BN_erase 5 /* erase sector(s) of FLASH */
+#define __BN_open 6
+#define __BN_write 7
+#define __BN_read 8
+#define __BN_close 9
+#define __BN_mmap 10 /* map a file descriptor into memory */
+#define __BN_munmap 11 /* remove a file to memory mapping */
+#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */
+#define __BN_getserialnum 13 /* get the serial number of this board */
+#define __BN_getbenv 14 /* get a bootloader envvar */
+#define __BN_setbenv 15 /* get a bootloader envvar */
+#define __BN_setpmask 16 /* set the protection mask */
+#define __BN_readenv 17 /* read environment variables */
+#define __BN_flash_chattr_range 18
+#define __BN_flash_erase_range 19
+#define __BN_flash_write_range 20
+
+/* Calling conventions compatible to (uC)linux/68k
+ * We use similar macros to call into the bootloader as for uClinux
+ */
+
+#define __bsc_return(type, res) \
+do { \
+ if ((unsigned long)(res) >= (unsigned long)(-64)) { \
+ /* let errno be a function, preserve res in %d0 */ \
+ int __err = -(res); \
+ errno = __err; \
+ res = -1; \
+ } \
+ return (type)(res); \
+} while (0)
+
+#define _bsc0(type,name) \
+type name(void) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc1(type,name,atype,a) \
+type name(atype a) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc2(type,name,atype,a,btype,b) \
+type name(atype a, btype b) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
+type name(atype a, btype b, ctype c) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
+type name(atype a, btype b, ctype c, dtype d) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ register long __d __asm__ ("%d4") = (long)d; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c), "d" (__d) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
+type name(atype a, btype b, ctype c, dtype d, etype e) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ register long __d __asm__ ("%d4") = (long)d; \
+ register long __e __asm__ ("%d5") = (long)e; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c), "d" (__d), "d" (__e) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#endif /* __BOOTSTD_H__ */
diff --git a/arch/m68k/include/asm/bug.h b/arch/m68k/include/asm/bug.h
new file mode 100644
index 00000000000..ef9a2e47352
--- /dev/null
+++ b/arch/m68k/include/asm/bug.h
@@ -0,0 +1,30 @@
+#ifndef _M68K_BUG_H
+#define _M68K_BUG_H
+
+#ifdef CONFIG_MMU
+#ifdef CONFIG_BUG
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#ifndef CONFIG_SUN3
+#define BUG() do { \
+ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ __builtin_trap(); \
+} while (0)
+#else
+#define BUG() do { \
+ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ panic("BUG!"); \
+} while (0)
+#endif
+#else
+#define BUG() do { \
+ __builtin_trap(); \
+} while (0)
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+#endif /* CONFIG_MMU */
+
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/arch/m68k/include/asm/bugs.h b/arch/m68k/include/asm/bugs.h
new file mode 100644
index 00000000000..d06207b9ba5
--- /dev/null
+++ b/arch/m68k/include/asm/bugs.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-m68k/bugs.h
+ *
+ * Copyright (C) 1994 Linus Torvalds
+ */
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ * void check_bugs(void);
+ */
+
+#ifdef CONFIG_MMU
+extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */
+#else
+static void check_bugs(void)
+{
+}
+#endif
diff --git a/arch/m68k/include/asm/bvme6000hw.h b/arch/m68k/include/asm/bvme6000hw.h
new file mode 100644
index 00000000000..f40d2f8510e
--- /dev/null
+++ b/arch/m68k/include/asm/bvme6000hw.h
@@ -0,0 +1,150 @@
+#ifndef _M68K_BVME6000HW_H_
+#define _M68K_BVME6000HW_H_
+
+#include <asm/irq.h>
+
+/*
+ * PIT structure
+ */
+
+#define BVME_PIT_BASE 0xffa00000
+
+typedef struct {
+ unsigned char
+ pad_a[3], pgcr,
+ pad_b[3], psrr,
+ pad_c[3], paddr,
+ pad_d[3], pbddr,
+ pad_e[3], pcddr,
+ pad_f[3], pivr,
+ pad_g[3], pacr,
+ pad_h[3], pbcr,
+ pad_i[3], padr,
+ pad_j[3], pbdr,
+ pad_k[3], paar,
+ pad_l[3], pbar,
+ pad_m[3], pcdr,
+ pad_n[3], psr,
+ pad_o[3], res1,
+ pad_p[3], res2,
+ pad_q[3], tcr,
+ pad_r[3], tivr,
+ pad_s[3], res3,
+ pad_t[3], cprh,
+ pad_u[3], cprm,
+ pad_v[3], cprl,
+ pad_w[3], res4,
+ pad_x[3], crh,
+ pad_y[3], crm,
+ pad_z[3], crl,
+ pad_A[3], tsr,
+ pad_B[3], res5;
+} PitRegs_t, *PitRegsPtr;
+
+#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
+
+#define BVME_RTC_BASE 0xff900000
+
+typedef struct {
+ unsigned char
+ pad_a[3], msr,
+ pad_b[3], t0cr_rtmr,
+ pad_c[3], t1cr_omr,
+ pad_d[3], pfr_icr0,
+ pad_e[3], irr_icr1,
+ pad_f[3], bcd_tenms,
+ pad_g[3], bcd_sec,
+ pad_h[3], bcd_min,
+ pad_i[3], bcd_hr,
+ pad_j[3], bcd_dom,
+ pad_k[3], bcd_mth,
+ pad_l[3], bcd_year,
+ pad_m[3], bcd_ujcc,
+ pad_n[3], bcd_hjcc,
+ pad_o[3], bcd_dow,
+ pad_p[3], t0lsb,
+ pad_q[3], t0msb,
+ pad_r[3], t1lsb,
+ pad_s[3], t1msb,
+ pad_t[3], cmp_sec,
+ pad_u[3], cmp_min,
+ pad_v[3], cmp_hr,
+ pad_w[3], cmp_dom,
+ pad_x[3], cmp_mth,
+ pad_y[3], cmp_dow,
+ pad_z[3], sav_sec,
+ pad_A[3], sav_min,
+ pad_B[3], sav_hr,
+ pad_C[3], sav_dom,
+ pad_D[3], sav_mth,
+ pad_E[3], ram,
+ pad_F[3], test;
+} RtcRegs_t, *RtcPtr_t;
+
+
+#define BVME_I596_BASE 0xff100000
+
+#define BVME_ETHIRQ_REG 0xff20000b
+
+#define BVME_LOCAL_IRQ_STAT 0xff20000f
+
+#define BVME_ETHERR 0x02
+#define BVME_ABORT_STATUS 0x08
+
+#define BVME_NCR53C710_BASE 0xff000000
+
+#define BVME_SCC_A_ADDR 0xffb0000b
+#define BVME_SCC_B_ADDR 0xffb00003
+#define BVME_SCC_RTxC 7372800
+
+#define BVME_CONFIG_REG 0xff500003
+
+#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
+
+#define BVME_CONFIG_SW1 0x08
+#define BVME_CONFIG_SW2 0x04
+#define BVME_CONFIG_SW3 0x02
+#define BVME_CONFIG_SW4 0x01
+
+
+#define BVME_IRQ_TYPE_PRIO 0
+
+#define BVME_IRQ_PRN (IRQ_USER+20)
+#define BVME_IRQ_TIMER (IRQ_USER+25)
+#define BVME_IRQ_I596 IRQ_AUTO_2
+#define BVME_IRQ_SCSI IRQ_AUTO_3
+#define BVME_IRQ_RTC IRQ_AUTO_6
+#define BVME_IRQ_ABORT IRQ_AUTO_7
+
+/* SCC interrupts */
+#define BVME_IRQ_SCC_BASE IRQ_USER
+#define BVME_IRQ_SCCB_TX IRQ_USER
+#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
+#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
+#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
+#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
+#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
+#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
+#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
+
+/* Address control registers */
+
+#define BVME_ACR_A32VBA 0xff400003
+#define BVME_ACR_A32MSK 0xff410003
+#define BVME_ACR_A24VBA 0xff420003
+#define BVME_ACR_A24MSK 0xff430003
+#define BVME_ACR_A16VBA 0xff440003
+#define BVME_ACR_A32LBA 0xff450003
+#define BVME_ACR_A24LBA 0xff460003
+#define BVME_ACR_ADDRCTL 0xff470003
+
+#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
+#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
+#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
+#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
+#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
+#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
+#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
+#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
+
+#endif
diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h
new file mode 100644
index 00000000000..31b260a8880
--- /dev/null
+++ b/arch/m68k/include/asm/byteorder.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _M68K_BYTEORDER_H */
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
new file mode 100644
index 00000000000..0395c51e46a
--- /dev/null
+++ b/arch/m68k/include/asm/cache.h
@@ -0,0 +1,13 @@
+/*
+ * include/asm-m68k/cache.h
+ */
+#ifndef __ARCH_M68K_CACHE_H
+#define __ARCH_M68K_CACHE_H
+
+/* bytes per L1 cache line */
+#define L1_CACHE_SHIFT 4
+#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+#endif
diff --git a/arch/m68k/include/asm/cachectl.h b/arch/m68k/include/asm/cachectl.h
new file mode 100644
index 00000000000..525978e959e
--- /dev/null
+++ b/arch/m68k/include/asm/cachectl.h
@@ -0,0 +1,14 @@
+#ifndef _M68K_CACHECTL_H
+#define _M68K_CACHECTL_H
+
+/* Definitions for the cacheflush system call. */
+
+#define FLUSH_SCOPE_LINE 1 /* Flush a cache line */
+#define FLUSH_SCOPE_PAGE 2 /* Flush a page */
+#define FLUSH_SCOPE_ALL 3 /* Flush the whole cache -- superuser only */
+
+#define FLUSH_CACHE_DATA 1 /* Writeback and flush data cache */
+#define FLUSH_CACHE_INSN 2 /* Flush instruction cache */
+#define FLUSH_CACHE_BOTH 3 /* Flush both caches */
+
+#endif /* _M68K_CACHECTL_H */
diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h
new file mode 100644
index 00000000000..a70d7319630
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush.h
@@ -0,0 +1,5 @@
+#ifdef __uClinux__
+#include "cacheflush_no.h"
+#else
+#include "cacheflush_mm.h"
+#endif
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
new file mode 100644
index 00000000000..8104bd87464
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -0,0 +1,235 @@
+#ifndef _M68K_CACHEFLUSH_H
+#define _M68K_CACHEFLUSH_H
+
+#include <linux/mm.h>
+#ifdef CONFIG_COLDFIRE
+#include <asm/mcfsim.h>
+#endif
+
+/* cache code */
+#define FLUSH_I_AND_D (0x00000808)
+#define FLUSH_I (0x00000008)
+
+#ifndef ICACHE_MAX_ADDR
+#define ICACHE_MAX_ADDR 0
+#define ICACHE_SET_MASK 0
+#define DCACHE_MAX_ADDR 0
+#define DCACHE_SETMASK 0
+#endif
+
+static inline void flush_cf_icache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_dcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_bcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+/*
+ * Cache handling functions
+ */
+
+static inline void flush_icache(void)
+{
+ if (CPU_IS_COLDFIRE) {
+ flush_cf_icache(0, ICACHE_MAX_ADDR);
+ } else if (CPU_IS_040_OR_060) {
+ asm volatile ( "nop\n"
+ " .chip 68040\n"
+ " cpusha %bc\n"
+ " .chip 68k");
+ } else {
+ unsigned long tmp;
+ asm volatile ( "movec %%cacr,%0\n"
+ " or.w %1,%0\n"
+ " movec %0,%%cacr"
+ : "=&d" (tmp)
+ : "id" (FLUSH_I));
+ }
+}
+
+/*
+ * invalidate the cache for the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_clear(unsigned long paddr, int len);
+/*
+ * push any dirty cache in the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_push(unsigned long paddr, int len);
+
+/*
+ * push and invalidate pages in the specified user virtual
+ * memory range.
+ */
+extern void cache_push_v(unsigned long vaddr, int len);
+
+/* This is needed whenever the virtual mapping of the current
+ process changes. */
+#define __flush_cache_all() \
+({ \
+ if (CPU_IS_COLDFIRE) { \
+ flush_cf_dcache(0, DCACHE_MAX_ADDR); \
+ } else if (CPU_IS_040_OR_060) { \
+ __asm__ __volatile__("nop\n\t" \
+ ".chip 68040\n\t" \
+ "cpusha %dc\n\t" \
+ ".chip 68k"); \
+ } else { \
+ unsigned long _tmp; \
+ __asm__ __volatile__("movec %%cacr,%0\n\t" \
+ "orw %1,%0\n\t" \
+ "movec %0,%%cacr" \
+ : "=&d" (_tmp) \
+ : "di" (FLUSH_I_AND_D)); \
+ } \
+})
+
+#define __flush_cache_030() \
+({ \
+ if (CPU_IS_020_OR_030) { \
+ unsigned long _tmp; \
+ __asm__ __volatile__("movec %%cacr,%0\n\t" \
+ "orw %1,%0\n\t" \
+ "movec %0,%%cacr" \
+ : "=&d" (_tmp) \
+ : "di" (FLUSH_I_AND_D)); \
+ } \
+})
+
+#define flush_cache_all() __flush_cache_all()
+
+#define flush_cache_vmap(start, end) flush_cache_all()
+#define flush_cache_vunmap(start, end) flush_cache_all()
+
+static inline void flush_cache_mm(struct mm_struct *mm)
+{
+ if (mm == current->mm)
+ __flush_cache_030();
+}
+
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+
+/* flush_cache_range/flush_cache_page must be macros to avoid
+ a dependency on linux/mm.h, which includes this file... */
+static inline void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end)
+{
+ if (vma->vm_mm == current->mm)
+ __flush_cache_030();
+}
+
+static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
+{
+ if (vma->vm_mm == current->mm)
+ __flush_cache_030();
+}
+
+
+/* Push the page at kernel virtual address and clear the icache */
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
+static inline void __flush_page_to_ram(void *vaddr)
+{
+ if (CPU_IS_COLDFIRE) {
+ unsigned long addr, start, end;
+ addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1);
+ start = addr & ICACHE_SET_MASK;
+ end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK;
+ if (start > end) {
+ flush_cf_bcache(0, end);
+ end = ICACHE_MAX_ADDR;
+ }
+ flush_cf_bcache(start, end);
+ } else if (CPU_IS_040_OR_060) {
+ __asm__ __volatile__("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (__pa(vaddr)));
+ } else {
+ unsigned long _tmp;
+ __asm__ __volatile__("movec %%cacr,%0\n\t"
+ "orw %1,%0\n\t"
+ "movec %0,%%cacr"
+ : "=&d" (_tmp)
+ : "di" (FLUSH_I));
+ }
+}
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
+
+extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+ unsigned long addr, int len);
+extern void flush_icache_range(unsigned long address, unsigned long endaddr);
+
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ flush_cache_page(vma, vaddr, page_to_pfn(page));
+ memcpy(dst, src, len);
+ flush_icache_user_range(vma, page, vaddr, len);
+}
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ flush_cache_page(vma, vaddr, page_to_pfn(page));
+ memcpy(dst, src, len);
+}
+
+#endif /* _M68K_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
new file mode 100644
index 00000000000..cb88aa96c4f
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -0,0 +1,79 @@
+#ifndef _M68KNOMMU_CACHEFLUSH_H
+#define _M68KNOMMU_CACHEFLUSH_H
+
+/*
+ * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
+ */
+#include <linux/mm.h>
+#include <asm/mcfsim.h>
+
+#define flush_cache_all() __flush_cache_all()
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_dup_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_dcache_range(start, len) __flush_dcache_all()
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
+#define flush_dcache_page(page) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_range(start, len) __flush_icache_all()
+#define flush_icache_page(vma,pg) do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_vmap(start, end) do { } while (0)
+#define flush_cache_vunmap(start, end) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+
+void mcf_cache_push(void);
+
+static inline void __flush_cache_all(void)
+{
+#ifdef CACHE_PUSH
+ mcf_cache_push();
+#endif
+#ifdef CACHE_INVALIDATE
+ __asm__ __volatile__ (
+ "movel %0, %%d0\n\t"
+ "movec %%d0, %%CACR\n\t"
+ "nop\n\t"
+ : : "i" (CACHE_INVALIDATE) : "d0" );
+#endif
+}
+
+/*
+ * Some ColdFire parts implement separate instruction and data caches,
+ * on those we should just flush the appropriate cache. If we don't need
+ * to do any specific flushing then this will be optimized away.
+ */
+static inline void __flush_icache_all(void)
+{
+#ifdef CACHE_INVALIDATEI
+ __asm__ __volatile__ (
+ "movel %0, %%d0\n\t"
+ "movec %%d0, %%CACR\n\t"
+ "nop\n\t"
+ : : "i" (CACHE_INVALIDATEI) : "d0" );
+#endif
+}
+
+static inline void __flush_dcache_all(void)
+{
+#ifdef CACHE_PUSH
+ mcf_cache_push();
+#endif
+#ifdef CACHE_INVALIDATED
+ __asm__ __volatile__ (
+ "movel %0, %%d0\n\t"
+ "movec %%d0, %%CACR\n\t"
+ "nop\n\t"
+ : : "i" (CACHE_INVALIDATED) : "d0" );
+#else
+ /* Flush the wrtite buffer */
+ __asm__ __volatile__ ( "nop" );
+#endif
+}
+#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h
new file mode 100644
index 00000000000..2f88d867c71
--- /dev/null
+++ b/arch/m68k/include/asm/checksum.h
@@ -0,0 +1,149 @@
+#ifndef _M68K_CHECKSUM_H
+#define _M68K_CHECKSUM_H
+
+#include <linux/in6.h>
+
+#ifdef CONFIG_GENERIC_CSUM
+#include <asm-generic/checksum.h>
+#else
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+__wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+extern __wsum csum_partial_copy_from_user(const void __user *src,
+ void *dst,
+ int len, __wsum sum,
+ int *csum_err);
+
+extern __wsum csum_partial_copy_nocheck(const void *src,
+ void *dst, int len,
+ __wsum sum);
+
+/*
+ * This is a version of ip_fast_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+ unsigned int sum = 0;
+ unsigned long tmp;
+
+ __asm__ ("subqw #1,%2\n"
+ "1:\t"
+ "movel %1@+,%3\n\t"
+ "addxl %3,%0\n\t"
+ "dbra %2,1b\n\t"
+ "movel %0,%3\n\t"
+ "swap %3\n\t"
+ "addxw %3,%0\n\t"
+ "clrw %3\n\t"
+ "addxw %3,%0\n\t"
+ : "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
+ : "0" (sum), "1" (iph), "2" (ihl)
+ : "memory");
+ return (__force __sum16)~sum;
+}
+
+static inline __sum16 csum_fold(__wsum sum)
+{
+ unsigned int tmp = (__force u32)sum;
+
+ __asm__("swap %1\n\t"
+ "addw %1, %0\n\t"
+ "clrw %1\n\t"
+ "addxw %1, %0"
+ : "=&d" (sum), "=&d" (tmp)
+ : "0" (sum), "1" (tmp));
+
+ return (__force __sum16)~sum;
+}
+
+static inline __wsum
+csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+ unsigned short proto, __wsum sum)
+{
+ __asm__ ("addl %2,%0\n\t"
+ "addxl %3,%0\n\t"
+ "addxl %4,%0\n\t"
+ "clrl %1\n\t"
+ "addxl %1,%0"
+ : "=&d" (sum), "=d" (saddr)
+ : "g" (daddr), "1" (saddr), "d" (len + proto),
+ "0" (sum));
+ return sum;
+}
+
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16
+csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
+ unsigned short proto, __wsum sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+ return csum_fold (csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ __sum16
+csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
+ __u32 len, unsigned short proto, __wsum sum)
+{
+ register unsigned long tmp;
+ __asm__("addl %2@,%0\n\t"
+ "movel %2@(4),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %2@(8),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %2@(12),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@,%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(4),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(8),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(12),%1\n\t"
+ "addxl %1,%0\n\t"
+ "addxl %4,%0\n\t"
+ "clrl %1\n\t"
+ "addxl %1,%0"
+ : "=&d" (sum), "=&d" (tmp)
+ : "a" (saddr), "a" (daddr), "d" (len + proto),
+ "0" (sum));
+
+ return csum_fold(sum);
+}
+
+#endif /* CONFIG_GENERIC_CSUM */
+#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
new file mode 100644
index 00000000000..c94557b9144
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire.h
@@ -0,0 +1,49 @@
+/****************************************************************************/
+
+/*
+ * coldfire.h -- Motorola ColdFire CPU sepecific defines
+ *
+ * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef coldfire_h
+#define coldfire_h
+/****************************************************************************/
+
+
+/*
+ * Define master clock frequency. This is done at config time now.
+ * No point enumerating dozens of possible clock options here. And
+ * in any case new boards come along from time to time that have yet
+ * another different clocking frequency.
+ */
+#ifdef CONFIG_CLOCK_SET
+#define MCF_CLK CONFIG_CLOCK_FREQ
+#else
+#error "Don't know what your ColdFire CPU clock frequency is??"
+#endif
+
+/*
+ * Define the processor internal peripherals base address.
+ *
+ * The majority of ColdFire parts use an MBAR register to set
+ * the base address. Some have an IPSBAR register instead, and it
+ * has slightly different rules on its size and alignment. Some
+ * parts have fixed addresses and the internal peripherals cannot
+ * be relocated in the CPU address space.
+ *
+ * The value of MBAR or IPSBAR is config time selectable, we no
+ * longer hard define it here. No MBAR or IPSBAR will be defined if
+ * this part has a fixed peripheral address map.
+ */
+#ifdef CONFIG_MBAR
+#define MCF_MBAR CONFIG_MBAR
+#endif
+#ifdef CONFIG_IPSBAR
+#define MCF_IPSBAR CONFIG_IPSBAR
+#endif
+
+/****************************************************************************/
+#endif /* coldfire_h */
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
new file mode 100644
index 00000000000..a73998528d2
--- /dev/null
+++ b/arch/m68k/include/asm/commproc.h
@@ -0,0 +1,703 @@
+
+/*
+ * 68360 Communication Processor Module.
+ * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
+ * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
+ *
+ * This file contains structures and information for the communication
+ * processor channels. Some CPM control and status is available
+ * through the 68360 internal memory map. See include/asm/360_immap.h for details.
+ * This file is not a complete map of all of the 360 QUICC's capabilities
+ *
+ * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
+ * bytes of the DP RAM and relocates the I2C parameter area to the
+ * IDMA1 space. The remaining DP RAM is available for buffer descriptors
+ * or other use.
+ */
+#ifndef __CPM_360__
+#define __CPM_360__
+
+
+/* CPM Command register masks: */
+#define CPM_CR_RST ((ushort)0x8000)
+#define CPM_CR_OPCODE ((ushort)0x0f00)
+#define CPM_CR_CHAN ((ushort)0x00f0)
+#define CPM_CR_FLG ((ushort)0x0001)
+
+/* CPM Command set (opcodes): */
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
+#define CPM_CR_GCI_ABORT ((ushort)0x000a)
+#define CPM_CR_RESET_BCS ((ushort)0x000a)
+
+/* CPM Channel numbers. */
+#define CPM_CR_CH_SCC1 ((ushort)0x0000)
+#define CPM_CR_CH_SCC2 ((ushort)0x0004)
+#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
+#define CPM_CR_CH_TMR ((ushort)0x0005)
+#define CPM_CR_CH_SCC3 ((ushort)0x0008)
+#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
+#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
+#define CPM_CR_CH_SCC4 ((ushort)0x000c)
+#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
+#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
+
+
+#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
+
+#if 1 /* mleslie: I dinna think we have any such restrictions on
+ * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
+
+/* The dual ported RAM is multi-functional. Some areas can be (and are
+ * being) used for microcode. There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
+#define CPM_DATAONLY_BASE ((uint)0x0000)
+#define CPM_DATAONLY_SIZE ((uint)0x0800)
+#define CPM_DP_NOSPACE ((uint)0x7fffffff)
+
+#endif
+
+
+/* Export the base address of the communication processor registers
+ * and dual port ram. */
+/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
+extern QUICC *pquicc;
+uint m360_cpm_dpalloc(uint size);
+/* void *m360_cpm_hostalloc(uint size); */
+void m360_cpm_setbrg(uint brg, uint rate);
+
+#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
+/* Buffer descriptors used by many of the CPM protocols. */
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+#endif
+
+
+/* rx bd status/control bits */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
+
+#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
+#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
+
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
+
+#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
+#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
+
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
+
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
+
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
+
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
+
+/* tx bd status/control bits (as differ from rx bd) */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_UN ((ushort)0x0002) /* Underrun */
+
+
+
+
+/* Parameter RAM offsets. */
+
+
+
+/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
+ * In 2.0, we use a more structured C struct map of DPRAM, and so
+ * instead, we need only a parameter ram `slot' */
+
+#define PRSLOT_SCC1 0
+#define PRSLOT_SCC2 1
+#define PRSLOT_SCC3 2
+#define PRSLOT_SMC1 2
+#define PRSLOT_SCC4 3
+#define PRSLOT_SMC2 3
+
+
+/* #define PROFF_SCC1 ((uint)0x0000) */
+/* #define PROFF_SCC2 ((uint)0x0100) */
+/* #define PROFF_SCC3 ((uint)0x0200) */
+/* #define PROFF_SMC1 ((uint)0x0280) */
+/* #define PROFF_SCC4 ((uint)0x0300) */
+/* #define PROFF_SMC2 ((uint)0x0380) */
+
+
+/* Define enough so I can at least use the serial port as a UART.
+ * The MBX uses SMC1 as the host serial port.
+ */
+typedef struct smc_uart {
+ ushort smc_rbase; /* Rx Buffer descriptor base address */
+ ushort smc_tbase; /* Tx Buffer descriptor base address */
+ u_char smc_rfcr; /* Rx function code */
+ u_char smc_tfcr; /* Tx function code */
+ ushort smc_mrblr; /* Max receive buffer length */
+ uint smc_rstate; /* Internal */
+ uint smc_idp; /* Internal */
+ ushort smc_rbptr; /* Internal */
+ ushort smc_ibc; /* Internal */
+ uint smc_rxtmp; /* Internal */
+ uint smc_tstate; /* Internal */
+ uint smc_tdp; /* Internal */
+ ushort smc_tbptr; /* Internal */
+ ushort smc_tbc; /* Internal */
+ uint smc_txtmp; /* Internal */
+ ushort smc_maxidl; /* Maximum idle characters */
+ ushort smc_tmpidl; /* Temporary idle counter */
+ ushort smc_brklen; /* Last received break length */
+ ushort smc_brkec; /* rcv'd break condition counter */
+ ushort smc_brkcr; /* xmt break count register */
+ ushort smc_rmask; /* Temporary bit mask */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define SMCMR_REN ((ushort)0x0001)
+#define SMCMR_TEN ((ushort)0x0002)
+#define SMCMR_DM ((ushort)0x000c)
+#define SMCMR_SM_GCI ((ushort)0x0000)
+#define SMCMR_SM_UART ((ushort)0x0020)
+#define SMCMR_SM_TRANS ((ushort)0x0030)
+#define SMCMR_SM_MASK ((ushort)0x0030)
+#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
+#define SMCMR_REVD SMCMR_PM_EVEN
+#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
+#define SMCMR_BS SMCMR_PEN
+#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
+#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer. It is half duplex, in that
+ * it can only receive or transmit. The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+ ushort scent_rbase;
+ ushort scent_tbase;
+ u_char scent_cfcr;
+ u_char scent_smask;
+ ushort scent_mrblr;
+ uint scent_rstate;
+ uint scent_r_ptr;
+ ushort scent_rbptr;
+ ushort scent_r_cnt;
+ uint scent_rtemp;
+ uint scent_tstate;
+ uint scent_t_ptr;
+ ushort scent_tbptr;
+ ushort scent_t_cnt;
+ uint scent_ttemp;
+ ushort scent_max_sl;
+ ushort scent_sl_cnt;
+ ushort scent_character1;
+ ushort scent_character2;
+ ushort scent_character3;
+ ushort scent_character4;
+ ushort scent_character5;
+ ushort scent_character6;
+ ushort scent_character7;
+ ushort scent_character8;
+ ushort scent_rccm;
+ ushort scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F ((u_char)0x08)
+#define SMC_CENT_PE ((u_char)0x04)
+#define SMC_CENT_S ((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
+#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
+#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
+#define SMCM_BSY ((unsigned char)0x04)
+#define SMCM_TX ((unsigned char)0x02)
+#define SMCM_RX ((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST ((uint)0x00020000)
+#define CPM_BRG_EN ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
+#define CPM_BRG_ATB ((uint)0x00002000)
+#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
+#define CPM_BRG_DIV16 ((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP ((uint)0x00040000)
+#define SCC_GSMRH_GDE ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
+#define SCC_GSMRH_REVD ((uint)0x00002000)
+#define SCC_GSMRH_TRX ((uint)0x00001000)
+#define SCC_GSMRH_TTX ((uint)0x00000800)
+#define SCC_GSMRH_CDP ((uint)0x00000400)
+#define SCC_GSMRH_CTSP ((uint)0x00000200)
+#define SCC_GSMRH_CDS ((uint)0x00000100)
+#define SCC_GSMRH_CTSS ((uint)0x00000080)
+#define SCC_GSMRH_TFL ((uint)0x00000040)
+#define SCC_GSMRH_RFW ((uint)0x00000020)
+#define SCC_GSMRH_TXSY ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
+#define SCC_GSMRH_RTSM ((uint)0x00000002)
+#define SCC_GSMRH_RSYN ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
+#define SCC_GSMRL_TCI ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
+#define SCC_GSMRL_RINV ((uint)0x02000000)
+#define SCC_GSMRL_TINV ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
+#define SCC_GSMRL_TEND ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
+#define SCC_GSMRL_ENR ((uint)0x00000020)
+#define SCC_GSMRL_ENT ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
+
+#define SCC_TODR_TOD ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE ((unsigned char)0x10)
+#define SCCM_BSY ((unsigned char)0x04)
+#define SCCM_TX ((unsigned char)0x02)
+#define SCCM_RX ((unsigned char)0x01)
+
+typedef struct scc_param {
+ ushort scc_rbase; /* Rx Buffer descriptor base address */
+ ushort scc_tbase; /* Tx Buffer descriptor base address */
+ u_char scc_rfcr; /* Rx function code */
+ u_char scc_tfcr; /* Tx function code */
+ ushort scc_mrblr; /* Max receive buffer length */
+ uint scc_rstate; /* Internal */
+ uint scc_idp; /* Internal */
+ ushort scc_rbptr; /* Internal */
+ ushort scc_ibc; /* Internal */
+ uint scc_rxtmp; /* Internal */
+ uint scc_tstate; /* Internal */
+ uint scc_tdp; /* Internal */
+ ushort scc_tbptr; /* Internal */
+ ushort scc_tbc; /* Internal */
+ uint scc_txtmp; /* Internal */
+ uint scc_rcrc; /* Internal */
+ uint scc_tcrc; /* Internal */
+} sccp_t;
+
+
+/* Function code bits.
+ */
+#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
+#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+ sccp_t sen_genscc;
+ uint sen_cpres; /* Preset CRC */
+ uint sen_cmask; /* Constant mask for CRC */
+ uint sen_crcec; /* CRC Error counter */
+ uint sen_alec; /* alignment error counter */
+ uint sen_disfc; /* discard frame counter */
+ ushort sen_pads; /* Tx short frame pad character */
+ ushort sen_retlim; /* Retry limit threshold */
+ ushort sen_retcnt; /* Retry limit counter */
+ ushort sen_maxflr; /* maximum frame length register */
+ ushort sen_minflr; /* minimum frame length register */
+ ushort sen_maxd1; /* maximum DMA1 length */
+ ushort sen_maxd2; /* maximum DMA2 length */
+ ushort sen_maxd; /* Rx max DMA */
+ ushort sen_dmacnt; /* Rx DMA counter */
+ ushort sen_maxb; /* Max BD byte count */
+ ushort sen_gaddr1; /* Group address filter */
+ ushort sen_gaddr2;
+ ushort sen_gaddr3;
+ ushort sen_gaddr4;
+ uint sen_tbuf0data0; /* Save area 0 - current frame */
+ uint sen_tbuf0data1; /* Save area 1 - current frame */
+ uint sen_tbuf0rba; /* Internal */
+ uint sen_tbuf0crc; /* Internal */
+ ushort sen_tbuf0bcnt; /* Internal */
+ ushort sen_paddrh; /* physical address (MSB) */
+ ushort sen_paddrm;
+ ushort sen_paddrl; /* physical address (LSB) */
+ ushort sen_pper; /* persistence */
+ ushort sen_rfbdptr; /* Rx first BD pointer */
+ ushort sen_tfbdptr; /* Tx first BD pointer */
+ ushort sen_tlbdptr; /* Tx last BD pointer */
+ uint sen_tbuf1data0; /* Save area 0 - current frame */
+ uint sen_tbuf1data1; /* Save area 1 - current frame */
+ uint sen_tbuf1rba; /* Internal */
+ uint sen_tbuf1crc; /* Internal */
+ ushort sen_tbuf1bcnt; /* Internal */
+ ushort sen_txlen; /* Tx Frame length counter */
+ ushort sen_iaddr1; /* Individual address filter */
+ ushort sen_iaddr2;
+ ushort sen_iaddr3;
+ ushort sen_iaddr4;
+ ushort sen_boffcnt; /* Backoff counter */
+
+ /* NOTE: Some versions of the manual have the following items
+ * incorrectly documented. Below is the proper order.
+ */
+ ushort sen_taddrh; /* temp address (MSB) */
+ ushort sen_taddrm;
+ ushort sen_taddrl; /* temp address (LSB) */
+} scc_enet_t;
+
+
+
+#if defined (CONFIG_UCQUICC)
+/* uCquicc has the following signals connected to Ethernet:
+ * 68360 - lxt905
+ * PA0/RXD1 - rxd
+ * PA1/TXD1 - txd
+ * PA8/CLK1 - tclk
+ * PA9/CLK2 - rclk
+ * PC0/!RTS1 - t_en
+ * PC1/!CTS1 - col
+ * PC5/!CD1 - cd
+ */
+#define PA_ENET_RXD PA_RXD1
+#define PA_ENET_TXD PA_TXD1
+#define PA_ENET_TCLK PA_CLK1
+#define PA_ENET_RCLK PA_CLK2
+#define PC_ENET_TENA PC_RTS1
+#define PC_ENET_CLSN PC_CTS1
+#define PC_ENET_RENA PC_CD1
+
+/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
+ * SCC1.
+ */
+#define SICR_ENET_MASK ((uint)0x000000ff)
+#define SICR_ENET_CLKRT ((uint)0x0000002c)
+
+#endif /* config_ucquicc */
+
+
+#ifdef MBX
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
+ * to the MBX860 board. Any two of the four available clocks could be
+ * used, and the MPC860 cookbook manual has an example using different
+ * clock pins.
+ */
+#define PA_ENET_RXD ((ushort)0x0001)
+#define PA_ENET_TXD ((ushort)0x0002)
+#define PA_ENET_TCLK ((ushort)0x0200)
+#define PA_ENET_RCLK ((ushort)0x0800)
+#define PC_ENET_TENA ((ushort)0x0001)
+#define PC_ENET_CLSN ((ushort)0x0010)
+#define PC_ENET_RENA ((ushort)0x0020)
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x000000ff)
+#define SICR_ENET_CLKRT ((uint)0x0000003d)
+#endif
+
+#ifdef CONFIG_RPXLITE
+/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
+ * this may be unique to the RPX-Lite configuration.
+ * Note TENA is on Port B.
+ */
+#define PA_ENET_RXD ((ushort)0x0004)
+#define PA_ENET_TXD ((ushort)0x0008)
+#define PA_ENET_TCLK ((ushort)0x0200)
+#define PA_ENET_RCLK ((ushort)0x0800)
+#define PB_ENET_TENA ((uint)0x00002000)
+#define PC_ENET_CLSN ((ushort)0x0040)
+#define PC_ENET_RENA ((ushort)0x0080)
+
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003d00)
+#endif
+
+#ifdef CONFIG_BSEIP
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.
+ * This is unique to the BSE ip-Engine board.
+ */
+#define PA_ENET_RXD ((ushort)0x0004)
+#define PA_ENET_TXD ((ushort)0x0008)
+#define PA_ENET_TCLK ((ushort)0x0100)
+#define PA_ENET_RCLK ((ushort)0x0200)
+#define PB_ENET_TENA ((uint)0x00002000)
+#define PC_ENET_CLSN ((ushort)0x0040)
+#define PC_ENET_RENA ((ushort)0x0080)
+
+/* BSE uses port B and C bits for PHY control also.
+*/
+#define PB_BSE_POWERUP ((uint)0x00000004)
+#define PB_BSE_FDXDIS ((uint)0x00008000)
+#define PC_BSE_LOOPBACK ((ushort)0x0800)
+
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002c00)
+#endif
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
+#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* SCC Mode Register (PMSR) as used by Ethernet.
+*/
+#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
+#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
+#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
+#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
+#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
+#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
+#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
+#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
+#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
+#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
+#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
+#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
+#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+ sccp_t scc_genscc;
+ uint scc_res1; /* Reserved */
+ uint scc_res2; /* Reserved */
+ ushort scc_maxidl; /* Maximum idle chars */
+ ushort scc_idlc; /* temp idle counter */
+ ushort scc_brkcr; /* Break count register */
+ ushort scc_parec; /* receive parity error counter */
+ ushort scc_frmec; /* receive framing error counter */
+ ushort scc_nosec; /* receive noise counter */
+ ushort scc_brkec; /* receive break condition counter */
+ ushort scc_brkln; /* last received break length */
+ ushort scc_uaddr1; /* UART address character 1 */
+ ushort scc_uaddr2; /* UART address character 2 */
+ ushort scc_rtemp; /* Temp storage */
+ ushort scc_toseq; /* Transmit out of sequence char */
+ ushort scc_char1; /* control character 1 */
+ ushort scc_char2; /* control character 2 */
+ ushort scc_char3; /* control character 3 */
+ ushort scc_char4; /* control character 4 */
+ ushort scc_char5; /* control character 5 */
+ ushort scc_char6; /* control character 6 */
+ ushort scc_char7; /* control character 7 */
+ ushort scc_char8; /* control character 8 */
+ ushort scc_rccm; /* receive control character mask */
+ ushort scc_rccr; /* receive control character register */
+ ushort scc_rlbc; /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR ((ushort)0x1000)
+#define UART_SCCM_GLT ((ushort)0x0800)
+#define UART_SCCM_AB ((ushort)0x0200)
+#define UART_SCCM_IDL ((ushort)0x0100)
+#define UART_SCCM_GRA ((ushort)0x0080)
+#define UART_SCCM_BRKE ((ushort)0x0040)
+#define UART_SCCM_BRKS ((ushort)0x0020)
+#define UART_SCCM_CCR ((ushort)0x0008)
+#define UART_SCCM_BSY ((ushort)0x0004)
+#define UART_SCCM_TX ((ushort)0x0002)
+#define UART_SCCM_RX ((ushort)0x0001)
+
+/* The SCC PMSR when used as a UART.
+*/
+#define SCU_PMSR_FLC ((ushort)0x8000)
+#define SCU_PMSR_SL ((ushort)0x4000)
+#define SCU_PMSR_CL ((ushort)0x3000)
+#define SCU_PMSR_UM ((ushort)0x0c00)
+#define SCU_PMSR_FRZ ((ushort)0x0200)
+#define SCU_PMSR_RZS ((ushort)0x0100)
+#define SCU_PMSR_SYN ((ushort)0x0080)
+#define SCU_PMSR_DRT ((ushort)0x0040)
+#define SCU_PMSR_PEN ((ushort)0x0010)
+#define SCU_PMSR_RPM ((ushort)0x000c)
+#define SCU_PMSR_REVP ((ushort)0x0008)
+#define SCU_PMSR_TPM ((ushort)0x0003)
+#define SCU_PMSR_TEVP ((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+ sccp_t st_genscc;
+ uint st_cpres; /* Preset CRC */
+ uint st_cmask; /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST ((ushort)0x0800)
+
+
+
+/* CPM interrupts. There are nearly 32 interrupts generated by CPM
+ * channels or devices. All of these are presented to the PPC core
+ * as a single interrupt. The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler. We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+/* #define CPMVEC_NR 32 */
+/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
+/* #define CPMVEC_SCC1 ((ushort)0x1e) */
+/* #define CPMVEC_SCC2 ((ushort)0x1d) */
+/* #define CPMVEC_SCC3 ((ushort)0x1c) */
+/* #define CPMVEC_SCC4 ((ushort)0x1b) */
+/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
+/* #define CPMVEC_TIMER1 ((ushort)0x19) */
+/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
+/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
+/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
+/* #define CPMVEC_IDMA1 ((ushort)0x15) */
+/* #define CPMVEC_IDMA2 ((ushort)0x14) */
+/* #define CPMVEC_TIMER2 ((ushort)0x12) */
+/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
+/* #define CPMVEC_I2C ((ushort)0x10) */
+/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
+/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
+/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
+/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
+/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
+/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
+/* #define CPMVEC_TIMER4 ((ushort)0x07) */
+/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
+/* #define CPMVEC_SPI ((ushort)0x05) */
+/* #define CPMVEC_SMC1 ((ushort)0x04) */
+/* #define CPMVEC_SMC2 ((ushort)0x03) */
+/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
+/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
+/* #define CPMVEC_ERROR ((ushort)0x00) */
+
+extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
+#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
+#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
+#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
+#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
+#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
+#define CICR_IEN ((uint)0x00000080) /* Int. enable */
+#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
+#endif /* __CPM_360__ */
diff --git a/arch/m68k/include/asm/contregs.h b/arch/m68k/include/asm/contregs.h
new file mode 100644
index 00000000000..d1ea750bddf
--- /dev/null
+++ b/arch/m68k/include/asm/contregs.h
@@ -0,0 +1,53 @@
+#ifndef _M68K_CONTREGS_H
+#define _M68K_CONTREGS_H
+
+/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
+ * space. These are for the mmu's context register, etc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* 3=sun3
+ 4=sun4 (as in sun4 sysmaint student book)
+ c=sun4c (according to davem) */
+
+#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
+#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
+#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
+#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
+#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
+#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
+#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
+#define AC_SYNC_ERR 0x60000000 /* c fault type */
+#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
+#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
+#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
+#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
+#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
+#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
+#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
+#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
+#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
+
+/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
+#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
+#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
+#define AC_M_CXR 0x0200 /* shv Context Register */
+#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
+#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
+#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
+#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
+#define AC_M_RESET 0x0700 /* hv Reset Reg */
+#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
+#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
+#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
+#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
+#define AC_M_ITR 0x1300 /* hv Index Tag Register */
+#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
+#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
+#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
+#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
+#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
+#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
+
+#endif /* _M68K_CONTREGS_H */
diff --git a/arch/m68k/include/asm/cputime.h b/arch/m68k/include/asm/cputime.h
new file mode 100644
index 00000000000..c79c5e89230
--- /dev/null
+++ b/arch/m68k/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __M68K_CPUTIME_H
+#define __M68K_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __M68K_CPUTIME_H */
diff --git a/arch/m68k/include/asm/current.h b/arch/m68k/include/asm/current.h
new file mode 100644
index 00000000000..91fcc5358cf
--- /dev/null
+++ b/arch/m68k/include/asm/current.h
@@ -0,0 +1,28 @@
+#ifndef _M68K_CURRENT_H
+#define _M68K_CURRENT_H
+
+#ifdef CONFIG_MMU
+
+register struct task_struct *current __asm__("%a2");
+
+#else
+
+/*
+ * Rather than dedicate a register (as the m68k source does), we
+ * just keep a global, we should probably just change it all to be
+ * current and lose _current_task.
+ */
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct *get_current(void)
+{
+ return(current_thread_info()->task);
+}
+
+#define current get_current()
+
+#endif /* CONFNIG_MMU */
+
+#endif /* !(_M68K_CURRENT_H) */
diff --git a/arch/m68k/include/asm/dbg.h b/arch/m68k/include/asm/dbg.h
new file mode 100644
index 00000000000..27af3270f67
--- /dev/null
+++ b/arch/m68k/include/asm/dbg.h
@@ -0,0 +1,6 @@
+#define DEBUG 1
+#ifdef CONFIG_COLDFIRE
+#define BREAK asm volatile ("halt")
+#else
+#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
+#endif
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h
new file mode 100644
index 00000000000..9c09becfd4c
--- /dev/null
+++ b/arch/m68k/include/asm/delay.h
@@ -0,0 +1,96 @@
+#ifndef _M68K_DELAY_H
+#define _M68K_DELAY_H
+
+#include <asm/param.h>
+
+/*
+ * Copyright (C) 1994 Hamish Macdonald
+ * Copyright (C) 2004 Greg Ungerer <gerg@uclinux.com>
+ *
+ * Delay routines, using a pre-computed "loops_per_jiffy" value.
+ */
+
+#if defined(CONFIG_COLDFIRE)
+/*
+ * The ColdFire runs the delay loop at significantly different speeds
+ * depending upon long word alignment or not. We'll pad it to
+ * long word alignment which is the faster version.
+ * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
+ * than using a NOP (0x4e71) instruction because it executes in one
+ * cycle not three and doesn't allow for an arbitrary delay waiting
+ * for bus cycles to finish. Also fp/a6 isn't likely to cause a
+ * stall waiting for the register to become valid if such is added
+ * to the coldfire at some stage.
+ */
+#define DELAY_ALIGN ".balignw 4, 0x4a8e\n\t"
+#else
+/*
+ * No instruction alignment required for other m68k types.
+ */
+#define DELAY_ALIGN
+#endif
+
+static inline void __delay(unsigned long loops)
+{
+ __asm__ __volatile__ (
+ DELAY_ALIGN
+ "1: subql #1,%0\n\t"
+ "jcc 1b"
+ : "=d" (loops)
+ : "0" (loops));
+}
+
+extern void __bad_udelay(void);
+
+
+#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
+/*
+ * The simpler m68k and ColdFire processors do not have a 32*32->64
+ * multiply instruction. So we need to handle them a little differently.
+ * We use a bit of shifting and a single 32*32->32 multiply to get close.
+ * This is a macro so that the const version can factor out the first
+ * multiply and shift.
+ */
+#define HZSCALE (268435456 / (1000000 / HZ))
+
+#define __const_udelay(u) \
+ __delay(((((u) * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6)
+
+#else
+
+static inline void __xdelay(unsigned long xloops)
+{
+ unsigned long tmp;
+
+ __asm__ ("mulul %2,%0:%1"
+ : "=d" (xloops), "=d" (tmp)
+ : "d" (xloops), "1" (loops_per_jiffy));
+ __delay(xloops * HZ);
+}
+
+/*
+ * The definition of __const_udelay is specifically made a macro so that
+ * the const factor (4295 = 2**32 / 1000000) can be optimized out when
+ * the delay is a const.
+ */
+#define __const_udelay(n) (__xdelay((n) * 4295))
+
+#endif
+
+static inline void __udelay(unsigned long usecs)
+{
+ __const_udelay(usecs);
+}
+
+/*
+ * Use only for very small delays ( < 1 msec). Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays. This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+#define udelay(n) (__builtin_constant_p(n) ? \
+ ((n) > 20000 ? __bad_udelay() : __const_udelay(n)) : __udelay(n))
+
+
+#endif /* defined(_M68K_DELAY_H) */
diff --git a/arch/m68k/include/asm/device.h b/arch/m68k/include/asm/device.h
new file mode 100644
index 00000000000..d8f9872b0e2
--- /dev/null
+++ b/arch/m68k/include/asm/device.h
@@ -0,0 +1,7 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h
new file mode 100644
index 00000000000..444ea8a09e9
--- /dev/null
+++ b/arch/m68k/include/asm/div64.h
@@ -0,0 +1,34 @@
+#ifndef _M68K_DIV64_H
+#define _M68K_DIV64_H
+
+#ifdef CONFIG_CPU_HAS_NO_MULDIV64
+#include <asm-generic/div64.h>
+#else
+
+#include <linux/types.h>
+
+/* n = n / base; return rem; */
+
+#define do_div(n, base) ({ \
+ union { \
+ unsigned long n32[2]; \
+ unsigned long long n64; \
+ } __n; \
+ unsigned long __rem, __upper; \
+ \
+ __n.n64 = (n); \
+ if ((__upper = __n.n32[0])) { \
+ asm ("divul.l %2,%1:%0" \
+ : "=d" (__n.n32[0]), "=d" (__upper) \
+ : "d" (base), "0" (__n.n32[0])); \
+ } \
+ asm ("divu.l %2,%1:%0" \
+ : "=d" (__n.n32[1]), "=d" (__rem) \
+ : "d" (base), "1" (__upper), "0" (__n.n32[1])); \
+ (n) = __n.n64; \
+ __rem; \
+})
+
+#endif /* CONFIG_CPU_HAS_NO_MULDIV64 */
+
+#endif /* _M68K_DIV64_H */
diff --git a/arch/m68k/include/asm/dma-mapping.h b/arch/m68k/include/asm/dma-mapping.h
new file mode 100644
index 00000000000..17f7a45948e
--- /dev/null
+++ b/arch/m68k/include/asm/dma-mapping.h
@@ -0,0 +1,102 @@
+#ifndef _M68K_DMA_MAPPING_H
+#define _M68K_DMA_MAPPING_H
+
+#include <asm/cache.h>
+
+struct scatterlist;
+
+#ifndef CONFIG_MMU_SUN3
+static inline int dma_supported(struct device *dev, u64 mask)
+{
+ return 1;
+}
+
+static inline int dma_set_mask(struct device *dev, u64 mask)
+{
+ return 0;
+}
+
+extern void *dma_alloc_coherent(struct device *, size_t,
+ dma_addr_t *, gfp_t);
+extern void dma_free_coherent(struct device *, size_t,
+ void *, dma_addr_t);
+
+static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
+ dma_addr_t *handle, gfp_t flag)
+{
+ return dma_alloc_coherent(dev, size, handle, flag);
+}
+static inline void dma_free_noncoherent(struct device *dev, size_t size,
+ void *addr, dma_addr_t handle)
+{
+ dma_free_coherent(dev, size, addr, handle);
+}
+static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+ enum dma_data_direction dir)
+{
+ /* we use coherent allocation, so not much to do here. */
+}
+
+extern dma_addr_t dma_map_single(struct device *, void *, size_t,
+ enum dma_data_direction);
+static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
+ size_t size, enum dma_data_direction dir)
+{
+}
+
+extern dma_addr_t dma_map_page(struct device *, struct page *,
+ unsigned long, size_t size,
+ enum dma_data_direction);
+static inline void dma_unmap_page(struct device *dev, dma_addr_t address,
+ size_t size, enum dma_data_direction dir)
+{
+}
+
+extern int dma_map_sg(struct device *, struct scatterlist *, int,
+ enum dma_data_direction);
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nhwentries, enum dma_data_direction dir)
+{
+}
+
+extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
+ enum dma_data_direction);
+extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
+ enum dma_data_direction);
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+ dma_addr_t dma_handle, unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ /* just sync everything for now */
+ dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
+}
+
+static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir)
+{
+}
+
+static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction dir)
+{
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+ dma_addr_t dma_handle, unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ /* just sync everything for now */
+ dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
+{
+ return 0;
+}
+
+#else
+#include <asm-generic/dma-mapping-broken.h>
+#endif
+
+#endif /* _M68K_DMA_MAPPING_H */
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
new file mode 100644
index 00000000000..6fbdfe89510
--- /dev/null
+++ b/arch/m68k/include/asm/dma.h
@@ -0,0 +1,491 @@
+#ifndef _M68K_DMA_H
+#define _M68K_DMA_H 1
+
+#ifdef CONFIG_COLDFIRE
+/*
+ * ColdFire DMA Model:
+ * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
+ * address mode emits a source address, and expects that the device will either
+ * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
+ * the device will place data on the correct byte(s) of the data bus, as the
+ * memory transactions are always 32 bits. This implies that only 32 bit
+ * devices will find single mode transfers useful. Dual address DMA mode
+ * performs two cycles: source read and destination write. ColdFire will
+ * align the data so that the device will always get the correct bytes, thus
+ * is useful for 8 and 16 bit devices. This is the mode that is supported
+ * below.
+ *
+ * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
+ * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
+ *
+ * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
+ * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
+ *
+ * APR/18/2002 : added proper support for MCF5272 DMA controller.
+ * Arthur Shipkowski (art@videon-central.com)
+ */
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfdma.h>
+
+/*
+ * Set number of channels of DMA on ColdFire for different implementations.
+ */
+#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
+ defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
+#define MAX_M68K_DMA_CHANNELS 4
+#elif defined(CONFIG_M5272)
+#define MAX_M68K_DMA_CHANNELS 1
+#elif defined(CONFIG_M532x)
+#define MAX_M68K_DMA_CHANNELS 0
+#else
+#define MAX_M68K_DMA_CHANNELS 2
+#endif
+
+extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
+extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
+
+#if !defined(CONFIG_M5272)
+#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
+#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
+#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
+#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
+
+/* I/O to memory, 8 bits, mode */
+#define DMA_MODE_READ 0
+/* memory to I/O, 8 bits, mode */
+#define DMA_MODE_WRITE 1
+/* I/O to memory, 16 bits, mode */
+#define DMA_MODE_READ_WORD 2
+/* memory to I/O, 16 bits, mode */
+#define DMA_MODE_WRITE_WORD 3
+/* I/O to memory, 32 bits, mode */
+#define DMA_MODE_READ_LONG 4
+/* memory to I/O, 32 bits, mode */
+#define DMA_MODE_WRITE_LONG 5
+/* I/O to memory, 8 bits, single-address-mode */
+#define DMA_MODE_READ_SINGLE 8
+/* memory to I/O, 8 bits, single-address-mode */
+#define DMA_MODE_WRITE_SINGLE 9
+/* I/O to memory, 16 bits, single-address-mode */
+#define DMA_MODE_READ_WORD_SINGLE 10
+/* memory to I/O, 16 bits, single-address-mode */
+#define DMA_MODE_WRITE_WORD_SINGLE 11
+/* I/O to memory, 32 bits, single-address-mode */
+#define DMA_MODE_READ_LONG_SINGLE 12
+/* memory to I/O, 32 bits, single-address-mode */
+#define DMA_MODE_WRITE_LONG_SINGLE 13
+
+#else /* CONFIG_M5272 is defined */
+
+/* Source static-address mode */
+#define DMA_MODE_SRC_SA_BIT 0x01
+/* Two bits to select between all four modes */
+#define DMA_MODE_SSIZE_MASK 0x06
+/* Offset to shift bits in */
+#define DMA_MODE_SSIZE_OFF 0x01
+/* Destination static-address mode */
+#define DMA_MODE_DES_SA_BIT 0x10
+/* Two bits to select between all four modes */
+#define DMA_MODE_DSIZE_MASK 0x60
+/* Offset to shift bits in */
+#define DMA_MODE_DSIZE_OFF 0x05
+/* Size modifiers */
+#define DMA_MODE_SIZE_LONG 0x00
+#define DMA_MODE_SIZE_BYTE 0x01
+#define DMA_MODE_SIZE_WORD 0x02
+#define DMA_MODE_SIZE_LINE 0x03
+
+/*
+ * Aliases to help speed quick ports; these may be suboptimal, however. They
+ * do not include the SINGLE mode modifiers since the MCF5272 does not have a
+ * mode where the device is in control of its addressing.
+ */
+
+/* I/O to memory, 8 bits, mode */
+#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 8 bits, mode */
+#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+/* I/O to memory, 16 bits, mode */
+#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 16 bits, mode */
+#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+/* I/O to memory, 32 bits, mode */
+#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 32 bits, mode */
+#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+
+#endif /* !defined(CONFIG_M5272) */
+
+#if !defined(CONFIG_M5272)
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("enable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+ volatile unsigned char *dmapb;
+
+#ifdef DMA_DEBUG
+ printk("disable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmapb = (unsigned char *) dma_base_addr[dmanr];
+
+ /* Turn off external requests, and stop any DMA in progress */
+ dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
+ dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
+}
+
+/*
+ * Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ *
+ * This is a NOP for ColdFire. Provide a stub for compatibility.
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+
+ volatile unsigned char *dmabp;
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
+#endif
+
+ dmabp = (unsigned char *) dma_base_addr[dmanr];
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+
+ /* Clear config errors */
+ dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
+
+ /* Set command register */
+ dmawp[MCFDMA_DCR] =
+ MCFDMA_DCR_INT | /* Enable completion irq */
+ MCFDMA_DCR_CS | /* Force one xfer per request */
+ MCFDMA_DCR_AA | /* Enable auto alignment */
+ /* single-address-mode */
+ ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
+ /* sets s_rw (-> r/w) high if Memory to I/0 */
+ ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
+ /* Memory to I/O or I/O to Memory */
+ ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
+ /* 32 bit, 16 bit or 8 bit transfers */
+ ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
+ ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
+ MCFDMA_DCR_SSIZE_BYTE)) |
+ ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
+ ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
+ MCFDMA_DCR_DSIZE_BYTE));
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
+ dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
+ (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
+#endif
+}
+
+/* Set transfer address for specific DMA channel */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+ volatile unsigned short *dmawp;
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Determine which address registers are used for memory/device accesses */
+ if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
+ /* Source incrementing, must be memory */
+ dmalp[MCFDMA_SAR] = a;
+ /* Set dest address, must be device */
+ dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
+ } else {
+ /* Destination incrementing, must be memory */
+ dmalp[MCFDMA_DAR] = a;
+ /* Set source address, must be device */
+ dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
+ }
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
+ __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
+ (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
+ (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
+#endif
+}
+
+/*
+ * Specific for Coldfire - sets device address.
+ * Should be called after the mode set call, and before set DMA address.
+ */
+static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
+{
+#ifdef DMA_DEBUG
+ printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dma_device_address[dmanr] = a;
+}
+
+/*
+ * NOTE 2: "count" represents _bytes_.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmawp[MCFDMA_BCR] = (unsigned short)count;
+}
+
+/*
+ * Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+ unsigned short count;
+
+#ifdef DMA_DEBUG
+ printk("get_dma_residue(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ count = dmawp[MCFDMA_BCR];
+ return((int) count);
+}
+#else /* CONFIG_M5272 is defined */
+
+/*
+ * The MCF5272 DMA controller is very different than the controller defined above
+ * in terms of register mapping. For instance, with the exception of the 16-bit
+ * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
+ *
+ * The big difference, however, is the lack of device-requested DMA. All modes
+ * are dual address transfer, and there is no 'device' setup or direction bit.
+ * You can DMA between a device and memory, between memory and memory, or even between
+ * two devices directly, with any combination of incrementing and non-incrementing
+ * addresses you choose. This puts a crimp in distinguishing between the 'device
+ * address' set up by set_dma_device_addr.
+ *
+ * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
+ * which will act exactly as above in -- it will look to see if the source is set to
+ * autoincrement, and if so it will make the source use the set_dma_addr value and the
+ * destination the set_dma_device_addr value. Otherwise the source will be set to the
+ * set_dma_device_addr value and the destination will get the set_dma_addr value.
+ *
+ * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
+ * and make it explicit. Depending on what you're doing, one of these two should work
+ * for you, but don't mix them in the same transfer setup.
+ */
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("enable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("disable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Turn off external requests, and stop any DMA in progress */
+ dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
+}
+
+/*
+ * Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ *
+ * This is a NOP for ColdFire. Provide a stub for compatibility.
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+
+ volatile unsigned int *dmalp;
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
+#endif
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+
+ /* Clear config errors */
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
+
+ /* Set command register */
+ dmalp[MCFDMA_DMR] =
+ MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
+ MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
+ MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
+ /* source static-address-mode */
+ ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
+ /* dest static-address-mode */
+ ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
+ /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
+ (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
+ (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
+
+ dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
+ dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
+ (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
+#endif
+}
+
+/* Set transfer address for specific DMA channel */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Determine which address registers are used for memory/device accesses */
+ if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
+ /* Source incrementing, must be memory */
+ dmalp[MCFDMA_DSAR] = a;
+ /* Set dest address, must be device */
+ dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
+ } else {
+ /* Destination incrementing, must be memory */
+ dmalp[MCFDMA_DDAR] = a;
+ /* Set source address, must be device */
+ dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
+ }
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
+ __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
+ (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
+ (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
+#endif
+}
+
+/*
+ * Specific for Coldfire - sets device address.
+ * Should be called after the mode set call, and before set DMA address.
+ */
+static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
+{
+#ifdef DMA_DEBUG
+ printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dma_device_address[dmanr] = a;
+}
+
+/*
+ * NOTE 2: "count" represents _bytes_.
+ *
+ * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmalp[MCFDMA_DBCR] = count;
+}
+
+/*
+ * Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+ unsigned int count;
+
+#ifdef DMA_DEBUG
+ printk("get_dma_residue(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ count = dmalp[MCFDMA_DBCR];
+ return(count);
+}
+
+#endif /* !defined(CONFIG_M5272) */
+#endif /* CONFIG_COLDFIRE */
+
+/* it's useless on the m68k, but unfortunately needed by the new
+ bootmem allocator (but this should do it for this) */
+#define MAX_DMA_ADDRESS PAGE_OFFSET
+
+#define MAX_DMA_CHANNELS 8
+
+extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr); /* release it again */
+
+#define isa_dma_bridge_buggy (0)
+
+#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/dsp56k.h b/arch/m68k/include/asm/dsp56k.h
new file mode 100644
index 00000000000..2d8c0c9f794
--- /dev/null
+++ b/arch/m68k/include/asm/dsp56k.h
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-m68k/dsp56k.h - defines and declarations for
+ * DSP56k device driver
+ *
+ * Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+
+/* Used for uploading DSP binary code */
+struct dsp56k_upload {
+ int len;
+ char __user *bin;
+};
+
+/* For the DSP host flags */
+struct dsp56k_host_flags {
+ int dir; /* Bit field. 1 = write output bit, 0 = do nothing.
+ * 0x0000 means reading only, 0x0011 means
+ * writing the bits stored in `out' on HF0 and HF1.
+ * Note that HF2 and HF3 can only be read.
+ */
+ int out; /* Bit field like above. */
+ int status; /* Host register's current state is returned */
+};
+
+/* ioctl command codes */
+#define DSP56K_UPLOAD 1 /* Upload DSP binary program */
+#define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */
+#define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */
+#define DSP56K_HOST_FLAGS 4 /* Host flag registers */
+#define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */
diff --git a/arch/m68k/include/asm/dvma.h b/arch/m68k/include/asm/dvma.h
new file mode 100644
index 00000000000..890bbf7e775
--- /dev/null
+++ b/arch/m68k/include/asm/dvma.h
@@ -0,0 +1,240 @@
+/*
+ * include/asm-m68k/dma.h
+ *
+ * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Hacked to fit Sun3x needs by Thomas Bogendoerfer
+ */
+
+#ifndef __M68K_DVMA_H
+#define __M68K_DVMA_H
+
+
+#define DVMA_PAGE_SHIFT 13
+#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
+#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
+#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
+
+extern void dvma_init(void);
+extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
+ int len);
+
+#define dvma_malloc(x) dvma_malloc_align(x, 0)
+#define dvma_map(x, y) dvma_map_align(x, y, 0)
+#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
+#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
+extern unsigned long dvma_map_align(unsigned long kaddr, int len,
+ int align);
+extern void *dvma_malloc_align(unsigned long len, unsigned long align);
+
+extern void dvma_unmap(void *baddr);
+extern void dvma_free(void *vaddr);
+
+
+#ifdef CONFIG_SUN3
+/* sun3 dvma page support */
+
+/* memory and pmegs potentially reserved for dvma */
+#define DVMA_PMEG_START 10
+#define DVMA_PMEG_END 16
+#define DVMA_START 0xf00000
+#define DVMA_END 0xfe0000
+#define DVMA_SIZE (DVMA_END-DVMA_START)
+#define IOMMU_TOTAL_ENTRIES 128
+#define IOMMU_ENTRIES 120
+
+/* empirical kludge -- dvma regions only seem to work right on 0x10000
+ byte boundaries */
+#define DVMA_REGION_SIZE 0x10000
+#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
+ ~(DVMA_REGION_SIZE-1))
+
+/* virt <-> phys conversions */
+#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
+#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
+#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
+#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
+#define dvma_vtob(x) dvma_vtop(x)
+#define dvma_btov(x) dvma_ptov(x)
+
+static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
+ int len)
+{
+ return 0;
+}
+
+#else /* Sun3x */
+
+/* sun3x dvma page support */
+
+#define DVMA_START 0x0
+#define DVMA_END 0xf00000
+#define DVMA_SIZE (DVMA_END-DVMA_START)
+#define IOMMU_TOTAL_ENTRIES 2048
+/* the prom takes the top meg */
+#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
+
+#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
+#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
+
+extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
+
+
+
+/* everything below this line is specific to dma used for the onboard
+ ESP scsi on sun3x */
+
+/* Structure to describe the current status of DMA registers on the Sparc */
+struct sparc_dma_registers {
+ __volatile__ unsigned long cond_reg; /* DMA condition register */
+ __volatile__ unsigned long st_addr; /* Start address of this transfer */
+ __volatile__ unsigned long cnt; /* How many bytes to transfer */
+ __volatile__ unsigned long dma_test; /* DMA test register */
+};
+
+/* DVMA chip revisions */
+enum dvma_rev {
+ dvmarev0,
+ dvmaesc1,
+ dvmarev1,
+ dvmarev2,
+ dvmarev3,
+ dvmarevplus,
+ dvmahme
+};
+
+#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct Linux_SBus_DMA {
+ struct Linux_SBus_DMA *next;
+ struct linux_sbus_device *SBus_dev;
+ struct sparc_dma_registers *regs;
+
+ /* Status, misc info */
+ int node; /* Prom node for this DMA device */
+ int running; /* Are we doing DMA now? */
+ int allocated; /* Are we "owned" by anyone yet? */
+
+ /* Transfer information. */
+ unsigned long addr; /* Start address of current transfer */
+ int nbytes; /* Size of current transfer */
+ int realbytes; /* For splitting up large transfers, etc. */
+
+ /* DMA revision */
+ enum dvma_rev revision;
+};
+
+extern struct Linux_SBus_DMA *dma_chain;
+
+/* Broken hardware... */
+#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
+#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
+#define DMA_VERS0 0x00000000 /* Sunray DMA version */
+#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
+#define DMA_VERS1 0x80000000 /* DMA rev 1 */
+#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
+#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
+#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
+#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
+#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
+#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
+#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
+#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
+#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
+#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
+#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
+#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
+#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
+#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
+#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
+#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
+#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
+#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1 0x01
+#define DMA_BURST2 0x02
+#define DMA_BURST4 0x04
+#define DMA_BURST8 0x08
+#define DMA_BURST16 0x10
+#define DMA_BURST32 0x20
+#define DMA_BURST64 0x40
+#define DMA_BURSTBITS 0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
+#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
+#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
+#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
+#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
+#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
+#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
+#define DMA_BEGINDMA_W(regs) \
+ ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
+#define DMA_BEGINDMA_R(regs) \
+ ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done. So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler. You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+ } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+ } while(0)
+
+/* Reset the friggin' thing... */
+#define DMA_RESET(dma) do { \
+ struct sparc_dma_registers *regs = dma->regs; \
+ /* Let the current FIFO drain itself */ \
+ sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
+ /* Reset the logic */ \
+ regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
+ __delay(400); /* let the bits set ;) */ \
+ regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
+ sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
+ /* Enable FAST transfers if available */ \
+ if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
+ dma->running = 0; \
+} while(0)
+
+
+#endif /* !CONFIG_SUN3 */
+
+#endif /* !(__M68K_DVMA_H) */
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
new file mode 100644
index 00000000000..e9b7cda5974
--- /dev/null
+++ b/arch/m68k/include/asm/elf.h
@@ -0,0 +1,118 @@
+#ifndef __ASMm68k_ELF_H
+#define __ASMm68k_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/*
+ * 68k ELF relocation types
+ */
+#define R_68K_NONE 0
+#define R_68K_32 1
+#define R_68K_16 2
+#define R_68K_8 3
+#define R_68K_PC32 4
+#define R_68K_PC16 5
+#define R_68K_PC8 6
+#define R_68K_GOT32 7
+#define R_68K_GOT16 8
+#define R_68K_GOT8 9
+#define R_68K_GOT32O 10
+#define R_68K_GOT16O 11
+#define R_68K_GOT8O 12
+#define R_68K_PLT32 13
+#define R_68K_PLT16 14
+#define R_68K_PLT8 15
+#define R_68K_PLT32O 16
+#define R_68K_PLT16O 17
+#define R_68K_PLT8O 18
+#define R_68K_COPY 19
+#define R_68K_GLOB_DAT 20
+#define R_68K_JMP_SLOT 21
+#define R_68K_RELATIVE 22
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_m68kfp_struct elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_68K)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS32
+#define ELF_DATA ELFDATA2MSB
+#define ELF_ARCH EM_68K
+
+/* For SVR4/m68k the function pointer to be registered with `atexit' is
+ passed in %a1. Although my copy of the ABI has no such statement, it
+ is actually used on ASV. */
+#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
+
+#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
+#define ELF_EXEC_PAGESIZE 8192
+#else
+#define ELF_EXEC_PAGESIZE 4096
+#endif
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#ifndef CONFIG_SUN3
+#define ELF_ET_DYN_BASE 0xD0000000UL
+#else
+#define ELF_ET_DYN_BASE 0x0D800000UL
+#endif
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) \
+ /* Bleech. */ \
+ pr_reg[0] = regs->d1; \
+ pr_reg[1] = regs->d2; \
+ pr_reg[2] = regs->d3; \
+ pr_reg[3] = regs->d4; \
+ pr_reg[4] = regs->d5; \
+ pr_reg[7] = regs->a0; \
+ pr_reg[8] = regs->a1; \
+ pr_reg[9] = regs->a2; \
+ pr_reg[14] = regs->d0; \
+ pr_reg[15] = rdusp(); \
+ pr_reg[16] = regs->orig_d0; \
+ pr_reg[17] = regs->sr; \
+ pr_reg[18] = regs->pc; \
+ pr_reg[19] = (regs->format << 12) | regs->vector; \
+ { \
+ struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
+ pr_reg[5] = sw->d6; \
+ pr_reg[6] = sw->d7; \
+ pr_reg[10] = sw->a3; \
+ pr_reg[11] = sw->a4; \
+ pr_reg[12] = sw->a5; \
+ pr_reg[13] = sw->a6; \
+ }
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. */
+
+#define ELF_HWCAP (0)
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo. */
+
+#define ELF_PLATFORM (NULL)
+
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+
+#endif
diff --git a/arch/m68k/include/asm/emergency-restart.h b/arch/m68k/include/asm/emergency-restart.h
new file mode 100644
index 00000000000..108d8c48e42
--- /dev/null
+++ b/arch/m68k/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h
new file mode 100644
index 00000000000..622138dc728
--- /dev/null
+++ b/arch/m68k/include/asm/entry.h
@@ -0,0 +1,262 @@
+#ifndef __M68K_ENTRY_H
+#define __M68K_ENTRY_H
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>
+#endif
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ * This allows access to the syscall arguments in registers d1-d5
+ *
+ * 0(sp) - d1
+ * 4(sp) - d2
+ * 8(sp) - d3
+ * C(sp) - d4
+ * 10(sp) - d5
+ * 14(sp) - a0
+ * 18(sp) - a1
+ * 1C(sp) - a2
+ * 20(sp) - d0
+ * 24(sp) - orig_d0
+ * 28(sp) - stack adjustment
+ * 2C(sp) - [ sr ] [ format & vector ]
+ * 2E(sp) - [ pc-hiword ] [ sr ]
+ * 30(sp) - [ pc-loword ] [ pc-hiword ]
+ * 32(sp) - [ format & vector ] [ pc-loword ]
+ * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
+ * M68K COLDFIRE
+ */
+
+/* the following macro is used when enabling interrupts */
+#if defined(MACH_ATARI_ONLY)
+ /* block out HSYNC on the atari */
+#define ALLOWINT (~0x400)
+#define MAX_NOINT_IPL 3
+#else
+ /* portable version */
+#define ALLOWINT (~0x700)
+#define MAX_NOINT_IPL 0
+#endif /* machine compilation types */
+
+#ifdef __ASSEMBLY__
+/*
+ * This defines the normal kernel pt-regs layout.
+ *
+ * regs a3-a6 and d6-d7 are preserved by C code
+ * the kernel doesn't mess with usp unless it needs to
+ */
+#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
+
+#ifdef CONFIG_COLDFIRE
+#ifdef CONFIG_COLDFIRE_SW_A7
+/*
+ * This is made a little more tricky on older ColdFires. There is no
+ * separate supervisor and user stack pointers. Need to artificially
+ * construct a usp in software... When doing this we need to disable
+ * interrupts, otherwise bad things will happen.
+ */
+.globl sw_usp
+.globl sw_ksp
+
+.macro SAVE_ALL_SYS
+ move #0x2700,%sr /* disable intrs */
+ btst #5,%sp@(2) /* from user? */
+ bnes 6f /* no, skip */
+ movel %sp,sw_usp /* save user sp */
+ addql #8,sw_usp /* remove exception */
+ movel sw_ksp,%sp /* kernel sp */
+ subql #8,%sp /* room for exception */
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+ movel sw_usp,%a0 /* get usp */
+ movel %a0@-,%sp@(PT_OFF_PC) /* copy exception program counter */
+ movel %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
+ bra 7f
+ 6:
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+ 7:
+.endm
+
+.macro SAVE_ALL_INT
+ SAVE_ALL_SYS
+ moveq #-1,%d0 /* not system call entry */
+ movel %d0,%sp@(PT_OFF_ORIG_D0)
+.endm
+
+.macro RESTORE_USER
+ move #0x2700,%sr /* disable intrs */
+ movel sw_usp,%a0 /* get usp */
+ movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
+ movel %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
+ moveml %sp@,%d1-%d5/%a0-%a2
+ lea %sp@(32),%sp /* space for 8 regs */
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stkadj */
+ addql #8,%sp /* remove exception */
+ movel %sp,sw_ksp /* save ksp */
+ subql #8,sw_usp /* set exception */
+ movel sw_usp,%sp /* restore usp */
+ rte
+.endm
+
+.macro RDUSP
+ movel sw_usp,%a3
+.endm
+
+.macro WRUSP
+ movel %a3,sw_usp
+.endm
+
+#else /* !CONFIG_COLDFIRE_SW_A7 */
+/*
+ * Modern ColdFire parts have separate supervisor and user stack
+ * pointers. Simple load and restore macros for this case.
+ */
+.macro SAVE_ALL_SYS
+ move #0x2700,%sr /* disable intrs */
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+.endm
+
+.macro SAVE_ALL_INT
+ move #0x2700,%sr /* disable intrs */
+ clrl %sp@- /* stkadj */
+ pea -1:w /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+.endm
+
+.macro RESTORE_USER
+ moveml %sp@,%d1-%d5/%a0-%a2
+ lea %sp@(32),%sp /* space for 8 regs */
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stkadj */
+ rte
+.endm
+
+.macro RDUSP
+ /*move %usp,%a3*/
+ .word 0x4e6b
+.endm
+
+.macro WRUSP
+ /*move %a3,%usp*/
+ .word 0x4e63
+.endm
+
+#endif /* !CONFIG_COLDFIRE_SW_A7 */
+
+.macro SAVE_SWITCH_STACK
+ lea %sp@(-24),%sp /* 6 regs */
+ moveml %a3-%a6/%d6-%d7,%sp@
+.endm
+
+.macro RESTORE_SWITCH_STACK
+ moveml %sp@,%a3-%a6/%d6-%d7
+ lea %sp@(24),%sp /* 6 regs */
+.endm
+
+#else /* !CONFIG_COLDFIRE */
+
+/*
+ * All other types of m68k parts (68000, 680x0, CPU32) have the same
+ * entry and exit code.
+ */
+
+/*
+ * a -1 in the orig_d0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro SAVE_ALL_INT
+ clrl %sp@- /* stk_adj */
+ pea -1:w /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ moveml %d1-%d5/%a0-%a2,%sp@-
+.endm
+
+.macro SAVE_ALL_SYS
+ clrl %sp@- /* stk_adj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ moveml %d1-%d5/%a0-%a2,%sp@-
+.endm
+
+.macro RESTORE_ALL
+ moveml %sp@+,%a0-%a2/%d1-%d5
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stk adj */
+ rte
+.endm
+
+
+.macro SAVE_SWITCH_STACK
+ moveml %a3-%a6/%d6-%d7,%sp@-
+.endm
+
+.macro RESTORE_SWITCH_STACK
+ moveml %sp@+,%a3-%a6/%d6-%d7
+.endm
+
+#endif /* !CONFIG_COLDFIRE */
+
+/*
+ * Register %a2 is reserved and set to current task on MMU enabled systems.
+ * Non-MMU systems do not reserve %a2 in this way, and this definition is
+ * not used for them.
+ */
+#ifdef CONFIG_MMU
+
+#define curptr a2
+
+#define GET_CURRENT(tmp) get_current tmp
+.macro get_current reg=%d0
+ movel %sp,\reg
+ andl #-THREAD_SIZE,\reg
+ movel \reg,%curptr
+ movel %curptr@,%curptr
+.endm
+
+#else
+
+#define GET_CURRENT(tmp)
+
+#endif /* CONFIG_MMU */
+
+#else /* C source */
+
+#define STR(X) STR1(X)
+#define STR1(X) #X
+
+#define SAVE_ALL_INT \
+ "clrl %%sp@-;" /* stk_adj */ \
+ "pea -1:w;" /* orig d0 = -1 */ \
+ "movel %%d0,%%sp@-;" /* d0 */ \
+ "moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
+
+#define GET_CURRENT(tmp) \
+ "movel %%sp,"#tmp"\n\t" \
+ "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
+ "movel "#tmp",%%a2\n\t" \
+ "movel %%a2@,%%a2"
+
+#endif
+
+#endif /* __M68K_ENTRY_H */
diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h
new file mode 100644
index 00000000000..0d4e188d6ef
--- /dev/null
+++ b/arch/m68k/include/asm/errno.h
@@ -0,0 +1,6 @@
+#ifndef _M68K_ERRNO_H
+#define _M68K_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif /* _M68K_ERRNO_H */
diff --git a/arch/m68k/include/asm/fb.h b/arch/m68k/include/asm/fb.h
new file mode 100644
index 00000000000..be4e4c6797e
--- /dev/null
+++ b/arch/m68k/include/asm/fb.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+
+#ifdef CONFIG_MMU
+#ifdef CONFIG_SUN3
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+ unsigned long off)
+{
+ pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
+}
+#else
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+ unsigned long off)
+{
+ if (CPU_IS_020_OR_030)
+ pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
+ if (CPU_IS_040_OR_060) {
+ pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
+ /* Use no-cache mode, serialized */
+ pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
+ }
+}
+#endif /* CONFIG_SUN3 */
+#else
+#define fb_pgprotect(...) do {} while (0)
+#endif /* CONFIG_MMU */
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+ return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/m68k/include/asm/fbio.h b/arch/m68k/include/asm/fbio.h
new file mode 100644
index 00000000000..0a21da87f7d
--- /dev/null
+++ b/arch/m68k/include/asm/fbio.h
@@ -0,0 +1,330 @@
+#ifndef __LINUX_FBIO_H
+#define __LINUX_FBIO_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/* Constants used for fbio SunOS compatibility */
+/* (C) 1996 Miguel de Icaza */
+
+/* Frame buffer types */
+#define FBTYPE_NOTYPE -1
+#define FBTYPE_SUN1BW 0 /* mono */
+#define FBTYPE_SUN1COLOR 1
+#define FBTYPE_SUN2BW 2
+#define FBTYPE_SUN2COLOR 3
+#define FBTYPE_SUN2GP 4
+#define FBTYPE_SUN5COLOR 5
+#define FBTYPE_SUN3COLOR 6
+#define FBTYPE_MEMCOLOR 7
+#define FBTYPE_SUN4COLOR 8
+
+#define FBTYPE_NOTSUN1 9
+#define FBTYPE_NOTSUN2 10
+#define FBTYPE_NOTSUN3 11
+
+#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
+#define FBTYPE_SUNROP_COLOR 13
+#define FBTYPE_SUNFB_VIDEO 14
+#define FBTYPE_SUNGIFB 15
+#define FBTYPE_SUNGPLAS 16
+#define FBTYPE_SUNGP3 17
+#define FBTYPE_SUNGT 18
+#define FBTYPE_SUNLEO 19 /* zx Leo card */
+#define FBTYPE_MDICOLOR 20 /* cg14 */
+#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
+
+#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
+
+/* Does not seem to be listed in the Sun file either */
+#define FBTYPE_CREATOR 22
+#define FBTYPE_PCI_IGA1682 23
+#define FBTYPE_P9100COLOR 24
+
+#define FBTYPE_PCI_GENERIC 1000
+#define FBTYPE_PCI_MACH64 1001
+
+/* fbio ioctls */
+/* Returned by FBIOGTYPE */
+struct fbtype {
+ int fb_type; /* fb type, see above */
+ int fb_height; /* pixels */
+ int fb_width; /* pixels */
+ int fb_depth;
+ int fb_cmsize; /* color map entries */
+ int fb_size; /* fb size in bytes */
+};
+#define FBIOGTYPE _IOR('F', 0, struct fbtype)
+
+struct fbcmap {
+ int index; /* first element (0 origin) */
+ int count;
+ unsigned char __user *red;
+ unsigned char __user *green;
+ unsigned char __user *blue;
+};
+
+#ifdef __KERNEL__
+#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
+#else
+#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
+#endif
+
+/* # of device specific values */
+#define FB_ATTR_NDEVSPECIFIC 8
+/* # of possible emulations */
+#define FB_ATTR_NEMUTYPES 4
+
+struct fbsattr {
+ int flags;
+ int emu_type; /* -1 if none */
+ int dev_specific[FB_ATTR_NDEVSPECIFIC];
+};
+
+struct fbgattr {
+ int real_type; /* real frame buffer type */
+ int owner; /* unknown */
+ struct fbtype fbtype; /* real frame buffer fbtype */
+ struct fbsattr sattr;
+ int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
+};
+#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
+#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
+
+#define FBIOSVIDEO _IOW('F', 7, int)
+#define FBIOGVIDEO _IOR('F', 8, int)
+
+struct fbcursor {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ char __user *image; /* cursor image bits */
+ char __user *mask; /* cursor mask bits */
+};
+
+/* set/get cursor attributes/shape */
+#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
+#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
+
+/* set/get cursor position */
+#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
+#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
+
+/* get max cursor size */
+#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
+
+/* wid manipulation */
+struct fb_wid_alloc {
+#define FB_WID_SHARED_8 0
+#define FB_WID_SHARED_24 1
+#define FB_WID_DBL_8 2
+#define FB_WID_DBL_24 3
+ __u32 wa_type;
+ __s32 wa_index; /* Set on return */
+ __u32 wa_count;
+};
+struct fb_wid_item {
+ __u32 wi_type;
+ __s32 wi_index;
+ __u32 wi_attrs;
+ __u32 wi_values[32];
+};
+struct fb_wid_list {
+ __u32 wl_flags;
+ __u32 wl_count;
+ struct fb_wid_item *wl_list;
+};
+
+#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
+#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
+#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
+#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
+
+/* Creator ioctls */
+#define FFB_IOCTL ('F'<<8)
+#define FFB_SYS_INFO (FFB_IOCTL|80)
+#define FFB_CLUTREAD (FFB_IOCTL|81)
+#define FFB_CLUTPOST (FFB_IOCTL|82)
+#define FFB_SETDIAGMODE (FFB_IOCTL|83)
+#define FFB_GETMONITORID (FFB_IOCTL|84)
+#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
+#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
+#define FFB_SETSERVER (FFB_IOCTL|87)
+#define FFB_SETOVCTL (FFB_IOCTL|88)
+#define FFB_GETOVCTL (FFB_IOCTL|89)
+#define FFB_GETSAXNUM (FFB_IOCTL|90)
+#define FFB_FBDEBUG (FFB_IOCTL|91)
+
+/* Cg14 ioctls */
+#define MDI_IOCTL ('M'<<8)
+#define MDI_RESET (MDI_IOCTL|1)
+#define MDI_GET_CFGINFO (MDI_IOCTL|2)
+#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
+# define MDI_32_PIX 32
+# define MDI_16_PIX 16
+# define MDI_8_PIX 8
+
+struct mdi_cfginfo {
+ int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
+ int mdi_type; /* FBTYPE name */
+ int mdi_height; /* height */
+ int mdi_width; /* width */
+ int mdi_size; /* available ram */
+ int mdi_mode; /* 8bpp, 16bpp or 32bpp */
+ int mdi_pixfreq; /* pixel clock (from PROM) */
+};
+
+/* SparcLinux specific ioctl for the MDI, should be replaced for
+ * the SET_XLUT/SET_CLUTn ioctls instead
+ */
+#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
+
+/* leo & ffb ioctls */
+struct fb_clut_alloc {
+ __u32 clutid; /* Set on return */
+ __u32 flag;
+ __u32 index;
+};
+
+struct fb_clut {
+#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ char * red;
+ char * green;
+ char * blue;
+};
+
+struct fb_clut32 {
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ __u32 red;
+ __u32 green;
+ __u32 blue;
+};
+
+#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
+#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
+#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
+#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
+#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
+#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
+
+#ifdef __KERNEL__
+/* Addresses on the fd of a cgsix that are mappable */
+#define CG6_FBC 0x70000000
+#define CG6_TEC 0x70001000
+#define CG6_BTREGS 0x70002000
+#define CG6_FHC 0x70004000
+#define CG6_THC 0x70005000
+#define CG6_ROM 0x70006000
+#define CG6_RAM 0x70016000
+#define CG6_DHC 0x80000000
+
+#define CG3_MMAP_OFFSET 0x4000000
+
+/* Addresses on the fd of a tcx that are mappable */
+#define TCX_RAM8BIT 0x00000000
+#define TCX_RAM24BIT 0x01000000
+#define TCX_UNK3 0x10000000
+#define TCX_UNK4 0x20000000
+#define TCX_CONTROLPLANE 0x28000000
+#define TCX_UNK6 0x30000000
+#define TCX_UNK7 0x38000000
+#define TCX_TEC 0x70000000
+#define TCX_BTREGS 0x70002000
+#define TCX_THC 0x70004000
+#define TCX_DHC 0x70008000
+#define TCX_ALT 0x7000a000
+#define TCX_SYNC 0x7000e000
+#define TCX_UNK2 0x70010000
+
+/* CG14 definitions */
+
+/* Offsets into the OBIO space: */
+#define CG14_REGS 0 /* registers */
+#define CG14_CURSORREGS 0x1000 /* cursor registers */
+#define CG14_DACREGS 0x2000 /* DAC registers */
+#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
+#define CG14_CLUT1 0x4000 /* Color Look Up Table */
+#define CG14_CLUT2 0x5000 /* Color Look Up Table */
+#define CG14_CLUT3 0x6000 /* Color Look Up Table */
+#define CG14_AUTO 0xf000
+
+#endif /* KERNEL */
+
+/* These are exported to userland for applications to use */
+/* Mappable offsets for the cg14: control registers */
+#define MDI_DIRECT_MAP 0x10000000
+#define MDI_CTLREG_MAP 0x20000000
+#define MDI_CURSOR_MAP 0x30000000
+#define MDI_SHDW_VRT_MAP 0x40000000
+
+/* Mappable offsets for the cg14: frame buffer resolutions */
+/* 32 bits */
+#define MDI_CHUNKY_XBGR_MAP 0x50000000
+#define MDI_CHUNKY_BGR_MAP 0x60000000
+
+/* 16 bits */
+#define MDI_PLANAR_X16_MAP 0x70000000
+#define MDI_PLANAR_C16_MAP 0x80000000
+
+/* 8 bit is done as CG3 MMAP offset */
+/* 32 bits, planar */
+#define MDI_PLANAR_X32_MAP 0x90000000
+#define MDI_PLANAR_B32_MAP 0xa0000000
+#define MDI_PLANAR_G32_MAP 0xb0000000
+#define MDI_PLANAR_R32_MAP 0xc0000000
+
+/* Mappable offsets on leo */
+#define LEO_SS0_MAP 0x00000000
+#define LEO_LC_SS0_USR_MAP 0x00800000
+#define LEO_LD_SS0_MAP 0x00801000
+#define LEO_LX_CURSOR_MAP 0x00802000
+#define LEO_SS1_MAP 0x00803000
+#define LEO_LC_SS1_USR_MAP 0x01003000
+#define LEO_LD_SS1_MAP 0x01004000
+#define LEO_UNK_MAP 0x01005000
+#define LEO_LX_KRN_MAP 0x01006000
+#define LEO_LC_SS0_KRN_MAP 0x01007000
+#define LEO_LC_SS1_KRN_MAP 0x01008000
+#define LEO_LD_GBL_MAP 0x01009000
+#define LEO_UNK2_MAP 0x0100a000
+
+#ifdef __KERNEL__
+struct fbcmap32 {
+ int index; /* first element (0 origin) */
+ int count;
+ u32 red;
+ u32 green;
+ u32 blue;
+};
+
+#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
+#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
+
+struct fbcursor32 {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap32 cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ u32 image; /* cursor image bits */
+ u32 mask; /* cursor mask bits */
+};
+
+#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
+#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
+#endif
+
+#endif /* __LINUX_FBIO_H */
diff --git a/arch/m68k/include/asm/fcntl.h b/arch/m68k/include/asm/fcntl.h
new file mode 100644
index 00000000000..1c369b20dc4
--- /dev/null
+++ b/arch/m68k/include/asm/fcntl.h
@@ -0,0 +1,11 @@
+#ifndef _M68K_FCNTL_H
+#define _M68K_FCNTL_H
+
+#define O_DIRECTORY 040000 /* must be a directory */
+#define O_NOFOLLOW 0100000 /* don't follow links */
+#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
+#define O_LARGEFILE 0400000
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _M68K_FCNTL_H */
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h
new file mode 100644
index 00000000000..a0e29079397
--- /dev/null
+++ b/arch/m68k/include/asm/flat.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-m68knommu/flat.h -- uClinux flat-format executables
+ */
+
+#ifndef __M68KNOMMU_FLAT_H__
+#define __M68KNOMMU_FLAT_H__
+
+#define flat_argvp_envp_on_stack() 1
+#define flat_old_ram_flag(flags) (flags)
+#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
+#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
+#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
+#define flat_get_relocate_addr(rel) (rel)
+#define flat_set_persistent(relval, p) 0
+
+#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68k/include/asm/floppy.h b/arch/m68k/include/asm/floppy.h
new file mode 100644
index 00000000000..697d50393dd
--- /dev/null
+++ b/arch/m68k/include/asm/floppy.h
@@ -0,0 +1,254 @@
+/*
+ * Implementation independent bits of the Floppy driver.
+ *
+ * much of this file is derived from what was originally the Q40 floppy driver.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 2001
+ *
+ * Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net)
+ *
+ */
+
+#include <asm/io.h>
+
+#include <linux/vmalloc.h>
+
+asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id);
+
+/* constants... */
+
+#undef MAX_DMA_ADDRESS
+#define MAX_DMA_ADDRESS 0x00 /* nothing like that */
+
+
+/*
+ * Again, the CMOS information doesn't work on m68k..
+ */
+#define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4)
+#define FLOPPY1_TYPE 0
+
+/* basically PC init + set use_virtual_dma */
+#define FDC1 m68k_floppy_init()
+
+#define N_FDC 1
+#define N_DRIVE 8
+
+
+/* vdma globals adapted from asm-i386/floppy.h */
+
+static int virtual_dma_count=0;
+static int virtual_dma_residue=0;
+static char *virtual_dma_addr=NULL;
+static int virtual_dma_mode=0;
+static int doing_pdma=0;
+
+#include <asm/sun3xflop.h>
+
+extern spinlock_t dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_spin_lock, flags);
+ return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+
+static __inline__ unsigned char fd_inb(int port)
+{
+ if(MACH_IS_Q40)
+ return inb_p(port);
+ else if(MACH_IS_SUN3X)
+ return sun3x_82072_fd_inb(port);
+ return 0;
+}
+
+static __inline__ void fd_outb(unsigned char value, int port)
+{
+ if(MACH_IS_Q40)
+ outb_p(value, port);
+ else if(MACH_IS_SUN3X)
+ sun3x_82072_fd_outb(value, port);
+}
+
+
+static int fd_request_irq(void)
+{
+ if(MACH_IS_Q40)
+ return request_irq(FLOPPY_IRQ, floppy_hardint,
+ IRQF_DISABLED, "floppy", floppy_hardint);
+ else if(MACH_IS_SUN3X)
+ return sun3xflop_request_irq();
+ return -ENXIO;
+}
+
+static void fd_free_irq(void)
+{
+ if(MACH_IS_Q40)
+ free_irq(FLOPPY_IRQ, floppy_hardint);
+}
+
+#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
+#define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA)
+#define fd_dma_mem_alloc(size) vdma_mem_alloc(size)
+#define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io)
+
+#define fd_enable_irq() /* nothing... */
+#define fd_disable_irq() /* nothing... */
+
+#define fd_free_dma() /* nothing */
+
+/* No 64k boundary crossing problems on Q40 - no DMA at all */
+#define CROSS_64KB(a,s) (0)
+
+#define DMA_MODE_READ 0x44 /* i386 look-alike */
+#define DMA_MODE_WRITE 0x48
+
+
+static int m68k_floppy_init(void)
+{
+ use_virtual_dma =1;
+ can_use_virtual_dma = 1;
+
+
+ if (MACH_IS_Q40)
+ return 0x3f0;
+ else if(MACH_IS_SUN3X)
+ return sun3xflop_init();
+ else
+ return -1;
+}
+
+
+static int vdma_request_dma(unsigned int dmanr, const char * device_id)
+{
+ return 0;
+}
+
+
+static int vdma_get_dma_residue(unsigned int dummy)
+{
+ return virtual_dma_count + virtual_dma_residue;
+}
+
+
+static unsigned long vdma_mem_alloc(unsigned long size)
+{
+ return (unsigned long) vmalloc(size);
+
+}
+
+static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+ vfree((void *)addr);
+}
+#define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size)
+
+
+/* choose_dma_mode ???*/
+
+static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+ doing_pdma = 1;
+ virtual_dma_port = (MACH_IS_Q40 ? io : 0);
+ virtual_dma_mode = (mode == DMA_MODE_WRITE);
+ virtual_dma_addr = addr;
+ virtual_dma_count = size;
+ virtual_dma_residue = 0;
+ return 0;
+}
+
+
+
+static void fd_disable_dma(void)
+{
+ doing_pdma = 0;
+ virtual_dma_residue += virtual_dma_count;
+ virtual_dma_count=0;
+}
+
+
+
+/* this is the only truly Q40 specific function */
+
+asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id)
+{
+ register unsigned char st;
+
+#undef TRACE_FLPY_INT
+#define NO_FLOPPY_ASSEMBLER
+
+#ifdef TRACE_FLPY_INT
+ static int calls=0;
+ static int bytes=0;
+ static int dma_wait=0;
+#endif
+ if(!doing_pdma) {
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+
+#ifdef TRACE_FLPY_INT
+ if(!calls)
+ bytes = virtual_dma_count;
+#endif
+
+ {
+ register int lcount;
+ register char *lptr;
+
+ /* serve 1st byte fast: */
+
+ st=1;
+ for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
+ lcount; lcount--, lptr++) {
+ st=inb(virtual_dma_port+4) & 0xa0 ;
+ if(st != 0xa0)
+ break;
+ if(virtual_dma_mode)
+ outb_p(*lptr, virtual_dma_port+5);
+ else
+ *lptr = inb_p(virtual_dma_port+5);
+ }
+
+ virtual_dma_count = lcount;
+ virtual_dma_addr = lptr;
+ st = inb(virtual_dma_port+4);
+ }
+
+#ifdef TRACE_FLPY_INT
+ calls++;
+#endif
+ if(st == 0x20)
+ return IRQ_HANDLED;
+ if(!(st & 0x20)) {
+ virtual_dma_residue += virtual_dma_count;
+ virtual_dma_count=0;
+#ifdef TRACE_FLPY_INT
+ printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
+ virtual_dma_count, virtual_dma_residue, calls, bytes,
+ dma_wait);
+ calls = 0;
+ dma_wait=0;
+#endif
+ doing_pdma = 0;
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+#ifdef TRACE_FLPY_INT
+ if(!virtual_dma_count)
+ dma_wait++;
+#endif
+ return IRQ_HANDLED;
+}
+
+#define EXTRA_FLOPPY_PARAMS
diff --git a/arch/m68k/include/asm/fpu.h b/arch/m68k/include/asm/fpu.h
new file mode 100644
index 00000000000..526db9da9e4
--- /dev/null
+++ b/arch/m68k/include/asm/fpu.h
@@ -0,0 +1,23 @@
+#ifndef __M68K_FPU_H
+#define __M68K_FPU_H
+
+
+/*
+ * MAX floating point unit state size (FSAVE/FRESTORE)
+ */
+
+#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
+#define FPSTATESIZE (216)
+#elif defined(CONFIG_M68040)
+#define FPSTATESIZE (96)
+#elif defined(CONFIG_M68KFPU_EMU)
+#define FPSTATESIZE (28)
+#elif defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
+#define FPSTATESIZE (16)
+#elif defined(CONFIG_M68060)
+#define FPSTATESIZE (12)
+#else
+#define FPSTATESIZE (0)
+#endif
+
+#endif /* __M68K_FPU_H */
diff --git a/arch/m68k/include/asm/ftrace.h b/arch/m68k/include/asm/ftrace.h
new file mode 100644
index 00000000000..40a8c178f10
--- /dev/null
+++ b/arch/m68k/include/asm/ftrace.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h
new file mode 100644
index 00000000000..6a332a9f099
--- /dev/null
+++ b/arch/m68k/include/asm/futex.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <asm-generic/futex.h>
+
+#endif
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
new file mode 100644
index 00000000000..00d0071de4c
--- /dev/null
+++ b/arch/m68k/include/asm/gpio.h
@@ -0,0 +1,244 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
+
+#ifndef coldfire_gpio_h
+#define coldfire_gpio_h
+
+#include <linux/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+/*
+ * The Freescale Coldfire family is quite varied in how they implement GPIO.
+ * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
+ * only one port, others have multiple ports; some have a single data latch
+ * for both input and output, others have a separate pin data register to read
+ * input; some require a read-modify-write access to change an output, others
+ * have set and clear registers for some of the outputs; Some have all the
+ * GPIOs in a single control area, others have some GPIOs implemented in
+ * different modules.
+ *
+ * This implementation attempts accommodate the differences while presenting
+ * a generic interface that will optimize to as few instructions as possible.
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M532x) || defined(CONFIG_M54xx)
+
+/* These parts have GPIO organized by 8 bit ports */
+
+#define MCFGPIO_PORTTYPE u8
+#define MCFGPIO_PORTSIZE 8
+#define mcfgpio_read(port) __raw_readb(port)
+#define mcfgpio_write(data, port) __raw_writeb(data, port)
+
+#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
+
+/* These parts have GPIO organized by 16 bit ports */
+
+#define MCFGPIO_PORTTYPE u16
+#define MCFGPIO_PORTSIZE 16
+#define mcfgpio_read(port) __raw_readw(port)
+#define mcfgpio_write(data, port) __raw_writew(data, port)
+
+#elif defined(CONFIG_M5249)
+
+/* These parts have GPIO organized by 32 bit ports */
+
+#define MCFGPIO_PORTTYPE u32
+#define MCFGPIO_PORTSIZE 32
+#define mcfgpio_read(port) __raw_readl(port)
+#define mcfgpio_write(data, port) __raw_writel(data, port)
+
+#endif
+
+#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
+#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
+
+#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+/*
+ * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
+ * read-modify-write to change an output and a GPIO module which has separate
+ * set/clr registers to directly change outputs with a single write access.
+ */
+#if defined(CONFIG_M528x)
+/*
+ * The 528x also has GPIOs in other modules (GPT, QADC) which use
+ * read-modify-write as well as those controlled by the EPORT and GPIO modules.
+ */
+#define MCFGPIO_SCR_START 40
+#else
+#define MCFGPIO_SCR_START 8
+#endif
+
+#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
+ mcfgpio_port(gpio - MCFGPIO_SCR_START))
+
+#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
+ mcfgpio_port(gpio - MCFGPIO_SCR_START))
+#else
+
+#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
+/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
+#define MCFGPIO_SETR_PORT(gpio) 0
+#define MCFGPIO_CLRR_PORT(gpio) 0
+
+#endif
+/*
+ * Coldfire specific helper functions
+ */
+
+/* return the port pin data register for a gpio */
+static inline u32 __mcf_gpio_ppdr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+ return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+ if (gpio < 16)
+ return MCFSIM_PADAT;
+ else if (gpio < 32)
+ return MCFSIM_PBDAT;
+ else
+ return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249)
+ if (gpio < 32)
+ return MCFSIM2_GPIOREAD;
+ else
+ return MCFSIM2_GPIO1READ;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+ if (gpio < 8)
+ return MCFEPORT_EPPDR;
+#if defined(CONFIG_M528x)
+ else if (gpio < 16)
+ return MCFGPTA_GPTPORT;
+ else if (gpio < 24)
+ return MCFGPTB_GPTPORT;
+ else if (gpio < 32)
+ return MCFQADC_PORTQA;
+ else if (gpio < 40)
+ return MCFQADC_PORTQB;
+#endif
+ else
+ return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+ return 0;
+#endif
+}
+
+/* return the port output data register for a gpio */
+static inline u32 __mcf_gpio_podr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+ return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+ if (gpio < 16)
+ return MCFSIM_PADAT;
+ else if (gpio < 32)
+ return MCFSIM_PBDAT;
+ else
+ return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249)
+ if (gpio < 32)
+ return MCFSIM2_GPIOWRITE;
+ else
+ return MCFSIM2_GPIO1WRITE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+ if (gpio < 8)
+ return MCFEPORT_EPDR;
+#if defined(CONFIG_M528x)
+ else if (gpio < 16)
+ return MCFGPTA_GPTPORT;
+ else if (gpio < 24)
+ return MCFGPTB_GPTPORT;
+ else if (gpio < 32)
+ return MCFQADC_PORTQA;
+ else if (gpio < 40)
+ return MCFQADC_PORTQB;
+#endif
+ else
+ return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+ return 0;
+#endif
+}
+
+/*
+ * The Generic GPIO functions
+ *
+ * If the gpio is a compile time constant and is one of the Coldfire gpios,
+ * use the inline version, otherwise dispatch thru gpiolib.
+ */
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
+ return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
+ else
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) {
+ if (gpio < MCFGPIO_SCR_START) {
+ unsigned long flags;
+ MCFGPIO_PORTTYPE data;
+
+ local_irq_save(flags);
+ data = mcfgpio_read(__mcf_gpio_podr(gpio));
+ if (value)
+ data |= mcfgpio_bit(gpio);
+ else
+ data &= ~mcfgpio_bit(gpio);
+ mcfgpio_write(data, __mcf_gpio_podr(gpio));
+ local_irq_restore(flags);
+ } else {
+ if (value)
+ mcfgpio_write(mcfgpio_bit(gpio),
+ MCFGPIO_SETR_PORT(gpio));
+ else
+ mcfgpio_write(~mcfgpio_bit(gpio),
+ MCFGPIO_CLRR_PORT(gpio));
+ }
+ } else
+ __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE
+ : __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return (irq >= MCFGPIO_IRQ_VECBASE &&
+ irq < (MCFGPIO_IRQ_VECBASE + MCFGPIO_IRQ_MAX)) ?
+ irq - MCFGPIO_IRQ_VECBASE : -ENXIO;
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+ return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
+}
+
+#endif
diff --git a/arch/m68k/include/asm/hardirq.h b/arch/m68k/include/asm/hardirq.h
new file mode 100644
index 00000000000..db30ed27687
--- /dev/null
+++ b/arch/m68k/include/asm/hardirq.h
@@ -0,0 +1,39 @@
+#ifndef __M68K_HARDIRQ_H
+#define __M68K_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/cache.h>
+#include <asm/irq.h>
+
+#define HARDIRQ_BITS 8
+
+/*
+ * The hardirq mask has to be large enough to have
+ * space for potentially all IRQ sources in the system
+ * nesting on a single CPU:
+ */
+#if (1 << HARDIRQ_BITS) < NR_IRQS
+# error HARDIRQ_BITS is too low!
+#endif
+
+#ifdef CONFIG_MMU
+
+static inline void ack_bad_irq(unsigned int irq)
+{
+ pr_crit("unexpected IRQ trap at vector %02x\n", irq);
+}
+
+/* entry.S is sensitive to the offsets of these fields */
+typedef struct {
+ unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
+
+#else
+
+#include <asm-generic/hardirq.h>
+
+#endif /* !CONFIG_MMU */
+
+#endif
diff --git a/arch/m68k/include/asm/hp300hw.h b/arch/m68k/include/asm/hp300hw.h
new file mode 100644
index 00000000000..d998ea67c19
--- /dev/null
+++ b/arch/m68k/include/asm/hp300hw.h
@@ -0,0 +1,25 @@
+#ifndef _M68K_HP300HW_H
+#define _M68K_HP300HW_H
+
+extern unsigned long hp300_model;
+
+/* This information was taken from NetBSD */
+#define HP_320 (0) /* 16MHz 68020+HP MMU+16K external cache */
+#define HP_330 (1) /* 16MHz 68020+68851 MMU */
+#define HP_340 (2) /* 16MHz 68030 */
+#define HP_345 (3) /* 50MHz 68030+32K external cache */
+#define HP_350 (4) /* 25MHz 68020+HP MMU+32K external cache */
+#define HP_360 (5) /* 25MHz 68030 */
+#define HP_370 (6) /* 33MHz 68030+64K external cache */
+#define HP_375 (7) /* 50MHz 68030+32K external cache */
+#define HP_380 (8) /* 25MHz 68040 */
+#define HP_385 (9) /* 33MHz 68040 */
+
+#define HP_400 (10) /* 50MHz 68030+32K external cache */
+#define HP_425T (11) /* 25MHz 68040 - model 425t */
+#define HP_425S (12) /* 25MHz 68040 - model 425s */
+#define HP_425E (13) /* 25MHz 68040 - model 425e */
+#define HP_433T (14) /* 33MHz 68040 - model 433t */
+#define HP_433S (15) /* 33MHz 68040 - model 433s */
+
+#endif /* _M68K_HP300HW_H */
diff --git a/arch/m68k/include/asm/hw_irq.h b/arch/m68k/include/asm/hw_irq.h
new file mode 100644
index 00000000000..eacef0951fb
--- /dev/null
+++ b/arch/m68k/include/asm/hw_irq.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_M68K_HW_IRQ_H
+#define __ASM_M68K_HW_IRQ_H
+
+/* Dummy include. */
+
+#endif
diff --git a/arch/m68k/include/asm/hwtest.h b/arch/m68k/include/asm/hwtest.h
new file mode 100644
index 00000000000..402c8a4401f
--- /dev/null
+++ b/arch/m68k/include/asm/hwtest.h
@@ -0,0 +1,15 @@
+/* Routines to test for presence/absence of hardware registers:
+ * see arch/m68k/mm/hwtest.c.
+ * -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998
+ *
+ * Removed __init from decls. We might want them in modules, and
+ * the code is tiny anyway. 16/5/98 pb
+ */
+
+#ifndef __ASM_HWTEST_H
+#define __ASM_HWTEST_H
+
+extern int hwreg_present(volatile void *regp);
+extern int hwreg_write(volatile void *regp, unsigned short val);
+
+#endif
diff --git a/arch/m68k/include/asm/ide.h b/arch/m68k/include/asm/ide.h
new file mode 100644
index 00000000000..492fee8a1ab
--- /dev/null
+++ b/arch/m68k/include/asm/ide.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 1994-1996 Linus Torvalds & authors
+ */
+
+/* Copyright(c) 1996 Kars de Jong */
+/* Based on the ide driver from 1.2.13pl8 */
+
+/*
+ * Credits (alphabetical):
+ *
+ * - Bjoern Brauel
+ * - Kars de Jong
+ * - Torsten Ebeling
+ * - Dwight Engen
+ * - Thorsten Floeck
+ * - Roman Hodek
+ * - Guenther Kelleter
+ * - Chris Lawrence
+ * - Michael Rausch
+ * - Christian Sauer
+ * - Michael Schmitz
+ * - Jes Soerensen
+ * - Michael Thurm
+ * - Geert Uytterhoeven
+ */
+
+#ifndef _M68K_IDE_H
+#define _M68K_IDE_H
+
+#ifdef __KERNEL__
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#ifdef CONFIG_MMU
+
+/*
+ * Get rid of defs from io.h - ide has its private and conflicting versions
+ * Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we
+ * always use the `raw' MMIO versions
+ */
+#undef readb
+#undef readw
+#undef writeb
+#undef writew
+
+#define readb in_8
+#define readw in_be16
+#define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n)
+#define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n)
+#define writeb(val, port) out_8(port, val)
+#define writew(val, port) out_be16(port, val)
+#define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
+#define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
+
+#else
+
+#define __ide_mm_insw(port, addr, n) io_insw((unsigned int)port, addr, n)
+#define __ide_mm_insl(port, addr, n) io_insl((unsigned int)port, addr, n)
+#define __ide_mm_outsw(port, addr, n) io_outsw((unsigned int)port, addr, n)
+#define __ide_mm_outsl(port, addr, n) io_outsl((unsigned int)port, addr, n)
+
+#endif /* CONFIG_MMU */
+
+#endif /* __KERNEL__ */
+#endif /* _M68K_IDE_H */
diff --git a/arch/m68k/include/asm/idprom.h b/arch/m68k/include/asm/idprom.h
new file mode 100644
index 00000000000..160616a89e0
--- /dev/null
+++ b/arch/m68k/include/asm/idprom.h
@@ -0,0 +1,27 @@
+#ifndef _M68K_IDPROM_H
+#define _M68K_IDPROM_H
+/*
+ * idprom.h: Macros and defines for idprom routines
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#include <linux/types.h>
+
+struct idprom {
+ u8 id_format; /* Format identifier (always 0x01) */
+ u8 id_machtype; /* Machine type */
+ u8 id_ethaddr[6]; /* Hardware ethernet address */
+ s32 id_date; /* Date of manufacture */
+ u32 id_sernum:24; /* Unique serial number */
+ u8 id_cksum; /* Checksum - xor of the data bytes */
+ u8 reserved[16];
+};
+
+extern struct idprom *idprom;
+extern void idprom_init(void);
+
+/* Sun3: in control space */
+#define SUN3_IDPROM_BASE 0x00000000
+
+#endif /* !(_M68K_IDPROM_H) */
diff --git a/arch/m68k/include/asm/intersil.h b/arch/m68k/include/asm/intersil.h
new file mode 100644
index 00000000000..f482902cac8
--- /dev/null
+++ b/arch/m68k/include/asm/intersil.h
@@ -0,0 +1,48 @@
+#ifndef _SUN3_INTERSIL_H
+#define _SUN3_INTERSIL_H
+/* bits 0 and 1 */
+#define INTERSIL_FREQ_32K 0x00
+#define INTERSIL_FREQ_1M 0x01
+#define INTERSIL_FREQ_2M 0x02
+#define INTERSIL_FREQ_4M 0x03
+
+/* bit 2 */
+#define INTERSIL_12H_MODE 0x00
+#define INTERSIL_24H_MODE 0x04
+
+/* bit 3 */
+#define INTERSIL_STOP 0x00
+#define INTERSIL_RUN 0x08
+
+/* bit 4 */
+#define INTERSIL_INT_ENABLE 0x10
+#define INTERSIL_INT_DISABLE 0x00
+
+/* bit 5 */
+#define INTERSIL_MODE_NORMAL 0x00
+#define INTERSIL_MODE_TEST 0x20
+
+#define INTERSIL_HZ_100_MASK 0x02
+
+struct intersil_dt {
+ unsigned char csec;
+ unsigned char hour;
+ unsigned char minute;
+ unsigned char second;
+ unsigned char month;
+ unsigned char day;
+ unsigned char year;
+ unsigned char weekday;
+};
+
+struct intersil_7170 {
+ struct intersil_dt counter;
+ struct intersil_dt alarm;
+ unsigned char int_reg;
+ unsigned char cmd_reg;
+};
+
+extern volatile char* clock_va;
+#define intersil_clock ((volatile struct intersil_7170 *) clock_va)
+#define intersil_clear() (void)intersil_clock->int_reg
+#endif
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
new file mode 100644
index 00000000000..c7210ba184e
--- /dev/null
+++ b/arch/m68k/include/asm/io.h
@@ -0,0 +1,5 @@
+#ifdef __uClinux__
+#include "io_no.h"
+#else
+#include "io_mm.h"
+#endif
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
new file mode 100644
index 00000000000..0fb3468000e
--- /dev/null
+++ b/arch/m68k/include/asm/io_mm.h
@@ -0,0 +1,336 @@
+/*
+ * linux/include/asm-m68k/io.h
+ *
+ * 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
+ * IO access
+ * - added Q40 support
+ * - added skeleton for GG-II and Amiga PCMCIA
+ * 2/3/01 RZ: - moved a few more defs into raw_io.h
+ *
+ * inX/outX should not be used by any driver unless it does
+ * ISA access. Other drivers should use function defined in raw_io.h
+ * or define its own macros on top of these.
+ *
+ * inX(),outX() are for ISA I/O
+ * isa_readX(),isa_writeX() are for ISA memory
+ */
+
+#ifndef _IO_H
+#define _IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <asm/raw_io.h>
+#include <asm/virtconvert.h>
+
+#include <asm-generic/iomap.h>
+
+#ifdef CONFIG_ATARI
+#include <asm/atarihw.h>
+#endif
+
+
+/*
+ * IO/MEM definitions for various ISA bridges
+ */
+
+
+#ifdef CONFIG_Q40
+
+#define q40_isa_io_base 0xff400000
+#define q40_isa_mem_base 0xff800000
+
+#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
+#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
+#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
+#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
+
+#define MULTI_ISA 0
+#endif /* Q40 */
+
+#ifdef CONFIG_AMIGA_PCMCIA
+#include <asm/amigayle.h>
+
+#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
+#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
+
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
+#else
+#undef MULTI_ISA
+#define MULTI_ISA 1
+#endif
+#endif /* AMIGA_PCMCIA */
+
+
+
+#ifdef CONFIG_ISA
+
+#if MULTI_ISA == 0
+#undef MULTI_ISA
+#endif
+
+#define ISA_TYPE_Q40 (1)
+#define ISA_TYPE_AG (2)
+
+#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_Q40
+#define ISA_SEX 0
+#endif
+#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_AG
+#define ISA_SEX 1
+#endif
+
+#ifdef MULTI_ISA
+extern int isa_type;
+extern int isa_sex;
+
+#define ISA_TYPE isa_type
+#define ISA_SEX isa_sex
+#endif
+
+/*
+ * define inline addr translation functions. Normally only one variant will
+ * be compiled in so the case statement will be optimised away
+ */
+
+static inline u8 __iomem *isa_itb(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u16 __iomem *isa_itw(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u32 __iomem *isa_itl(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr);
+#endif
+ default: return 0; /* avoid warnings, just in case */
+ }
+}
+static inline u8 __iomem *isa_mtb(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u8 __iomem *)addr;
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u16 __iomem *isa_mtw(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u16 __iomem *)addr;
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+
+
+#define isa_inb(port) in_8(isa_itb(port))
+#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
+#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
+#define isa_outb(val,port) out_8(isa_itb(port),(val))
+#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
+#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
+
+#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
+#define isa_readw(p) \
+ (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
+ : in_le16(isa_mtw((unsigned long)(p))))
+#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
+#define isa_writew(val,p) \
+ (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
+ : out_le16(isa_mtw((unsigned long)(p)),(val)))
+
+static inline void isa_delay(void)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: isa_outb(0,0x80); break;
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: break;
+#endif
+ default: break; /* avoid warnings */
+ }
+}
+
+#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
+#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
+#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
+#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
+#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
+#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
+
+#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
+#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_insw(port, buf, nr) \
+ (ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_outsw(port, buf, nr) \
+ (ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_insl(port, buf, nr) \
+ (ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
+ raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
+
+#define isa_outsl(port, buf, nr) \
+ (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
+ raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
+
+
+#define inb isa_inb
+#define inb_p isa_inb_p
+#define outb isa_outb
+#define outb_p isa_outb_p
+#define inw isa_inw
+#define inw_p isa_inw_p
+#define outw isa_outw
+#define outw_p isa_outw_p
+#define inl isa_inl
+#define inl_p isa_inl_p
+#define outl isa_outl
+#define outl_p isa_outl_p
+#define insb isa_insb
+#define insw isa_insw
+#define insl isa_insl
+#define outsb isa_outsb
+#define outsw isa_outsw
+#define outsl isa_outsl
+#define readb isa_readb
+#define readw isa_readw
+#define writeb isa_writeb
+#define writew isa_writew
+
+#else /* CONFIG_ISA */
+
+/*
+ * We need to define dummy functions for GENERIC_IOMAP support.
+ */
+#define inb(port) 0xff
+#define inb_p(port) 0xff
+#define outb(val,port) ((void)0)
+#define outb_p(val,port) ((void)0)
+#define inw(port) 0xffff
+#define inw_p(port) 0xffff
+#define outw(val,port) ((void)0)
+#define outw_p(val,port) ((void)0)
+#define inl(port) 0xffffffffUL
+#define inl_p(port) 0xffffffffUL
+#define outl(val,port) ((void)0)
+#define outl_p(val,port) ((void)0)
+
+#define insb(port,buf,nr) ((void)0)
+#define outsb(port,buf,nr) ((void)0)
+#define insw(port,buf,nr) ((void)0)
+#define outsw(port,buf,nr) ((void)0)
+#define insl(port,buf,nr) ((void)0)
+#define outsl(port,buf,nr) ((void)0)
+
+/*
+ * These should be valid on any ioremap()ed region
+ */
+#define readb(addr) in_8(addr)
+#define writeb(val,addr) out_8((addr),(val))
+#define readw(addr) in_le16(addr)
+#define writew(val,addr) out_le16((addr),(val))
+
+#endif /* CONFIG_ISA */
+
+#define readl(addr) in_le32(addr)
+#define writel(val,addr) out_le32((addr),(val))
+
+#define mmiowb()
+
+static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+ __builtin_memset((void __force *) addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+ __builtin_memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+ __builtin_memcpy((void __force *) dst, src, count);
+}
+
+#ifndef CONFIG_SUN3
+#define IO_SPACE_LIMIT 0xffff
+#else
+#define IO_SPACE_LIMIT 0x0fffffff
+#endif
+
+#endif /* __KERNEL__ */
+
+#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#endif /* _IO_H */
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
new file mode 100644
index 00000000000..353bf754a97
--- /dev/null
+++ b/arch/m68k/include/asm/io_no.h
@@ -0,0 +1,183 @@
+#ifndef _M68KNOMMU_IO_H
+#define _M68KNOMMU_IO_H
+
+#ifdef __KERNEL__
+
+#include <asm/virtconvert.h>
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesirable for some devices.
+ */
+
+/*
+ * swap functions are sometimes needed to interface little-endian hardware
+ */
+static inline unsigned short _swapw(volatile unsigned short v)
+{
+ return ((v << 8) | (v >> 8));
+}
+
+static inline unsigned int _swapl(volatile unsigned long v)
+{
+ return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
+}
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+static inline void io_outsb(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned char *ap = (volatile unsigned char *) addr;
+ unsigned char *bp = (unsigned char *) buf;
+ while (len--)
+ *ap = *bp++;
+}
+
+static inline void io_outsw(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned short *ap = (volatile unsigned short *) addr;
+ unsigned short *bp = (unsigned short *) buf;
+ while (len--)
+ *ap = _swapw(*bp++);
+}
+
+static inline void io_outsl(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned int *ap = (volatile unsigned int *) addr;
+ unsigned int *bp = (unsigned int *) buf;
+ while (len--)
+ *ap = _swapl(*bp++);
+}
+
+static inline void io_insb(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned char *ap = (volatile unsigned char *) addr;
+ unsigned char *bp = (unsigned char *) buf;
+ while (len--)
+ *bp++ = *ap;
+}
+
+static inline void io_insw(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned short *ap = (volatile unsigned short *) addr;
+ unsigned short *bp = (unsigned short *) buf;
+ while (len--)
+ *bp++ = _swapw(*ap);
+}
+
+static inline void io_insl(unsigned int addr, void *buf, int len)
+{
+ volatile unsigned int *ap = (volatile unsigned int *) addr;
+ unsigned int *bp = (unsigned int *) buf;
+ while (len--)
+ *bp++ = _swapl(*ap);
+}
+
+#define mmiowb()
+
+/*
+ * make the short names macros so specific devices
+ * can override them as required
+ */
+
+#define memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
+#define inb(addr) readb(addr)
+#define inw(addr) readw(addr)
+#define inl(addr) readl(addr)
+#define outb(x,addr) ((void) writeb(x,addr))
+#define outw(x,addr) ((void) writew(x,addr))
+#define outl(x,addr) ((void) writel(x,addr))
+
+#define inb_p(addr) inb(addr)
+#define inw_p(addr) inw(addr)
+#define inl_p(addr) inl(addr)
+#define outb_p(x,addr) outb(x,addr)
+#define outw_p(x,addr) outw(x,addr)
+#define outl_p(x,addr) outl(x,addr)
+
+#define outsb(a,b,l) io_outsb(a,b,l)
+#define outsw(a,b,l) io_outsw(a,b,l)
+#define outsl(a,b,l) io_outsl(a,b,l)
+
+#define insb(a,b,l) io_insb(a,b,l)
+#define insw(a,b,l) io_insw(a,b,l)
+#define insl(a,b,l) io_insl(a,b,l)
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING 0
+#define IOMAP_NOCACHE_SER 1
+#define IOMAP_NOCACHE_NONSER 2
+#define IOMAP_WRITETHROUGH 3
+
+static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
+{
+ return (void *) physaddr;
+}
+static inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+#define iounmap(addr) do { } while(0)
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#endif /* __KERNEL__ */
+
+#endif /* _M68KNOMMU_IO_H */
diff --git a/arch/m68k/include/asm/ioctl.h b/arch/m68k/include/asm/ioctl.h
new file mode 100644
index 00000000000..b279fe06dfe
--- /dev/null
+++ b/arch/m68k/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/m68k/include/asm/ioctls.h b/arch/m68k/include/asm/ioctls.h
new file mode 100644
index 00000000000..1332bb4ca5b
--- /dev/null
+++ b/arch/m68k/include/asm/ioctls.h
@@ -0,0 +1,8 @@
+#ifndef __ARCH_M68K_IOCTLS_H__
+#define __ARCH_M68K_IOCTLS_H__
+
+#define FIOQSIZE 0x545E
+
+#include <asm-generic/ioctls.h>
+
+#endif /* __ARCH_M68K_IOCTLS_H__ */
diff --git a/arch/m68k/include/asm/ipcbuf.h b/arch/m68k/include/asm/ipcbuf.h
new file mode 100644
index 00000000000..84c7e51cb6d
--- /dev/null
+++ b/arch/m68k/include/asm/ipcbuf.h
@@ -0,0 +1 @@
+#include <asm-generic/ipcbuf.h>
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h
new file mode 100644
index 00000000000..c1155f0e22c
--- /dev/null
+++ b/arch/m68k/include/asm/irq.h
@@ -0,0 +1,76 @@
+#ifndef _M68K_IRQ_H_
+#define _M68K_IRQ_H_
+
+/*
+ * This should be the same as the max(NUM_X_SOURCES) for all the
+ * different m68k hosts compiled into the kernel.
+ * Currently the Atari has 72 and the Amiga 24, but if both are
+ * supported in the kernel it is better to make room for 72.
+ */
+#if defined(CONFIG_COLDFIRE)
+#define NR_IRQS 256
+#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
+#define NR_IRQS 200
+#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
+#define NR_IRQS 72
+#elif defined(CONFIG_Q40)
+#define NR_IRQS 43
+#elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU)
+#define NR_IRQS 32
+#elif defined(CONFIG_APOLLO)
+#define NR_IRQS 24
+#elif defined(CONFIG_HP300)
+#define NR_IRQS 8
+#else
+#define NR_IRQS 0
+#endif
+
+#if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \
+ defined(CONFIG_M68040) || defined(CONFIG_M68060)
+
+/*
+ * Interrupt source definitions
+ * General interrupt sources are the level 1-7.
+ * Adding an interrupt service routine for one of these sources
+ * results in the addition of that routine to a chain of routines.
+ * Each one is called in succession. Each individual interrupt
+ * service routine should determine if the device associated with
+ * that routine requires service.
+ */
+
+#define IRQ_SPURIOUS 0
+
+#define IRQ_AUTO_1 1 /* level 1 interrupt */
+#define IRQ_AUTO_2 2 /* level 2 interrupt */
+#define IRQ_AUTO_3 3 /* level 3 interrupt */
+#define IRQ_AUTO_4 4 /* level 4 interrupt */
+#define IRQ_AUTO_5 5 /* level 5 interrupt */
+#define IRQ_AUTO_6 6 /* level 6 interrupt */
+#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
+
+#define IRQ_USER 8
+
+struct irq_data;
+struct irq_chip;
+struct irq_desc;
+extern unsigned int m68k_irq_startup(struct irq_data *data);
+extern unsigned int m68k_irq_startup_irq(unsigned int irq);
+extern void m68k_irq_shutdown(struct irq_data *data);
+extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int,
+ struct pt_regs *));
+extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
+extern void m68k_setup_irq_controller(struct irq_chip *,
+ void (*handle)(unsigned int irq,
+ struct irq_desc *desc),
+ unsigned int irq, unsigned int cnt);
+
+extern unsigned int irq_canonicalize(unsigned int irq);
+
+#else
+#define irq_canonicalize(irq) (irq)
+#endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */
+
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
+extern atomic_t irq_err_count;
+
+#endif /* _M68K_IRQ_H_ */
diff --git a/arch/m68k/include/asm/irq_regs.h b/arch/m68k/include/asm/irq_regs.h
new file mode 100644
index 00000000000..3dd9c0b7027
--- /dev/null
+++ b/arch/m68k/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/m68k/include/asm/irqflags.h b/arch/m68k/include/asm/irqflags.h
new file mode 100644
index 00000000000..7ef4115b8c4
--- /dev/null
+++ b/arch/m68k/include/asm/irqflags.h
@@ -0,0 +1,78 @@
+#ifndef _M68K_IRQFLAGS_H
+#define _M68K_IRQFLAGS_H
+
+#include <linux/types.h>
+#ifdef CONFIG_MMU
+#include <linux/hardirq.h>
+#endif
+#include <linux/preempt.h>
+#include <asm/thread_info.h>
+#include <asm/entry.h>
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ unsigned long flags;
+ asm volatile ("movew %%sr,%0" : "=d" (flags) : : "memory");
+ return flags;
+}
+
+static inline void arch_local_irq_disable(void)
+{
+#ifdef CONFIG_COLDFIRE
+ asm volatile (
+ "move %/sr,%%d0 \n\t"
+ "ori.l #0x0700,%%d0 \n\t"
+ "move %%d0,%/sr \n"
+ : /* no outputs */
+ :
+ : "cc", "%d0", "memory");
+#else
+ asm volatile ("oriw #0x0700,%%sr" : : : "memory");
+#endif
+}
+
+static inline void arch_local_irq_enable(void)
+{
+#if defined(CONFIG_COLDFIRE)
+ asm volatile (
+ "move %/sr,%%d0 \n\t"
+ "andi.l #0xf8ff,%%d0 \n\t"
+ "move %%d0,%/sr \n"
+ : /* no outputs */
+ :
+ : "cc", "%d0", "memory");
+#else
+# if defined(CONFIG_MMU)
+ if (MACH_IS_Q40 || !hardirq_count())
+# endif
+ asm volatile (
+ "andiw %0,%%sr"
+ :
+ : "i" (ALLOWINT)
+ : "memory");
+#endif
+}
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags = arch_local_save_flags();
+ arch_local_irq_disable();
+ return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ asm volatile ("movew %0,%%sr" : : "d" (flags) : "memory");
+}
+
+static inline bool arch_irqs_disabled_flags(unsigned long flags)
+{
+ return (flags & ~ALLOWINT) != 0;
+}
+
+static inline bool arch_irqs_disabled(void)
+{
+ return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+
+#endif /* _M68K_IRQFLAGS_H */
diff --git a/arch/m68k/include/asm/kdebug.h b/arch/m68k/include/asm/kdebug.h
new file mode 100644
index 00000000000..6ece1b03766
--- /dev/null
+++ b/arch/m68k/include/asm/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h
new file mode 100644
index 00000000000..3413cc1390e
--- /dev/null
+++ b/arch/m68k/include/asm/kmap_types.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_M68K_KMAP_TYPES_H
+#define __ASM_M68K_KMAP_TYPES_H
+
+#include <asm-generic/kmap_types.h>
+
+#endif /* __ASM_M68K_KMAP_TYPES_H */
diff --git a/arch/m68k/include/asm/linkage.h b/arch/m68k/include/asm/linkage.h
new file mode 100644
index 00000000000..5a822bb790f
--- /dev/null
+++ b/arch/m68k/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 4
+#define __ALIGN_STR ".align 4"
+
+#endif
diff --git a/arch/m68k/include/asm/local.h b/arch/m68k/include/asm/local.h
new file mode 100644
index 00000000000..6c259263e1f
--- /dev/null
+++ b/arch/m68k/include/asm/local.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_M68K_LOCAL_H
+#define _ASM_M68K_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* _ASM_M68K_LOCAL_H */
diff --git a/arch/m68k/include/asm/local64.h b/arch/m68k/include/asm/local64.h
new file mode 100644
index 00000000000..36c93b5cc23
--- /dev/null
+++ b/arch/m68k/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
new file mode 100644
index 00000000000..9015eadd5c0
--- /dev/null
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -0,0 +1,147 @@
+/****************************************************************************/
+
+/*
+ * m5206sim.h -- ColdFire 5206 System Integration Module support.
+ *
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef m5206sim_h
+#define m5206sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5206)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5206 SIM register set addresses.
+ */
+#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
+#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
+#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
+#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
+#ifdef CONFIG_M5206e
+#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
+#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
+#endif
+
+#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
+#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
+
+#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
+
+#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
+
+#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
+#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
+#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
+
+#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
+#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
+#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
+#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
+#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
+#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
+#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
+#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
+#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
+#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
+#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
+#define MCFSIM_DMCR 0xc6 /* Default control */
+
+#ifdef CONFIG_M5206e
+#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
+#else
+#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
+#endif
+
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
+
+#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
+#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
+
+#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
+
+#if defined(CONFIG_NETtel)
+#define MCFUART_BASE1 0x180 /* Base address of UART1 */
+#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+#else
+#define MCFUART_BASE1 0x140 /* Base address of UART1 */
+#define MCFUART_BASE2 0x180 /* Base address of UART2 */
+#endif
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+
+/*
+ * Generic GPIO
+ */
+#define MCFGPIO_PIN_MAX 8
+#define MCFGPIO_IRQ_VECBASE -1
+#define MCFGPIO_IRQ_MAX -1
+
+/*
+ * Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#ifdef CONFIG_M5206e
+#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
+ /* Clear to select T0 input */
+#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
+ /* Clear to select T0 output */
+#endif
+
+/*
+ * Some symbol defines for the Interrupt Control Register
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
+#ifdef CONFIG_M5206e
+#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
+#endif
+
+/****************************************************************************/
+#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
new file mode 100644
index 00000000000..eda62de7e60
--- /dev/null
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -0,0 +1,167 @@
+/****************************************************************************/
+
+/*
+ * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
+ *
+ * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
+ */
+
+/****************************************************************************/
+#ifndef m520xsim_h
+#define m520xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m520x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 520x SIM register set addresses.
+ */
+#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
+#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+/*
+ * The common interrupt controller code just wants to know the absolute
+ * address to the SIMR and CIMR registers (not offsets into IPSBAR).
+ * The 520x family only has a single INTC unit.
+ */
+#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
+#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC1_SIMR (0)
+#define MCFINTC1_CIMR (0)
+#define MCFINTC1_ICR0 (0)
+
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 26 /* Interrupt number for UART0 */
+#define MCFINT_UART1 27 /* Interrupt number for UART1 */
+#define MCFINT_UART2 28 /* Interrupt number for UART2 */
+#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
+
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
+#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
+#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
+#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
+#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
+#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
+
+/*
+ * EPORT and GPIO registers.
+ */
+#define MCFEPORT_EPPAR 0xFC088000
+#define MCFEPORT_EPDDR 0xFC088002
+#define MCFEPORT_EPIER 0xFC088003
+#define MCFEPORT_EPDR 0xFC088004
+#define MCFEPORT_EPPDR 0xFC088005
+#define MCFEPORT_EPFR 0xFC088006
+
+#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
+#define MCFGPIO_PODR_BE 0xFC0A4001
+#define MCFGPIO_PODR_CS 0xFC0A4002
+#define MCFGPIO_PODR_FECI2C 0xFC0A4003
+#define MCFGPIO_PODR_QSPI 0xFC0A4004
+#define MCFGPIO_PODR_TIMER 0xFC0A4005
+#define MCFGPIO_PODR_UART 0xFC0A4006
+#define MCFGPIO_PODR_FECH 0xFC0A4007
+#define MCFGPIO_PODR_FECL 0xFC0A4008
+
+#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
+#define MCFGPIO_PDDR_BE 0xFC0A400D
+#define MCFGPIO_PDDR_CS 0xFC0A400E
+#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
+#define MCFGPIO_PDDR_QSPI 0xFC0A4010
+#define MCFGPIO_PDDR_TIMER 0xFC0A4011
+#define MCFGPIO_PDDR_UART 0xFC0A4012
+#define MCFGPIO_PDDR_FECH 0xFC0A4013
+#define MCFGPIO_PDDR_FECL 0xFC0A4014
+
+#define MCFGPIO_PPDSDR_CS 0xFC0A401A
+#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B
+#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C
+#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D
+#define MCFGPIO_PPDSDR_UART 0xFC0A401E
+#define MCFGPIO_PPDSDR_FECH 0xFC0A401F
+#define MCFGPIO_PPDSDR_FECL 0xFC0A4020
+
+#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
+#define MCFGPIO_PCLRR_BE 0xFC0A4025
+#define MCFGPIO_PCLRR_CS 0xFC0A4026
+#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
+#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
+#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
+#define MCFGPIO_PCLRR_UART 0xFC0A402A
+#define MCFGPIO_PCLRR_FECH 0xFC0A402B
+#define MCFGPIO_PCLRR_FECL 0xFC0A402C
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_CS
+#define MCFGPIO_PDDR MCFGPIO_PDDR_CS
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS
+
+#define MCFGPIO_PIN_MAX 80
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+#define MCF_GPIO_PAR_UART 0xFC0A4036
+#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
+#define MCF_GPIO_PAR_QSPI 0xFC0A4034
+#define MCF_GPIO_PAR_FEC 0xFC0A4038
+
+#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
+
+#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
+
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
+
+/*
+ * PIT timer module.
+ */
+#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
+#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
+#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
+
+/*
+ * FEC module.
+ */
+#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
+#define MCFFEC_SIZE 0x800 /* Register set size */
+
+/*
+ * Reset Control Unit.
+ */
+#define MCF_RCR 0xFC0A0000
+#define MCF_RSR 0xFC0A0001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/****************************************************************************/
+#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
new file mode 100644
index 00000000000..6235921eca4
--- /dev/null
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -0,0 +1,177 @@
+/****************************************************************************/
+
+/*
+ * m523xsim.h -- ColdFire 523x System Integration Module support.
+ *
+ * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m523xsim_h
+#define m523xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m523x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 523x SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR 0x110000
+#define MCF_RSR 0x110001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE 0x800
+
+/*
+ * GPIO module.
+ */
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
+#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
+#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
+#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
+
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
+#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
+#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
+
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
+#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
+
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
+#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
+#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+
+#define MCFGPIO_PIN_MAX 107
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*
+ * Pin Assignment
+*/
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
+/****************************************************************************/
+#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
new file mode 100644
index 00000000000..805714ca8d7
--- /dev/null
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -0,0 +1,255 @@
+/****************************************************************************/
+
+/*
+ * m5249sim.h -- ColdFire 5249 System Integration Module support.
+ *
+ * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m5249sim_h
+#define m5249sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5249)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * The 5249 has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2 0x80000000
+
+/*
+ * Define the 5249 SIM register set addresses.
+ */
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
+#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
+#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
+#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
+#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
+#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
+#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
+#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
+
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
+#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+
+/*
+ * General purpose IO registers (in MBAR2).
+ */
+#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
+#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
+#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
+#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
+#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
+#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
+#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
+#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
+
+#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
+#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
+#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
+
+#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */
+#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */
+#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */
+#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */
+#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */
+#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */
+#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */
+#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */
+
+#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */
+
+#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
+
+/*
+ * Define the base interrupt for the second interrupt controller.
+ * We set it to 128, out of the way of the base interrupts, and plenty
+ * of room for its 64 interrupts.
+ */
+#define MCFINTC2_VECBASE 128
+
+#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
+#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
+#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
+#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
+#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
+#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
+#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
+#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 64
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+
+/****************************************************************************/
+
+#ifdef __ASSEMBLER__
+
+/*
+ * The M5249C3 board needs a little help getting all its SIM devices
+ * initialized at kernel start time. dBUG doesn't set much up, so
+ * we need to do it manually.
+ */
+.macro m5249c3_setup
+ /*
+ * Set MBAR1 and MBAR2, just incase they are not set.
+ */
+ movel #0x10000001,%a0
+ movec %a0,%MBAR /* map MBAR region */
+ subql #1,%a0 /* get MBAR address in a0 */
+
+ movel #0x80000001,%a1
+ movec %a1,#3086 /* map MBAR2 region */
+ subql #1,%a1 /* get MBAR2 address in a1 */
+
+ /*
+ * Move secondary interrupts to their base (128).
+ */
+ moveb #MCFINTC2_VECBASE,%d0
+ moveb %d0,0x16b(%a1) /* interrupt base register */
+
+ /*
+ * Work around broken CSMR0/DRAM vector problem.
+ */
+ movel #0x001F0021,%d0 /* disable C/I bit */
+ movel %d0,0x84(%a0) /* set CSMR0 */
+
+ /*
+ * Disable the PLL firstly. (Who knows what state it is
+ * in here!).
+ */
+ movel 0x180(%a1),%d0 /* get current PLL value */
+ andl #0xfffffffe,%d0 /* PLL bypass first */
+ movel %d0,0x180(%a1) /* set PLL register */
+ nop
+
+#if CONFIG_CLOCK_FREQ == 140000000
+ /*
+ * Set initial clock frequency. This assumes M5249C3 board
+ * is fitted with 11.2896MHz crystal. It will program the
+ * PLL for 140MHz. Lets go fast :-)
+ */
+ movel #0x125a40f0,%d0 /* set for 140MHz */
+ movel %d0,0x180(%a1) /* set PLL register */
+ orl #0x1,%d0
+ movel %d0,0x180(%a1) /* set PLL register */
+#endif
+
+ /*
+ * Setup CS1 for ethernet controller.
+ * (Setup as per M5249C3 doco).
+ */
+ movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
+ movel %d0,0x8c(%a0)
+ movel #0x001f0021,%d0 /* CS1 size of 1Mb */
+ movel %d0,0x90(%a0)
+ movew #0x0080,%d0 /* CS1 = 16bit port, AA */
+ movew %d0,0x96(%a0)
+
+ /*
+ * Setup CS2 for IDE interface.
+ */
+ movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
+ movel %d0,0x98(%a0)
+ movel #0x001f0001,%d0 /* CS2 size of 1MB */
+ movel %d0,0x9c(%a0)
+ movew #0x0080,%d0 /* CS2 = 16bit, TA */
+ movew %d0,0xa2(%a0)
+
+ movel #0x00107000,%d0 /* IDEconfig1 */
+ movel %d0,0x18c(%a1)
+ movel #0x000c0400,%d0 /* IDEconfig2 */
+ movel %d0,0x190(%a1)
+
+ movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
+ orl %d0,0xc(%a1) /* function GPIO19 */
+ orl %d0,0x8(%a1) /* enable GPIO19 as output */
+ orl %d0,0x4(%a1) /* de-assert IDE reset */
+.endm
+
+#define PLATFORM_SETUP m5249c3_setup
+
+#endif /* __ASSEMBLER__ */
+
+/****************************************************************************/
+#endif /* m5249sim_h */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
new file mode 100644
index 00000000000..759c2b07a99
--- /dev/null
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -0,0 +1,136 @@
+/****************************************************************************/
+
+/*
+ * m5272sim.h -- ColdFire 5272 System Integration Module support.
+ *
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef m5272sim_h
+#define m5272sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5272)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5272 SIM register set addresses.
+ */
+#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
+#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
+#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
+#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
+#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
+
+#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
+
+#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
+#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
+#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
+#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
+
+#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
+#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
+#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
+#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
+
+#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
+#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
+#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
+#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
+#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
+#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
+#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
+#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
+#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
+#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
+#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
+#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
+#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
+#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
+#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
+#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
+
+#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
+#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
+#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
+
+#define MCFUART_BASE1 0x100 /* Base address of UART1 */
+#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+
+#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
+#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
+#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
+#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
+#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
+#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
+#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
+#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
+#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
+
+#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
+
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
+#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
+#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCFINT_VECBASE 64 /* Base of interrupts */
+#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
+#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
+#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
+#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
+#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
+#define MCF_IRQ_TIMER1 69 /* Timer 1 */
+#define MCF_IRQ_TIMER2 70 /* Timer 2 */
+#define MCF_IRQ_TIMER3 71 /* Timer 3 */
+#define MCF_IRQ_TIMER4 72 /* Timer 4 */
+#define MCF_IRQ_UART1 73 /* UART 1 */
+#define MCF_IRQ_UART2 74 /* UART 2 */
+#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
+#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
+#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
+#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
+#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
+#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
+#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
+#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
+#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
+#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
+#define MCF_IRQ_DMA 85 /* DMA Controller */
+#define MCF_IRQ_ERX 86 /* Ethernet Receiver */
+#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */
+#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */
+#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
+#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
+#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
+#define MCF_IRQ_SWTO 92 /* Software Watchdog */
+#define MCFINT_VECMAX 95 /* Maxmum interrupt */
+
+#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
+#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 48
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+/****************************************************************************/
+#endif /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
new file mode 100644
index 00000000000..758810ef91e
--- /dev/null
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -0,0 +1,295 @@
+/****************************************************************************/
+
+/*
+ * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
+ *
+ * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m527xsim_h
+#define m527xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m527x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5270/5271 SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+
+/*
+ * SDRAM configuration registers.
+ */
+#ifdef CONFIG_M5271
+#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
+#endif
+#ifdef CONFIG_M5275
+#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
+#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
+#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
+#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
+#endif
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0 0x800
+#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
+#define MCFFEC_SIZE1 0x800
+
+#ifdef CONFIG_M5271
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
+#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
+#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
+
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
+#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
+
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
+
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
+#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+
+#define MCFGPIO_PIN_MAX 100
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
+#endif
+
+#ifdef CONFIG_M5275
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E)
+#define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F)
+#define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
+
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
+#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
+#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
+#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
+
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
+#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
+#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
+#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
+
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
+#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
+#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
+#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
+#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
+#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
+#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
+#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
+#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
+#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
+
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
+
+#define MCFGPIO_PIN_MAX 148
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
+#endif
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
+
+/*
+ * GPIO pins setups to enable the UARTs.
+ */
+#ifdef CONFIG_M5271
+#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x0ff0
+#define UART2_ENABLE_MASK 0x3000
+#endif
+#ifdef CONFIG_M5275
+#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+#endif
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR 0x110000
+#define MCF_RSR 0x110001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/****************************************************************************/
+#endif /* m527xsim_h */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
new file mode 100644
index 00000000000..d798bd5df56
--- /dev/null
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -0,0 +1,288 @@
+/****************************************************************************/
+
+/*
+ * m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
+ *
+ * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m528xsim_h
+#define m528xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m528x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5280/5282 SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
+
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE 0x800
+
+/*
+ * GPIO registers
+ */
+#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
+#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001)
+#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002)
+#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003)
+#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004)
+#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005)
+#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006)
+#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007)
+#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008)
+#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009)
+#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A)
+#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B)
+#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C)
+#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D)
+#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E)
+#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F)
+#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010)
+#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011)
+
+#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014)
+#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015)
+#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016)
+#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017)
+#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018)
+#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019)
+#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A)
+#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B)
+#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C)
+#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D)
+#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E)
+#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F)
+#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020)
+#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021)
+#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022)
+#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023)
+#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024)
+#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025)
+
+#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028)
+#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029)
+#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A)
+#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B)
+#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C)
+#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D)
+#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E)
+#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F)
+#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030)
+#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031)
+#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032)
+#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033)
+#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034)
+#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035)
+#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036)
+#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037)
+#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038)
+#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039)
+
+#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028)
+#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029)
+#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A)
+#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B)
+#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C)
+#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D)
+#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E)
+#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F)
+#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030)
+#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031)
+#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032)
+#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033)
+#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034)
+#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035)
+#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036)
+#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037)
+#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038)
+#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039)
+
+#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C)
+#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D)
+#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E)
+#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F)
+#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040)
+#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041)
+#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042)
+#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043)
+#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044)
+#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045)
+#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046)
+#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047)
+#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048)
+#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049)
+#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A)
+#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B)
+#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C)
+#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D)
+
+#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
+#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
+#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
+#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
+#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
+#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
+#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
+#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
+#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
+#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
+#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
+
+/*
+ * Edge Port registers
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
+
+/*
+ * Queued ADC registers
+ */
+#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
+#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
+#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
+#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
+
+/*
+ * General Purpose Timers registers
+ */
+#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
+#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
+#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
+#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
+/*
+ *
+ * definitions for generic gpio support
+ *
+ */
+#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */
+#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */
+#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */
+#define MCFGPIO_SETR MCFGPIO_SETA /* set output */
+#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */
+
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX 180
+
+
+/*
+ * Derek Cheung - 6 Feb 2005
+ * add I2C and QSPI register definition using Freescale's MCF5282
+ */
+/* set Port AS pin for I2C or UART */
+#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
+
+/* Port UA Pin Assignment Register (8 Bit) */
+#define MCF5282_GPIO_PUAPAR 0x10005C
+
+/* Interrupt Mask Register Register Low */
+#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
+/* Interrupt Control Register 7 */
+#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
+
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR 0x110000
+#define MCF_RSR 0x110001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*********************************************************************
+*
+* Inter-IC (I2C) Module
+*
+*********************************************************************/
+/* Read/Write access macros for general use */
+#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
+#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
+#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
+#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
+#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
+
+/* Bit level definitions and macros */
+#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
+
+#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
+
+#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
+#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
+#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
+#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
+#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
+#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
+
+#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
+#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
+#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
+#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
+#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
+#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
+#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
+
+
+#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h
new file mode 100644
index 00000000000..abc391a9ae8
--- /dev/null
+++ b/arch/m68k/include/asm/m52xxacr.h
@@ -0,0 +1,94 @@
+/****************************************************************************/
+
+/*
+ * m52xxacr.h -- ColdFire version 2 core cache support
+ *
+ * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m52xxacr_h
+#define m52xxacr_h
+/****************************************************************************/
+
+/*
+ * All varients of the ColdFire using version 2 cores have a similar
+ * cache setup. Although not absolutely identical the cache register
+ * definitions are compatible for all of them. Mostly they support a
+ * configurable cache memory that can be instruction only, data only,
+ * or split instruction and data. The exception is the very old version 2
+ * core based parts, like the 5206(e), 5249 and 5272, which are instruction
+ * cache only. Cache size varies from 2k up to 16k.
+ */
+
+/*
+ * Define the Cache Control register flags.
+ */
+#define CACR_CENB 0x80000000 /* Enable cache */
+#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
+#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
+#define CACR_CINV 0x01000000 /* Invalidate cache */
+#define CACR_DISI 0x00800000 /* Disable instruction cache */
+#define CACR_DISD 0x00400000 /* Disable data cache */
+#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
+#define CACR_INVD 0x00100000 /* Invalidate data cache */
+#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
+#define CACR_DCM 0x00000200 /* Default cache mode */
+#define CACR_DBWE 0x00000100 /* Buffered write enable */
+#define CACR_DWP 0x00000020 /* Write protection */
+#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
+
+/*
+ * Define the Access Control register flags.
+ */
+#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
+#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
+#define ACR_ENABLE 0x00008000 /* Enable this ACR */
+#define ACR_USER 0x00000000 /* Allow only user accesses */
+#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
+#define ACR_ANY 0x00004000 /* Allow any access type */
+#define ACR_CENB 0x00000000 /* Caching of region enabled */
+#define ACR_CDIS 0x00000040 /* Caching of region disabled */
+#define ACR_BWE 0x00000020 /* Write buffer enabled */
+#define ACR_WPROTECT 0x00000004 /* Write protect region */
+
+/*
+ * Set the cache controller settings we will use. On the cores that support
+ * a split cache configuration we allow all the combinations at Kconfig
+ * time. For those cores that only have an instruction cache we just set
+ * that as on.
+ */
+#if defined(CONFIG_CACHE_I)
+#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
+#define CACHE_INVTYPEI 0
+#elif defined(CONFIG_CACHE_D)
+#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
+#define CACHE_INVTYPED 0
+#elif defined(CONFIG_CACHE_BOTH)
+#define CACHE_TYPE CACR_EUSP
+#define CACHE_INVTYPEI CACR_INVI
+#define CACHE_INVTYPED CACR_INVD
+#else
+/* This is the instruction cache only devices (no split cache, no eusp) */
+#define CACHE_TYPE 0
+#define CACHE_INVTYPEI 0
+#endif
+
+#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
+#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
+
+#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
+#if defined(CACHE_INVTYPEI)
+#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
+#endif
+#if defined(CACHE_INVTYPED)
+#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
+#endif
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
+#define ACR1_MODE 0
+
+/****************************************************************************/
+#endif /* m52xxsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
new file mode 100644
index 00000000000..8f8609fcc9b
--- /dev/null
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -0,0 +1,181 @@
+/****************************************************************************/
+
+/*
+ * m5307sim.h -- ColdFire 5307 System Integration Module support.
+ *
+ * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
+ * (C) Copyright 1999, Lineo (www.lineo.com)
+ *
+ * Modified by David W. Miller for the MCF5307 Eval Board.
+ */
+
+/****************************************************************************/
+#ifndef m5307sim_h
+#define m5307sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5307)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m53xxacr.h>
+
+/*
+ * Define the 5307 SIM register set addresses.
+ */
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
+#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
+#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
+#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
+#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
+#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
+#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
+#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
+#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
+
+#ifdef CONFIG_OLDMASK
+#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
+#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
+#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
+#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
+#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
+#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
+#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
+#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
+#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
+#else
+#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
+#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
+#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
+#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
+#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
+#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
+#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
+#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
+#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
+#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
+#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
+#endif /* CONFIG_OLDMASK */
+
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
+
+#define MCFSIM_PADDR (MCF_MBAR + 0x244)
+#define MCFSIM_PADAT (MCF_MBAR + 0x248)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
+ * UART module.
+ */
+#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
+#define MCFUART_BASE1 0x200 /* Base address of UART1 */
+#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
+#else
+#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
+#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#endif
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 16
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+
+
+/* Definition offset address for CS2-7 -- old mask 5307 */
+
+#define MCF5307_CS2 (0x400000)
+#define MCF5307_CS3 (0x600000)
+#define MCF5307_CS4 (0x800000)
+#define MCF5307_CS5 (0xA00000)
+#define MCF5307_CS6 (0xC00000)
+#define MCF5307_CS7 (0xE00000)
+
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+
+
+/*
+ * Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
+ /* Clear to select par I/O */
+#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
+ /* Clear to select par I/O */
+
+/*
+ * Defines for the IRQPAR Register
+ */
+#define IRQ5_LEVEL4 0x80
+#define IRQ3_LEVEL6 0x40
+#define IRQ1_LEVEL2 0x20
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+
+/****************************************************************************/
+#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
new file mode 100644
index 00000000000..ba4cc784f57
--- /dev/null
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -0,0 +1,2234 @@
+/****************************************************************************/
+
+/*
+ * m532xsim.h -- ColdFire 5329 registers
+ */
+
+/****************************************************************************/
+#ifndef m532xsim_h
+#define m532xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m532x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 3)
+
+#include <asm/m53xxacr.h>
+
+#define MCF_REG32(x) (*(volatile unsigned long *)(x))
+#define MCF_REG16(x) (*(volatile unsigned short *)(x))
+#define MCF_REG08(x) (*(volatile unsigned char *)(x))
+
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 26 /* Interrupt number for UART0 */
+#define MCFINT_UART1 27 /* Interrupt number for UART1 */
+#define MCFINT_UART2 28 /* Interrupt number for UART2 */
+#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+
+#define MCF_WTM_WCR MCF_REG16(0xFC098000)
+
+/*
+ * Define the 532x SIM register set addresses.
+ */
+#define MCFSIM_IPRL 0xFC048004
+#define MCFSIM_IPRH 0xFC048000
+#define MCFSIM_IPR MCFSIM_IPRL
+#define MCFSIM_IMRL 0xFC04800C
+#define MCFSIM_IMRH 0xFC048008
+#define MCFSIM_IMR MCFSIM_IMRL
+#define MCFSIM_ICR0 0xFC048040
+#define MCFSIM_ICR1 0xFC048041
+#define MCFSIM_ICR2 0xFC048042
+#define MCFSIM_ICR3 0xFC048043
+#define MCFSIM_ICR4 0xFC048044
+#define MCFSIM_ICR5 0xFC048045
+#define MCFSIM_ICR6 0xFC048046
+#define MCFSIM_ICR7 0xFC048047
+#define MCFSIM_ICR8 0xFC048048
+#define MCFSIM_ICR9 0xFC048049
+#define MCFSIM_ICR10 0xFC04804A
+#define MCFSIM_ICR11 0xFC04804B
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+
+
+#define MCFINTC0_SIMR 0xFC04801C
+#define MCFINTC0_CIMR 0xFC04801D
+#define MCFINTC0_ICR0 0xFC048040
+#define MCFINTC1_SIMR 0xFC04C01C
+#define MCFINTC1_CIMR 0xFC04C01D
+#define MCFINTC1_ICR0 0xFC04C040
+
+#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
+#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
+#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
+#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
+#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
+#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
+
+/*********************************************************************
+ *
+ * Reset Controller Module
+ *
+ *********************************************************************/
+
+#define MCF_RCR 0xFC0A0000
+#define MCF_RSR 0xFC0A0001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*********************************************************************
+ *
+ * Inter-IC (I2C) Module
+ *
+ *********************************************************************/
+
+/* Read/Write access macros for general use */
+#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
+#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
+#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
+#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
+#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
+
+/* Bit level definitions and macros */
+#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
+
+#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
+
+#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
+#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
+#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
+#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
+#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
+#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
+
+#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
+#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
+#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
+#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
+#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
+#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
+#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
+
+#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
+
+
+/*
+ * The M5329EVB board needs a help getting its devices initialized
+ * at kernel start time if dBUG doesn't set it up (for example
+ * it is not used), so we need to do it manually.
+ */
+#ifdef __ASSEMBLER__
+.macro m5329EVB_setup
+ movel #0xFC098000, %a7
+ movel #0x0, (%a7)
+#define CORE_SRAM 0x80000000
+#define CORE_SRAM_SIZE 0x8000
+ movel #CORE_SRAM, %d0
+ addl #0x221, %d0
+ movec %d0,%RAMBAR1
+ movel #CORE_SRAM, %sp
+ addl #CORE_SRAM_SIZE, %sp
+ jsr sysinit
+.endm
+#define PLATFORM_SETUP m5329EVB_setup
+
+#endif /* __ASSEMBLER__ */
+
+/*********************************************************************
+ *
+ * Chip Configuration Module (CCM)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
+#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
+#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
+#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
+#define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
+#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
+#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
+
+/* Bit definitions and macros for MCF_CCM_CCR */
+#define MCF_CCM_CCR_RESERVED (0x0001)
+#define MCF_CCM_CCR_PLL_MODE (0x0003)
+#define MCF_CCM_CCR_OSC_MODE (0x0005)
+#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define MCF_CCM_CCR_LOAD (0x0021)
+#define MCF_CCM_CCR_LIMP (0x0041)
+#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
+
+/* Bit definitions and macros for MCF_CCM_RCON */
+#define MCF_CCM_RCON_RESERVED (0x0001)
+#define MCF_CCM_RCON_PLL_MODE (0x0003)
+#define MCF_CCM_RCON_OSC_MODE (0x0005)
+#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define MCF_CCM_RCON_LOAD (0x0021)
+#define MCF_CCM_RCON_LIMP (0x0041)
+#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
+
+/* Bit definitions and macros for MCF_CCM_CIR */
+#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
+#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+
+/* Bit definitions and macros for MCF_CCM_MISCCR */
+#define MCF_CCM_MISCCR_USBSRC (0x0001)
+#define MCF_CCM_MISCCR_USBDIV (0x0002)
+#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
+#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
+#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
+#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
+#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
+#define MCF_CCM_MISCCR_LIMP (0x1000)
+#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
+
+/* Bit definitions and macros for MCF_CCM_CDR */
+#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
+#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
+
+/* Bit definitions and macros for MCF_CCM_UHCSR */
+#define MCF_CCM_UHCSR_XPDE (0x0001)
+#define MCF_CCM_UHCSR_UHMIE (0x0002)
+#define MCF_CCM_UHCSR_WKUP (0x0004)
+#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_CCM_UOCSR */
+#define MCF_CCM_UOCSR_XPDE (0x0001)
+#define MCF_CCM_UOCSR_UOMIE (0x0002)
+#define MCF_CCM_UOCSR_WKUP (0x0004)
+#define MCF_CCM_UOCSR_PWRFLT (0x0008)
+#define MCF_CCM_UOCSR_SEND (0x0010)
+#define MCF_CCM_UOCSR_VVLD (0x0020)
+#define MCF_CCM_UOCSR_BVLD (0x0040)
+#define MCF_CCM_UOCSR_AVLD (0x0080)
+#define MCF_CCM_UOCSR_DPPU (0x0100)
+#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
+#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
+#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
+#define MCF_CCM_UOCSR_DMPD (0x1000)
+#define MCF_CCM_UOCSR_DPPD (0x2000)
+#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
+
+/*********************************************************************
+ *
+ * DMA Timers (DTIM)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
+#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
+#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
+#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
+#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
+#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
+#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
+#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
+#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
+#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
+#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
+#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
+#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
+#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
+#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
+#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
+#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
+#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
+#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
+#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
+#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
+#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
+#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
+#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
+#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
+#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
+#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
+#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
+#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
+#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
+
+/* Bit definitions and macros for MCF_DTIM_DTMR */
+#define MCF_DTIM_DTMR_RST (0x0001)
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
+#define MCF_DTIM_DTMR_FRR (0x0008)
+#define MCF_DTIM_DTMR_ORRI (0x0010)
+#define MCF_DTIM_DTMR_OM (0x0020)
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
+#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
+#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
+#define MCF_DTIM_DTMR_CE_FALL (0x0080)
+#define MCF_DTIM_DTMR_CE_RISE (0x0040)
+#define MCF_DTIM_DTMR_CE_NONE (0x0000)
+#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
+#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
+
+/* Bit definitions and macros for MCF_DTIM_DTXMR */
+#define MCF_DTIM_DTXMR_MODE16 (0x01)
+#define MCF_DTIM_DTXMR_DMAEN (0x80)
+
+/* Bit definitions and macros for MCF_DTIM_DTER */
+#define MCF_DTIM_DTER_CAP (0x01)
+#define MCF_DTIM_DTER_REF (0x02)
+
+/* Bit definitions and macros for MCF_DTIM_DTRR */
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DTIM_DTCR */
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DTIM_DTCN */
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
+
+/*********************************************************************
+ *
+ * FlexBus Chip Selects (FBCS)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
+#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
+#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
+#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
+#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
+#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
+#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
+#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
+#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
+#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
+#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
+#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
+#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
+#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
+#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
+#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
+#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
+#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
+#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
+#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
+#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V (0x00000001)
+#define MCF_FBCS_CSMR_WP (0x00000100)
+#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
+#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
+#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
+#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
+#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
+#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
+#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
+#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
+#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
+#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
+#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW (0x00000008)
+#define MCF_FBCS_CSCR_BSTR (0x00000010)
+#define MCF_FBCS_CSCR_BEM (0x00000020)
+#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
+#define MCF_FBCS_CSCR_AA (0x00000100)
+#define MCF_FBCS_CSCR_SBM (0x00000200)
+#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
+#define MCF_FBCS_CSCR_SWSEN (0x00800000)
+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
+#define MCF_FBCS_CSCR_PS_8 (0x0040)
+#define MCF_FBCS_CSCR_PS_16 (0x0080)
+#define MCF_FBCS_CSCR_PS_32 (0x0000)
+
+/*********************************************************************
+ *
+ * General Purpose I/O (GPIO)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCFGPIO_PODR_FECH (0xFC0A4000)
+#define MCFGPIO_PODR_FECL (0xFC0A4001)
+#define MCFGPIO_PODR_SSI (0xFC0A4002)
+#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
+#define MCFGPIO_PODR_BE (0xFC0A4004)
+#define MCFGPIO_PODR_CS (0xFC0A4005)
+#define MCFGPIO_PODR_PWM (0xFC0A4006)
+#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
+#define MCFGPIO_PODR_UART (0xFC0A4009)
+#define MCFGPIO_PODR_QSPI (0xFC0A400A)
+#define MCFGPIO_PODR_TIMER (0xFC0A400B)
+#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
+#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
+#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
+#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
+#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
+#define MCFGPIO_PDDR_FECH (0xFC0A4014)
+#define MCFGPIO_PDDR_FECL (0xFC0A4015)
+#define MCFGPIO_PDDR_SSI (0xFC0A4016)
+#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
+#define MCFGPIO_PDDR_BE (0xFC0A4018)
+#define MCFGPIO_PDDR_CS (0xFC0A4019)
+#define MCFGPIO_PDDR_PWM (0xFC0A401A)
+#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
+#define MCFGPIO_PDDR_UART (0xFC0A401C)
+#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
+#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
+#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
+#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
+#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
+#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
+#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
+#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
+#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
+#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
+#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
+#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
+#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
+#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
+#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
+#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
+#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
+#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
+#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
+#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
+#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
+#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
+#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
+#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
+#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
+#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
+#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
+#define MCFGPIO_PCLRR_BE (0xFC0A4040)
+#define MCFGPIO_PCLRR_CS (0xFC0A4041)
+#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
+#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
+#define MCFGPIO_PCLRR_UART (0xFC0A4045)
+#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
+#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
+#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
+#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
+#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
+#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
+#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
+#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
+#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
+#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
+#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053)
+#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054)
+#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055)
+#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056)
+#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058)
+#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A)
+#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
+#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D)
+#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E)
+#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060)
+#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064)
+#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065)
+#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068)
+#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069)
+#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A)
+#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
+#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
+#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D)
+#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E)
+#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F)
+#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070)
+#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071)
+#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
+#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
+#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
+#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
+#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
+#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
+#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
+#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
+#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
+#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
+#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
+#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
+#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
+#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
+#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
+#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
+#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
+#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
+#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
+#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
+#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
+#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
+#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BE */
+#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
+#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
+#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
+#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_CS */
+#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
+#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
+#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
+#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
+#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
+#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
+#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
+#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
+#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_UART */
+#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
+#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
+#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
+#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
+#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
+#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
+#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
+#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
+#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
+#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
+#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
+#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
+#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
+#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
+#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
+#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
+#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
+#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
+#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
+#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
+#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
+#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
+#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
+#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
+#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
+#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
+#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
+#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
+#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
+#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
+#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
+#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
+#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
+#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
+#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
+#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
+#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
+#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BE */
+#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
+#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
+#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
+#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_CS */
+#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
+#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
+#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
+#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
+#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
+#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
+#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
+#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_UART */
+#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
+#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
+#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
+#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
+#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
+#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
+#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
+#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
+#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
+#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
+#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
+#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
+
+/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
+#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
+#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
+#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
+#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
+#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
+#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
+#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
+#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
+#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
+#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
+#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_FECH
+#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
+
+#define MCFGPIO_PIN_MAX 136
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+
+/*********************************************************************
+ *
+ * Interrupt Controller (INTC)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
+#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
+#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
+#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
+#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
+#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
+#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
+#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
+#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
+#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
+#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
+#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
+#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
+#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
+#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
+#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
+#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
+#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
+#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
+#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
+#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
+#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
+#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
+#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
+#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
+#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
+#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
+#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
+#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
+#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
+#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
+#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
+#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
+#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
+#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
+#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
+#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
+#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
+#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
+#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
+#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
+#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
+#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
+#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
+#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
+#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
+#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
+#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
+#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
+#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
+#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
+#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
+#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
+#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
+#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
+#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
+#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
+#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
+#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
+#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
+#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
+#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
+#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
+#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
+#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
+#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
+#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
+#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
+#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
+#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
+#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
+#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
+#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
+#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
+#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
+#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
+#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
+#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
+#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
+#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
+#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
+#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
+#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
+#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
+#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
+#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
+#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
+#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
+#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
+#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
+#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
+#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
+#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
+#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
+#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
+#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
+#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
+#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
+#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
+#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
+#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
+#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
+#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
+#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
+#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
+#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
+#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
+#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
+#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
+#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
+#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
+#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
+#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
+#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
+#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
+#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
+#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
+#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
+#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
+#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
+#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
+#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
+#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
+#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
+#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
+#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
+#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
+#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
+#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
+#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
+#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
+#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
+#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
+#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
+#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
+#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
+#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
+#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
+#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
+#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
+#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
+#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
+#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
+#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
+#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
+#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
+#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
+#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
+#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
+#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
+#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
+#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
+#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
+#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
+#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
+#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
+#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
+#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
+#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
+#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
+#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
+#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
+#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
+#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
+#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
+#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
+#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
+#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
+#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
+#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
+#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
+#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
+#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
+#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
+#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
+#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
+#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
+#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
+#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
+#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
+#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
+#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
+#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
+#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
+#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
+#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
+#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
+#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
+#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
+#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
+#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
+#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
+#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
+#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
+#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
+#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
+#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
+#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
+#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
+#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
+#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
+#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
+#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
+#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
+#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
+#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
+#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
+#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
+#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
+#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
+#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
+#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
+#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
+#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
+#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
+#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
+#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
+#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
+#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
+#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
+#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
+#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
+#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
+#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
+#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
+#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
+#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
+#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
+#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
+#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
+#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
+#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
+#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
+#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
+#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
+#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
+#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
+#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
+#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
+#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
+#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
+#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
+#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
+#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
+#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
+#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
+#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
+#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
+#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
+#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
+#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
+#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
+#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32 (0x00000001)
+#define MCF_INTC_IPRH_INT33 (0x00000002)
+#define MCF_INTC_IPRH_INT34 (0x00000004)
+#define MCF_INTC_IPRH_INT35 (0x00000008)
+#define MCF_INTC_IPRH_INT36 (0x00000010)
+#define MCF_INTC_IPRH_INT37 (0x00000020)
+#define MCF_INTC_IPRH_INT38 (0x00000040)
+#define MCF_INTC_IPRH_INT39 (0x00000080)
+#define MCF_INTC_IPRH_INT40 (0x00000100)
+#define MCF_INTC_IPRH_INT41 (0x00000200)
+#define MCF_INTC_IPRH_INT42 (0x00000400)
+#define MCF_INTC_IPRH_INT43 (0x00000800)
+#define MCF_INTC_IPRH_INT44 (0x00001000)
+#define MCF_INTC_IPRH_INT45 (0x00002000)
+#define MCF_INTC_IPRH_INT46 (0x00004000)
+#define MCF_INTC_IPRH_INT47 (0x00008000)
+#define MCF_INTC_IPRH_INT48 (0x00010000)
+#define MCF_INTC_IPRH_INT49 (0x00020000)
+#define MCF_INTC_IPRH_INT50 (0x00040000)
+#define MCF_INTC_IPRH_INT51 (0x00080000)
+#define MCF_INTC_IPRH_INT52 (0x00100000)
+#define MCF_INTC_IPRH_INT53 (0x00200000)
+#define MCF_INTC_IPRH_INT54 (0x00400000)
+#define MCF_INTC_IPRH_INT55 (0x00800000)
+#define MCF_INTC_IPRH_INT56 (0x01000000)
+#define MCF_INTC_IPRH_INT57 (0x02000000)
+#define MCF_INTC_IPRH_INT58 (0x04000000)
+#define MCF_INTC_IPRH_INT59 (0x08000000)
+#define MCF_INTC_IPRH_INT60 (0x10000000)
+#define MCF_INTC_IPRH_INT61 (0x20000000)
+#define MCF_INTC_IPRH_INT62 (0x40000000)
+#define MCF_INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT0 (0x00000001)
+#define MCF_INTC_IPRL_INT1 (0x00000002)
+#define MCF_INTC_IPRL_INT2 (0x00000004)
+#define MCF_INTC_IPRL_INT3 (0x00000008)
+#define MCF_INTC_IPRL_INT4 (0x00000010)
+#define MCF_INTC_IPRL_INT5 (0x00000020)
+#define MCF_INTC_IPRL_INT6 (0x00000040)
+#define MCF_INTC_IPRL_INT7 (0x00000080)
+#define MCF_INTC_IPRL_INT8 (0x00000100)
+#define MCF_INTC_IPRL_INT9 (0x00000200)
+#define MCF_INTC_IPRL_INT10 (0x00000400)
+#define MCF_INTC_IPRL_INT11 (0x00000800)
+#define MCF_INTC_IPRL_INT12 (0x00001000)
+#define MCF_INTC_IPRL_INT13 (0x00002000)
+#define MCF_INTC_IPRL_INT14 (0x00004000)
+#define MCF_INTC_IPRL_INT15 (0x00008000)
+#define MCF_INTC_IPRL_INT16 (0x00010000)
+#define MCF_INTC_IPRL_INT17 (0x00020000)
+#define MCF_INTC_IPRL_INT18 (0x00040000)
+#define MCF_INTC_IPRL_INT19 (0x00080000)
+#define MCF_INTC_IPRL_INT20 (0x00100000)
+#define MCF_INTC_IPRL_INT21 (0x00200000)
+#define MCF_INTC_IPRL_INT22 (0x00400000)
+#define MCF_INTC_IPRL_INT23 (0x00800000)
+#define MCF_INTC_IPRL_INT24 (0x01000000)
+#define MCF_INTC_IPRL_INT25 (0x02000000)
+#define MCF_INTC_IPRL_INT26 (0x04000000)
+#define MCF_INTC_IPRL_INT27 (0x08000000)
+#define MCF_INTC_IPRL_INT28 (0x10000000)
+#define MCF_INTC_IPRL_INT29 (0x20000000)
+#define MCF_INTC_IPRL_INT30 (0x40000000)
+#define MCF_INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
+#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
+#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
+#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
+#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
+#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
+#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
+#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
+#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
+#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
+#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
+#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
+#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
+#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
+#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
+#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
+#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
+#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
+#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
+#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
+#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
+#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
+#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
+#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
+#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
+#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
+#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
+#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
+#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
+#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
+#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
+#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
+#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
+#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
+#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
+#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
+#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
+#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
+#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
+#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
+#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
+#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
+#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
+#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
+#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
+#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
+#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
+#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
+#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
+#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
+#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
+#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
+#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
+#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
+#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
+#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
+#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
+#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
+#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
+#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
+#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
+#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
+#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
+#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
+#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
+#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
+#define MCF_INTC_INTFRCH_INTFRC44 (0x0