summaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include/plat
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include/plat')
-rw-r--r--arch/arm/plat-omap/include/plat/blizzard.h12
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h49
-rw-r--r--arch/arm/plat-omap/include/plat/board.h2
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h10
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h9
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h55
-rw-r--r--arch/arm/plat-omap/include/plat/hwa742.h8
-rw-r--r--arch/arm/plat-omap/include/plat/io.h277
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h333
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h3
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h9
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h9
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h18
-rw-r--r--arch/arm/plat-omap/include/plat/remoteproc.h57
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h4
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h1
-rw-r--r--arch/arm/plat-omap/include/plat/system.h15
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h17
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h40
-rw-r--r--arch/arm/plat-omap/include/plat/vram.h21
24 files changed, 169 insertions, 786 deletions
diff --git a/arch/arm/plat-omap/include/plat/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
deleted file mode 100644
index 56e7f2e7d12..00000000000
--- a/arch/arm/plat-omap/include/plat/blizzard.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _BLIZZARD_H
-#define _BLIZZARD_H
-
-struct blizzard_platform_data {
- void (*power_up)(struct device *dev);
- void (*power_down)(struct device *dev);
- unsigned long (*get_clock_rate)(struct device *dev);
-
- unsigned te_connected:1;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906..ad6f865d1f1 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -28,33 +28,8 @@
#if defined (CONFIG_MACH_AMS_DELTA)
-#define AMS_DELTA_LATCH1_PHYS 0x01000000
-#define AMS_DELTA_LATCH1_VIRT 0xEA000000
-#define AMS_DELTA_MODEM_PHYS 0x04000000
-#define AMS_DELTA_MODEM_VIRT 0xEB000000
-#define AMS_DELTA_LATCH2_PHYS 0x08000000
-#define AMS_DELTA_LATCH2_VIRT 0xEC000000
-
-#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
-#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
-#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
-#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
-#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
-#define AMS_DELTA_LATCH1_LED_VOICE 0x20
-
-#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
-#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
-#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
-#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
-#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
-#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
-#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
-#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
-#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
-#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
-#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
@@ -66,9 +41,29 @@
#define AMS_DELTA_GPIO_PIN_CONFIG 11
#define AMS_DELTA_GPIO_PIN_NAND_RB 12
+#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
+#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
+#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
+#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
+#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
+#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
+#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
+#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
+#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
+#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
+#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
+#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
+#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
+
+#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
+#define AMS_DELTA_LATCH2_NGPIO 16
+
#ifndef __ASSEMBLY__
-void ams_delta_latch1_write(u8 mask, u8 value);
-void ams_delta_latch2_write(u16 mask, u16 value);
+void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
+#define ams_delta_latch2_write(mask, value) \
+ ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
+ AMS_DELTA_LATCH2_NGPIO, (mask), (value))
#endif
#endif /* CONFIG_MACH_AMS_DELTA */
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 97126dfd288..d5eb4c87db9 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -28,9 +28,7 @@ enum {
/* Different peripheral ids */
#define OMAP_TAG_CLOCK 0x4f01
-#define OMAP_TAG_LCD 0x4f05
#define OMAP_TAG_GPIO_SWITCH 0x4f06
-#define OMAP_TAG_FBMEM 0x4f08
#define OMAP_TAG_STI_CONSOLE 0x4f09
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 240a7b9fd94..d0ef57c1d71 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -272,8 +272,6 @@ struct clk {
#endif
};
-struct cpufreq_frequency_table;
-
struct clk_functions {
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
@@ -283,10 +281,6 @@ struct clk_functions {
void (*clk_allow_idle)(struct clk *clk);
void (*clk_deny_idle)(struct clk *clk);
void (*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
- void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
- void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
-#endif
};
extern int mpurate;
@@ -301,10 +295,6 @@ extern void recalculate_root_clocks(void);
extern unsigned long followparent_recalc(struct clk *clk);
extern void clk_enable_init_clocks(void);
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
-extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
-extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
-#endif
extern struct clk *omap_clk_get_by_name(const char *name);
extern int omap_clk_enable_autoidle_all(void);
extern int omap_clk_disable_autoidle_all(void);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 6b51086fce1..dc6a86bf217 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
- * cpu_is_omap4430(): True for OMAP4430
* cpu_is_omap3505(): True for OMAP3505
* cpu_is_omap3517(): True for OMAP3517
*/
@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap3505() 0
#define cpu_is_omap3517() 0
#define cpu_is_omap3430() 0
-#define cpu_is_omap4430() 0
#define cpu_is_omap3630() 0
/*
@@ -451,7 +449,12 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
-void omap2_check_revision(void);
+void omap2xxx_check_revision(void);
+void omap3xxx_check_revision(void);
+void omap4xxx_check_revision(void);
+void omap3xxx_check_features(void);
+void ti81xx_check_features(void);
+void omap4xxx_check_features(void);
/*
* Runtime detection of OMAP3 features
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0..2f6e9924a81 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -158,17 +158,6 @@
#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
-#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
- IH_MPUIO_BASE + ((nr) & 0x0f) : \
- IH_GPIO_BASE + (nr))
-
-#define METHOD_MPUIO 0
-#define METHOD_GPIO_1510 1
-#define METHOD_GPIO_1610 2
-#define METHOD_GPIO_7XX 3
-#define METHOD_GPIO_24XX 5
-#define METHOD_GPIO_44XX 6
-
struct omap_gpio_dev_attr {
int bank_width; /* GPIO bank width */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +173,21 @@ struct omap_gpio_reg_offs {
u16 irqstatus;
u16 irqstatus2;
u16 irqenable;
+ u16 irqenable2;
u16 set_irqenable;
u16 clr_irqenable;
u16 debounce;
u16 debounce_en;
+ u16 ctrl;
+ u16 wkup_en;
+ u16 leveldetect0;
+ u16 leveldetect1;
+ u16 risingdetect;
+ u16 fallingdetect;
+ u16 irqctrl;
+ u16 edgectrl1;
+ u16 edgectrl2;
+ u16 pinctrl;
bool irqenable_inv;
};
@@ -198,45 +198,30 @@ struct omap_gpio_platform_data {
int bank_width; /* GPIO bank width */
int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
+ bool loses_context; /* whether the bank would ever lose context */
+ bool is_mpuio; /* whether the bank is of type MPUIO */
+ u32 non_wakeup_gpios;
struct omap_gpio_reg_offs *regs;
-};
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
+ /* Return context loss count due to PM states changing */
+ int (*get_context_loss_count)(struct device *dev);
+};
extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
/*-------------------------------------------------------------------------*/
-/* Wrappers for "new style" GPIO calls, using the new infrastructure
+/*
+ * Wrappers for "new style" GPIO calls, using the new infrastructure
* which lets us plug in FPGA, I2C, and other implementations.
- * *
+ *
* The original OMAP-specific calls should eventually be removed.
*/
#include <linux/errno.h>
#include <asm-generic/gpio.h>
-static inline int irq_to_gpio(unsigned irq)
-{
- int tmp;
-
- /* omap1 SOC mpuio */
- if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
- return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
-
- /* SOC gpio */
- tmp = irq - IH_GPIO_BASE;
- if (tmp < OMAP_MAX_GPIO_LINES)
- return tmp;
-
- /* we don't supply reverse mappings for non-SOC gpios */
- return -EIO;
-}
-
#endif
diff --git a/arch/arm/plat-omap/include/plat/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
deleted file mode 100644
index 886248d32b4..00000000000
--- a/arch/arm/plat-omap/include/plat/hwa742.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _HWA742_H
-#define _HWA742_H
-
-struct hwa742_platform_data {
- unsigned te_connected:1;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
deleted file mode 100644
index 0696bae1818..00000000000
--- a/arch/arm/plat-omap/include/plat/io.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- * 06-12-1997 RMK Created.
- * 07-04-1999 RMK Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-/*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
- */
-
-#ifdef __ASSEMBLER__
-#define IOMEM(x) (x)
-#else
-#define IOMEM(x) ((void __force __iomem *)(x))
-#endif
-
-#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
-#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
-
-#define OMAP2_L3_IO_OFFSET 0x90000000
-#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
-
-
-#define OMAP2_L4_IO_OFFSET 0xb2000000
-#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
-
-#define OMAP4_L3_IO_OFFSET 0xb4000000
-#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
-
-#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
-#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
-
-#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
-#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
-
-#define OMAP4_GPMC_IO_OFFSET 0xa9000000
-#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
-
-#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
-#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
-
-/*
- * ----------------------------------------------------------------------------
- * Omap1 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1_IO_PHYS 0xFFFB0000
-#define OMAP1_IO_SIZE 0x40000
-#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
-
-/*
- * ----------------------------------------------------------------------------
- * Omap2 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-/* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
-#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
-#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
-#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
-
-#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
-#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_243X_SIZE SZ_1M
-#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
-#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
- /* 0x6e000000 --> 0xfe000000 */
-#define OMAP243X_GPMC_SIZE SZ_1M
-#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
- /* 0x6D000000 --> 0xfd000000 */
-#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SDRC_SIZE SZ_1M
-#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
- /* 0x6c000000 --> 0xfc000000 */
-#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SMS_SIZE SZ_1M
-
-/* 2420 IVA */
-#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
- /* 0x58000000 --> 0xfc100000 */
-#define DSP_MEM_2420_VIRT 0xfc100000
-#define DSP_MEM_2420_SIZE 0x28000
-#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
- /* 0x59000000 --> 0xfc128000 */
-#define DSP_IPI_2420_VIRT 0xfc128000
-#define DSP_IPI_2420_SIZE SZ_4K
-#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
- /* 0x5a000000 --> 0xfc129000 */
-#define DSP_MMU_2420_VIRT 0xfc129000
-#define DSP_MMU_2420_SIZE SZ_4K
-
-/* 2430 IVA2.1 - currently unmapped */
-
-/*
- * ----------------------------------------------------------------------------
- * Omap3 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-/* We map both L3 and L4 on OMAP3 */
-#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
-#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
-#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
-
-#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
-#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
-
-/*
- * ----------------------------------------------------------------------------
- * AM33XX specific IO mapping
- * ----------------------------------------------------------------------------
- */
-#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
-#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
-#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
-
-/*
- * Need to look at the Size 4M for L4.
- * VPOM3430 was not working for Int controller
- */
-
-#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
- /* 0x49000000 --> 0xfb000000 */
-#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_PER_34XX_SIZE SZ_1M
-
-#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
- /* 0x54000000 --> 0xfe800000 */
-#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
-#define L4_EMU_34XX_SIZE SZ_8M
-
-#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
- /* 0x6e000000 --> 0xfe000000 */
-#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP34XX_GPMC_SIZE SZ_1M
-
-#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
- /* 0x6c000000 --> 0xfc000000 */
-#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP343X_SMS_SIZE SZ_1M
-
-#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
- /* 0x6D000000 --> 0xfd000000 */
-#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP343X_SDRC_SIZE SZ_1M
-
-/* 3430 IVA - currently unmapped */
-
-/*
- * ----------------------------------------------------------------------------
- * Omap4 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-/* We map both L3 and L4 on OMAP4 */
-#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
-#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
-#define L3_44XX_SIZE SZ_1M
-
-#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
-#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_44XX_SIZE SZ_4M
-
-#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
- /* 0x48000000 --> 0xfa000000 */
-#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_PER_44XX_SIZE SZ_4M
-
-#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
- /* 0x49000000 --> 0xfb000000 */
-#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_ABE_44XX_SIZE SZ_1M
-
-#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
- /* 0x54000000 --> 0xfe800000 */
-#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
-#define L4_EMU_44XX_SIZE SZ_8M
-
-#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
- /* 0x50000000 --> 0xf9000000 */
-#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
-#define OMAP44XX_GPMC_SIZE SZ_1M
-
-
-#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
- /* 0x4c000000 --> 0xfd100000 */
-#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
-#define OMAP44XX_EMIF1_SIZE SZ_1M
-
-#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
- /* 0x4d000000 --> 0xfd200000 */
-#define OMAP44XX_EMIF2_SIZE SZ_1M
-#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
-
-#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
- /* 0x4e000000 --> 0xfd300000 */
-#define OMAP44XX_DMM_SIZE SZ_1M
-#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
-/*
- * ----------------------------------------------------------------------------
- * Omap specific register access
- * ----------------------------------------------------------------------------
- */
-
-#ifndef __ASSEMBLER__
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-extern u8 omap_readb(u32 pa);
-extern u16 omap_readw(u32 pa);
-extern u32 omap_readl(u32 pa);
-extern void omap_writeb(u8 v, u32 pa);
-extern void omap_writew(u16 v, u32 pa);
-extern void omap_writel(u32 v, u32 pa);
-
-struct omap_sdrc_params;
-extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
- struct omap_sdrc_params *sdrc_cs1);
-
-extern void __init omap_init_consistent_dma_size(void);
-
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 793ce9d5329..a6b21eddb21 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -12,6 +12,8 @@
#ifndef CONFIG_ARCH_OMAP1
#warning Please update the board to use matrix-keypad driver
+#define omap_readw(reg) 0
+#define omap_writew(val, reg) do {} while (0)
#endif
#include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 8fa74e2c9d6..18814127809 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -27,271 +27,10 @@
#include <linux/spinlock.h>
#include <linux/clk.h>
-/* macro for building platform_device for McBSP ports */
-#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
-static struct platform_device omap_mcbsp##port_nr = { \
- .name = "omap-mcbsp-dai", \
- .id = port_nr - 1, \
-}
-
#define MCBSP_CONFIG_TYPE2 0x2
#define MCBSP_CONFIG_TYPE3 0x3
#define MCBSP_CONFIG_TYPE4 0x4
-/* McBSP register numbers. Register address offset = num * reg_step */
-enum {
- /* Common registers */
- OMAP_MCBSP_REG_SPCR2 = 4,
- OMAP_MCBSP_REG_SPCR1,
- OMAP_MCBSP_REG_RCR2,
- OMAP_MCBSP_REG_RCR1,
- OMAP_MCBSP_REG_XCR2,
- OMAP_MCBSP_REG_XCR1,
- OMAP_MCBSP_REG_SRGR2,
- OMAP_MCBSP_REG_SRGR1,
- OMAP_MCBSP_REG_MCR2,
- OMAP_MCBSP_REG_MCR1,
- OMAP_MCBSP_REG_RCERA,
- OMAP_MCBSP_REG_RCERB,
- OMAP_MCBSP_REG_XCERA,
- OMAP_MCBSP_REG_XCERB,
- OMAP_MCBSP_REG_PCR0,
- OMAP_MCBSP_REG_RCERC,
- OMAP_MCBSP_REG_RCERD,
- OMAP_MCBSP_REG_XCERC,
- OMAP_MCBSP_REG_XCERD,
- OMAP_MCBSP_REG_RCERE,
- OMAP_MCBSP_REG_RCERF,
- OMAP_MCBSP_REG_XCERE,
- OMAP_MCBSP_REG_XCERF,
- OMAP_MCBSP_REG_RCERG,
- OMAP_MCBSP_REG_RCERH,
- OMAP_MCBSP_REG_XCERG,
- OMAP_MCBSP_REG_XCERH,
-
- /* OMAP1-OMAP2420 registers */
- OMAP_MCBSP_REG_DRR2 = 0,
- OMAP_MCBSP_REG_DRR1,
- OMAP_MCBSP_REG_DXR2,
- OMAP_MCBSP_REG_DXR1,
-
- /* OMAP2430 and onwards */
- OMAP_MCBSP_REG_DRR = 0,
- OMAP_MCBSP_REG_DXR = 2,
- OMAP_MCBSP_REG_SYSCON = 35,
- OMAP_MCBSP_REG_THRSH2,
- OMAP_MCBSP_REG_THRSH1,
- OMAP_MCBSP_REG_IRQST = 40,
- OMAP_MCBSP_REG_IRQEN,
- OMAP_MCBSP_REG_WAKEUPEN,
- OMAP_MCBSP_REG_XCCR,
- OMAP_MCBSP_REG_RCCR,
- OMAP_MCBSP_REG_XBUFFSTAT,
- OMAP_MCBSP_REG_RBUFFSTAT,
- OMAP_MCBSP_REG_SSELCR,
-};
-
-/* OMAP3 sidetone control registers */
-#define OMAP_ST_REG_REV 0x00
-#define OMAP_ST_REG_SYSCONFIG 0x10
-#define OMAP_ST_REG_IRQSTATUS 0x18
-#define OMAP_ST_REG_IRQENABLE 0x1C
-#define OMAP_ST_REG_SGAINCR 0x24
-#define OMAP_ST_REG_SFIRCR 0x28
-#define OMAP_ST_REG_SSELCR 0x2C
-
-/************************** McBSP SPCR1 bit definitions ***********************/
-#define RRST 0x0001
-#define RRDY 0x0002
-#define RFULL 0x0004
-#define RSYNC_ERR 0x0008
-#define RINTM(value) ((value)<<4) /* bits 4:5 */
-#define ABIS 0x0040
-#define DXENA 0x0080
-#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
-#define RJUST(value) ((value)<<13) /* bits 13:14 */
-#define ALB 0x8000
-#define DLB 0x8000
-
-/************************** McBSP SPCR2 bit definitions ***********************/
-#define XRST 0x0001
-#define XRDY 0x0002
-#define XEMPTY 0x0004
-#define XSYNC_ERR 0x0008
-#define XINTM(value) ((value)<<4) /* bits 4:5 */
-#define GRST 0x0040
-#define FRST 0x0080
-#define SOFT 0x0100
-#define FREE 0x0200
-
-/************************** McBSP PCR bit definitions *************************/
-#define CLKRP 0x0001
-#define CLKXP 0x0002
-#define FSRP 0x0004
-#define FSXP 0x0008
-#define DR_STAT 0x0010
-#define DX_STAT 0x0020
-#define CLKS_STAT 0x0040
-#define SCLKME 0x0080
-#define CLKRM 0x0100
-#define CLKXM 0x0200
-#define FSRM 0x0400
-#define FSXM 0x0800
-#define RIOEN 0x1000
-#define XIOEN 0x2000
-#define IDLE_EN 0x4000
-
-/************************** McBSP RCR1 bit definitions ************************/
-#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
-#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
-
-/************************** McBSP XCR1 bit definitions ************************/
-#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
-#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
-
-/*************************** McBSP RCR2 bit definitions ***********************/
-#define RDATDLY(value) (value) /* Bits 0:1 */
-#define RFIG 0x0004
-#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
-#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
-#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
-#define RPHASE 0x8000
-
-/*************************** McBSP XCR2 bit definitions ***********************/
-#define XDATDLY(value) (value) /* Bits 0:1 */
-#define XFIG 0x0004
-#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
-#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
-#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
-#define XPHASE 0x8000
-
-/************************* McBSP SRGR1 bit definitions ************************/
-#define CLKGDV(value) (value) /* Bits 0:7 */
-#define FWID(value) ((value)<<8) /* Bits 8:15 */
-
-/************************* McBSP SRGR2 bit definitions ************************/
-#define FPER(value) (value) /* Bits 0:11 */
-#define FSGM 0x1000
-#define CLKSM 0x2000
-#define CLKSP 0x4000
-#define GSYNC 0x8000
-
-/************************* McBSP MCR1 bit definitions *************************/
-#define RMCM 0x0001
-#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
-#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
-#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
-
-/************************* McBSP MCR2 bit definitions *************************/
-#define XMCM(value) (value) /* Bits 0:1 */
-#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
-#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
-#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
-
-/*********************** McBSP XCCR bit definitions *************************/
-#define EXTCLKGATE 0x8000
-#define PPCONNECT 0x4000
-#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
-#define XFULL_CYCLE 0x0800
-#define DILB 0x0020
-#define XDMAEN 0x0008
-#define XDISABLE 0x0001
-
-/********************** McBSP RCCR bit definitions *************************/
-#define RFULL_CYCLE 0x0800
-#define RDMAEN 0x0008
-#define RDISABLE 0x0001
-
-/********************** McBSP SYSCONFIG bit definitions ********************/
-#define CLOCKACTIVITY(value) ((value)<<8)
-#define SIDLEMODE(value) ((value)<<3)
-#define ENAWAKEUP 0x0004
-#define SOFTRST 0x0002
-
-/********************** McBSP SSELCR bit definitions ***********************/
-#define SIDETONEEN 0x0400
-
-/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
-#define ST_AUTOIDLE 0x0001
-
-/********************** McBSP Sidetone SGAINCR bit definitions *************/
-#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
-#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
-
-/********************** McBSP Sidetone SFIRCR bit definitions **************/
-#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
-
-/********************** McBSP Sidetone SSELCR bit definitions **************/
-#define ST_COEFFWRDONE 0x0004
-#define ST_COEFFWREN 0x0002
-#define ST_SIDETONEEN 0x0001
-
-/********************** McBSP DMA operating modes **************************/
-#define MCBSP_DMA_MODE_ELEMENT 0
-#define MCBSP_DMA_MODE_THRESHOLD 1
-#define MCBSP_DMA_MODE_FRAME 2
-
-/********************** McBSP WAKEUPEN bit definitions *********************/
-#define XEMPTYEOFEN 0x4000
-#define XRDYEN 0x0400
-#define XEOFEN 0x0200
-#define XFSXEN 0x0100
-#define XSYNCERREN 0x0080
-#define RRDYEN 0x0008
-#define REOFEN 0x0004
-#define RFSREN 0x0002
-#define RSYNCERREN 0x0001
-
-/* CLKR signal muxing options */
-#define CLKR_SRC_CLKR 0
-#define CLKR_SRC_CLKX 1
-
-/* FSR signal muxing options */
-#define FSR_SRC_FSR 0
-#define FSR_SRC_FSX 1
-
-/* McBSP functional clock sources */
-#define MCBSP_CLKS_PRCM_SRC 0
-#define MCBSP_CLKS_PAD_SRC 1
-
-/* we don't do multichannel for now */
-struct omap_mcbsp_reg_cfg {
- u16 spcr2;
- u16 spcr1;
- u16 rcr2;
- u16 rcr1;
- u16 xcr2;
- u16 xcr1;
- u16 srgr2;
- u16 srgr1;
- u16 mcr2;
- u16 mcr1;
- u16 pcr0;
- u16 rcerc;
- u16 rcerd;
- u16 xcerc;
- u16 xcerd;
- u16 rcere;
- u16 rcerf;
- u16 xcere;
- u16 xcerf;
- u16 rcerg;
- u16 rcerh;
- u16 xcerg;
- u16 xcerh;
- u16 xccr;
- u16 rccr;
-};
-
-typedef enum {
- OMAP_MCBSP_WORD_8 = 0,
- OMAP_MCBSP_WORD_12,
- OMAP_MCBSP_WORD_16,
- OMAP_MCBSP_WORD_20,
- OMAP_MCBSP_WORD_24,
- OMAP_MCBSP_WORD_32,
-} omap_mcbsp_word_length;
-
/* Platform specific configuration */
struct omap_mcbsp_ops {
void (*request)(unsigned int);
@@ -312,43 +51,6 @@ struct omap_mcbsp_platform_data {
int (*mux_signal)(struct device *dev, const char *signal, const char *src);
};
-struct omap_mcbsp_st_data {
- void __iomem *io_base_st;
- bool running;
- bool enabled;
- s16 taps[128]; /* Sidetone filter coefficients */
- int nr_taps; /* Number of filter coefficients in use */
- s16 ch0gain;
- s16 ch1gain;
-};
-
-struct omap_mcbsp {
- struct device *dev;
- unsigned long phys_base;
- unsigned long phys_dma_base;
- void __iomem *io_base;
- u8 id;
- u8 free;
-
- int rx_irq;
- int tx_irq;
-
- /* DMA stuff */
- u8 dma_rx_sync;
- u8 dma_tx_sync;
-
- /* Protect the field .free, while checking if the mcbsp is in use */
- spinlock_t lock;
- struct omap_mcbsp_platform_data *pdata;
- struct clk *fclk;
- struct omap_mcbsp_st_data *st_data;
- int dma_op_mode;
- u16 max_tx_thres;
- u16 max_rx_thres;
- void *reg_cache;
- int reg_cache_size;
-};
-
/**
* omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
* @sidetone: name of the sidetone device
@@ -357,39 +59,4 @@ struct omap_mcbsp_dev_attr {
const char *sidetone;
};
-extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count;
-
-int omap_mcbsp_init(void);
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
-void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
-u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
-u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
-u16 omap_mcbsp_get_fifo_size(unsigned int id);
-u16 omap_mcbsp_get_tx_delay(unsigned int id);
-u16 omap_mcbsp_get_rx_delay(unsigned int id);
-int omap_mcbsp_get_dma_op_mode(unsigned int id);
-int omap_mcbsp_request(unsigned int id);
-void omap_mcbsp_free(unsigned int id);
-void omap_mcbsp_start(unsigned int id, int tx, int rx);
-void omap_mcbsp_stop(unsigned int id, int tx, int rx);
-
-/* McBSP functional clock source changing function */
-extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
-
-/* McBSP signal muxing API */
-void omap2_mcbsp1_mux_clkr_src(u8 mux);
-void omap2_mcbsp1_mux_fsr_src(u8 mux);
-
-int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
-int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
-
-/* Sidetone specific API */
-int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
-int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
-int omap_st_enable(unsigned int id);
-int omap_st_disable(unsigned int id);
-int omap_st_is_enabled(unsigned int id);
-
#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 3d51b18131c..a357eb26bd2 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
struct omap2_mcspi_device_config {
unsigned turbo_mode:1;
-
- /* Do we want one channel enabled at the same time? */
- unsigned single_channel:1;
};
#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f75946c3293..7a38750c007 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -137,8 +137,6 @@ struct omap_mmc_platform_data {
int (*set_power)(struct device *dev, int slot,
int power_on, int vdd);
int (*get_ro)(struct device *dev, int slot);
- int (*set_sleep)(struct device *dev, int slot, int sleep,
- int vdd, int cardsleep);
void (*remux)(struct device *dev, int slot, int power_on);
/* Call back before enabling / disabling regulators */
void (*before_set_reg)(struct device *dev, int slot,
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c878323..8ad0a377a54 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
-#include <linux/input/matrix_keypad.h>
-
-struct omap4_keypad_platform_data {
- const struct matrix_keymap_data *keymap_data;
-
- u8 rows;
- u8 cols;
-};
-
extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
struct omap_board_data *);
#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 51423d2727a..4327b2c90c3 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,7 +36,7 @@
#include <plat/omap_hwmod.h>
-extern struct device omap_device_parent;
+extern struct dev_pm_domain omap_device_pm_domain;
/* omap_device._state values */
#define OMAP_DEVICE_STATE_UNKNOWN 0
@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
struct omap_device_pm_latency *pm_lats,
int pm_lats_cnt, int is_early_device);
+struct omap_device *omap_device_alloc(struct platform_device *pdev,
+ struct omap_hwmod **ohs, int oh_cnt,
+ struct omap_device_pm_latency *pm_lats,
+ int pm_lats_cnt);
+void omap_device_delete(struct omap_device *od);
+int omap_device_register(struct platform_device *pdev);
+
void __iomem *omap_device_get_rt_va(struct omap_device *od);
struct device *omap_device_get_by_hwmod_name(const char *oh_name);
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 647010109af..3f26db4ee8e 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -47,17 +47,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
* with the original PRCM protocol defined for OMAP2420
*/
#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
-#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
+#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
-#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
-#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
+#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
-#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
+#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
#define SYSC_TYPE1_SOFTRESET_SHIFT 1
-#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
-#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
+#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
/*
* OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
@@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
* @rev_offs: IP block revision register offset (from module base addr)
* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
* @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
+ * @srst_udelay: Delay needed after doing a softreset in usecs
* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
* @clockact: the default value of the module CLOCKACTIVITY bits
@@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
u16 sysc_offs;
u16 syss_offs;
u16 sysc_flags;
+ struct omap_hwmod_sysc_fields *sysc_fields;
+ u8 srst_udelay;
u8 idlemodes;
u8 clockact;
- struct omap_hwmod_sysc_fields *sysc_fields;
};
/**
@@ -484,7 +486,6 @@ struct omap_hwmod_class {
* @main_clk: main clock: OMAP clock name
* @_clk: pointer to the main struct clk (filled in at runtime)
* @opt_clks: other device clocks that drivers can request (0..*)
- * @vdd_name: voltage domain name
* @voltdm: pointer to voltage domain (filled in at runtime)
* @masters: ptr to array of OCP ifs that this hwmod can initiate on
* @slaves: ptr to array of OCP ifs that this hwmod can respond on
@@ -528,7 +529,6 @@ struct omap_hwmod {
struct omap_hwmod_opt_clk *opt_clks;
char *clkdm_name;
struct clockdomain *clkdm;
- char *vdd_name;
struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
void *dev_attr;
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
new file mode 100644
index 00000000000..b10eac89e2e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -0,0 +1,57 @@
+/*
+ * Remote Processor - omap-specific bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PLAT_REMOTEPROC_H
+#define _PLAT_REMOTEPROC_H
+
+struct rproc_ops;
+struct platform_device;
+
+/*
+ * struct omap_rproc_pdata - omap remoteproc's platform data
+ * @name: the remoteproc's name
+ * @oh_name: omap hwmod device
+ * @oh_name_opt: optional, secondary omap hwmod device
+ * @firmware: name of firmware file to load
+ * @mbox_name: name of omap mailbox device to use with this rproc
+ * @ops: start/stop rproc handlers
+ * @device_enable: omap-specific handler for enabling a device
+ * @device_shutdown: omap-specific handler for shutting down a device
+ */
+struct omap_rproc_pdata {
+ const char *name;
+ const char *oh_name;
+ const char *oh_name_opt;
+ const char *firmware;
+ const char *mbox_name;
+ const struct rproc_ops *ops;
+ int (*device_enable) (struct platform_device *pdev);
+ int (*device_shutdown) (struct platform_device *pdev);
+};
+
+#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
+
+void __init omap_rproc_reserve_cma(void);
+
+#else
+
+void __init omap_rproc_reserve_cma(void)
+{
+}
+
+#endif
+
+#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 925b12b500d..9bb978ecd88 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -16,7 +16,6 @@
* published by the Free Software Foundation.
*/
-#include <mach/io.h>
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6a4a6..fd14d28e5bb 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -110,8 +110,8 @@ struct omap_board_data;
struct omap_uart_port_info;
extern void omap_serial_init(void);
-extern int omap_uart_can_sleep(void);
-extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data,
+ u8 port_id);
extern void omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *platform_data);
#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 75aa1b2bef5..227ae265755 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
#else
#define OMAP4_SRAM_PA 0x40300000
#endif
+#define AM33XX_SRAM_PA 0x40300000
#endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b12..00000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copied from arch/arm/mach-sa1100/include/mach/system.h
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9..1b4b2da8620 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -84,23 +84,6 @@
#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
-/* Almost all documentation for chip and board memory maps assumes
- * BM is clear. Most devel boards have a switch to control booting
- * from NOR flash (using external chipselect 3) rather than mask ROM,
- * which uses BM to interchange the physical CS0 and CS3 addresses.
- */
-static inline u32 omap_cs0_phys(void)
-{
- return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
- ? OMAP_CS3_PHYS : 0;
-}
-
-static inline u32 omap_cs3_phys(void)
-{
- return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
- ? 0 : OMAP_CS3_PHYS;
-}
-
#endif /* __ASSEMBLER__ */
#endif /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee90495ca4..cc3f11ba7a9 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_OMAP3(3, igep0020);
DEBUG_LL_OMAP3(3, igep0030);
DEBUG_LL_OMAP3(3, nokia_rm680);
+ DEBUG_LL_OMAP3(3, nokia_rm696);
DEBUG_LL_OMAP3(3, nokia_rx51);
DEBUG_LL_OMAP3(3, omap3517evm);
DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index dc864b580da..762eeb0626c 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
#ifndef __ASM_ARCH_OMAP_USB_H
#define __ASM_ARCH_OMAP_USB_H
+#include <linux/io.h>
#include <linux/usb/musb.h>
#include <plat/board.h>
@@ -105,6 +106,45 @@ extern int omap4430_phy_set_clk(struct device *dev, int on);
extern int omap4430_phy_init(struct device *dev);
extern int omap4430_phy_exit(struct device *dev);
extern int omap4430_phy_suspend(struct device *dev, int suspend);
+
+/*
+ * NOTE: Please update omap USB drivers to use ioremap + read/write
+ */
+
+#define OMAP2_L4_IO_OFFSET 0xb2000000
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
+
+static inline u8 omap_readb(u32 pa)
+{
+ return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u16 omap_readw(u32 pa)
+{
+ return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u32 omap_readl(u32 pa)
+{
+ return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writeb(u8 v, u32 pa)
+{
+ __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+
+static inline void omap_writew(u16 v, u32 pa)
+{
+ __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writel(u32 v, u32 pa)
+{
+ __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
#endif
extern void am35x_musb_reset(void);
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index 0aa4ecd12c7..4d65b7d06e6 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -23,40 +23,21 @@
#include <linux/types.h>
-#define OMAP_VRAM_MEMTYPE_SDRAM 0
-#define OMAP_VRAM_MEMTYPE_SRAM 1
-#define OMAP_VRAM_MEMTYPE_MAX 1
-
extern int omap_vram_add_region(unsigned long paddr, size_t size);
extern int omap_vram_free(unsigned long paddr, size_t size);
-extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
+extern int omap_vram_alloc(size_t size, unsigned long *paddr);
extern int omap_vram_reserve(unsigned long paddr, size_t size);
extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
unsigned long *largest_free_block);
#ifdef CONFIG_OMAP2_VRAM
extern void omap_vram_set_sdram_vram(u32 size, u32 start);
-extern void omap_vram_set_sram_vram(u32 size, u32 start);
extern void omap_vram_reserve_sdram_memblock(void);
-extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
- unsigned long sram_vstart,
- unsigned long sram_size,
- unsigned long pstart_avail,
- unsigned long size_avail);
#else
static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
-static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
static inline void omap_vram_reserve_sdram_memblock(void) { }
-static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
- unsigned long sram_vstart,
- unsigned long sram_size,
- unsigned long pstart_avail,
- unsigned long size_avail)
-{
- return 0;
-}
#endif
#endif