diff options
Diffstat (limited to 'arch/arm/boot/dts/highbank.dts')
| -rw-r--r-- | arch/arm/boot/dts/highbank.dts | 120 |
1 files changed, 119 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 83e72294aef..5204cf73c2d 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -1,5 +1,5 @@ /* - * Copyright 2011 Calxeda, Inc. + * Copyright 2011-2012 Calxeda, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,7 @@ compatible = "calxeda,highbank"; #address-cells = <1>; #size-cells = <1>; + clock-ranges; cpus { #address-cells = <1>; @@ -33,24 +34,32 @@ compatible = "arm,cortex-a9"; reg = <0>; next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; }; cpu@1 { compatible = "arm,cortex-a9"; reg = <1>; next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; }; cpu@2 { compatible = "arm,cortex-a9"; reg = <2>; next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; }; cpu@3 { compatible = "arm,cortex-a9"; reg = <3>; next-level-cache = <&L2>; + clocks = <&a9pll>; + clock-names = "cpu"; }; }; @@ -75,12 +84,14 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xfff10600 0x20>; interrupts = <1 13 0xf01>; + clocks = <&a9periphclk>; }; watchdog@fff10620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0xfff10620 0x20>; interrupts = <1 14 0xf01>; + clocks = <&a9periphclk>; }; intc: interrupt-controller@fff11000 { @@ -110,18 +121,30 @@ compatible = "calxeda,hb-ahci"; reg = <0xffe08000 0x10000>; interrupts = <0 83 4>; + calxeda,port-phys = <&combophy5 0 &combophy0 0 + &combophy0 1 &combophy0 2 + &combophy0 3>; }; sdhci@ffe0e000 { compatible = "calxeda,hb-sdhci"; reg = <0xffe0e000 0x1000>; interrupts = <0 90 4>; + clocks = <&eclk>; + }; + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; }; ipc@fff20000 { compatible = "arm,pl320", "arm,primecell"; reg = <0xfff20000 0x1000>; interrupts = <0 7 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpioe: gpio@fff30000 { @@ -130,6 +153,8 @@ gpio-controller; reg = <0xfff30000 0x1000>; interrupts = <0 14 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpiof: gpio@fff31000 { @@ -138,6 +163,8 @@ gpio-controller; reg = <0xfff31000 0x1000>; interrupts = <0 15 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpiog: gpio@fff32000 { @@ -146,6 +173,8 @@ gpio-controller; reg = <0xfff32000 0x1000>; interrupts = <0 16 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; gpioh: gpio@fff33000 { @@ -154,24 +183,32 @@ gpio-controller; reg = <0xfff33000 0x1000>; interrupts = <0 17 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; timer { compatible = "arm,sp804", "arm,primecell"; reg = <0xfff34000 0x1000>; interrupts = <0 18 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; rtc@fff35000 { compatible = "arm,pl031", "arm,primecell"; reg = <0xfff35000 0x1000>; interrupts = <0 19 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; serial@fff36000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xfff36000 0x1000>; interrupts = <0 20 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; smic@fff3a000 { @@ -186,12 +223,79 @@ sregs@fff3c000 { compatible = "calxeda,hb-sregs"; reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + a9bclk: a9bclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9bus-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + + emmcpll: emmcpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x10C>; + }; + + eclk: eclk { + #clock-cells = <0>; + compatible = "calxeda,hb-emmc-clock"; + clocks = <&emmcpll>; + reg = <0x114>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <150000000>; + }; + }; + }; + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4 0 72 4>; }; dma@fff3d000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xfff3d000 0x1000>; interrupts = <0 92 4>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; ethernet@fff50000 { @@ -205,5 +309,19 @@ reg = <0xfff51000 0x1000>; interrupts = <0 80 4 0 81 4 0 82 4>; }; + + combophy0: combo-phy@fff58000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff58000 0x1000>; + phydev = <5>; + }; + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; }; }; |