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-===================================================================
-Debug Control and Status Register (DCSR) Binding
-Copyright 2011 Freescale Semiconductor Inc.
-
-NOTE: The bindings described in this document are preliminary and subject
-to change. Some of the compatible strings that contain only generic names
-may turn out to be inappropriate, or need additional properties to describe
-the integration of the block with the rest of the chip.
-
-=====================================================================
-Debug Control and Status Register Memory Map
-
-Description
-
-This node defines the base address and range for the
-defined DCSR Memory Map. Child nodes will describe the individual
-debug blocks defined within this memory space.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr" and "simple-bus".
- The DCSR space exists in the memory-mapped bus.
-
- - #address-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- or representing physical addresses in child nodes.
-
- - #size-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- or representing the size of physical addresses in
- child nodes.
-
- - ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- range of the DCSR space.
-
-EXAMPLE
- dcsr: dcsr@f00000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,dcsr", "simple-bus";
- ranges = <0x00000000 0xf 0x00000000 0x01008000>;
- };
-
-=====================================================================
-Event Processing Unit
-
-This node represents the region of DCSR space allocated to the EPU
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr-epu"
-
- - interrupts
- Usage: required
- Value type: <prop_encoded-array>
- Definition: Specifies the interrupts generated by the EPU.
- The value of the interrupts property consists of three
- interrupt specifiers. The format of the specifier is defined
- by the binding document describing the node's interrupt parent.
-
- The EPU counters can be configured to assert the performance
- monitor interrupt signal based on either counter overflow or value
- match. Which counter asserted the interrupt is captured in an EPU
- Counter Interrupt Status Register (EPCPUISR).
-
- The EPU unit can also be configured to assert either or both of
- two interrupt signals based on debug event sources within the SoC.
- The interrupt signals are epu_xt_int0 and epu_xt_int1.
- Which event source asserted the interrupt is captured in an EPU
- Interrupt Status Register (EPISR0,EPISR1).
-
- Interrupt numbers are lised in order (perfmon, event0, event1).
-
- - interrupt-parent
- Usage: required
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped. Value must be "&mpic"
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-epu@0 {
- compatible = "fsl,dcsr-epu";
- interrupts = <52 2 0 0
- 84 2 0 0
- 85 2 0 0>;
- interrupt-parent = <&mpic>;
- reg = <0x0 0x1000>;
- };
-
-=======================================================================
-Nexus Port Controller
-
-This node represents the region of DCSR space allocated to the NPC
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr-npc"
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
- The Nexus Port controller occupies two regions in the DCSR space
- with distinct functionality.
-
- The first register range describes the Nexus Port Controller
- control and status registers.
-
- The second register range describes the Nexus Port Controller
- internal trace buffer. The NPC trace buffer is a small memory buffer
- which stages the nexus trace data for transmission via the Aurora port
- or to a DDR based trace buffer. In some configurations the NPC trace
- buffer can be the only trace buffer used.
-
-
-EXAMPLE
- dcsr-npc {
- compatible = "fsl,dcsr-npc";
- reg = <0x1000 0x1000 0x1000000 0x8000>;
- };
-
-=======================================================================
-Nexus Concentrator
-
-This node represents the region of DCSR space allocated to the NXC
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr-nxc"
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-nxc@2000 {
- compatible = "fsl,dcsr-nxc";
- reg = <0x2000 0x1000>;
- };
-=======================================================================
-CoreNet Debug Controller
-
-This node represents the region of DCSR space allocated to
-the CoreNet Debug controller.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr-corenet"
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
- The CoreNet Debug controller occupies two regions in the DCSR space
- with distinct functionality.
-
- The first register range describes the CoreNet Debug Controller
- functionalty to perform transaction and transaction attribute matches.
-
- The second register range describes the CoreNet Debug Controller
- functionalty to trigger event notifications and debug traces.
-
-EXAMPLE
- dcsr-corenet {
- compatible = "fsl,dcsr-corenet";
- reg = <0x8000 0x1000 0xB0000 0x1000>;
- };
-
-=======================================================================
-Data Path Debug controller
-
-This node represents the region of DCSR space allocated to
-the DPAA Debug Controller. This controller controls debug configuration
-for the QMAN and FMAN blocks.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include both an identifier specific to the SoC
- or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
- generic compatible string "fsl,dcsr-dpaa".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-dpaa@9000 {
- compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
- reg = <0x9000 0x1000>;
- };
-
-=======================================================================
-OCeaN Debug controller
-
-This node represents the region of DCSR space allocated to
-the OCN Debug Controller.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include both an identifier specific to the SoC
- or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
- generic compatible string "fsl,dcsr-ocn".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-ocn@11000 {
- compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
- reg = <0x11000 0x1000>;
- };
-
-=======================================================================
-DDR Controller Debug controller
-
-This node represents the region of DCSR space allocated to
-the OCN Debug Controller.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,dcsr-ddr"
-
- - dev-handle
- Usage: required
- Definition: A phandle to associate this debug node with its
- component controller.
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-ddr@12000 {
- compatible = "fsl,dcsr-ddr";
- dev-handle = <&ddr1>;
- reg = <0x12000 0x1000>;
- };
-
-=======================================================================
-Nexus Aurora Link Controller
-
-This node represents the region of DCSR space allocated to
-the NAL Controller.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include both an identifier specific to the SoC
- or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
- generic compatible string "fsl,dcsr-nal".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-nal@18000 {
- compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
- reg = <0x18000 0x1000>;
- };
-
-
-=======================================================================
-Run Control and Power Management
-
-This node represents the region of DCSR space allocated to
-the RCPM Debug Controller. This functionlity is limited to the
-control the debug operations of the SoC and cores.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include both an identifier specific to the SoC
- or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
- generic compatible string "fsl,dcsr-rcpm".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-rcpm@22000 {
- compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
- reg = <0x22000 0x1000>;
- };
-
-=======================================================================
-Core Service Bridge Proxy
-
-This node represents the region of DCSR space allocated to
-the Core Service Bridge Proxies.
-There is one Core Service Bridge Proxy device for each CPU in the system.
-This functionlity provides access to the debug operations of the CPU.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include both an identifier specific to the cpu
- of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
- generic compatible string "fsl,dcsr-cpu-sb-proxy".
-
- - cpu-handle
- Usage: required
- Definition: A phandle to associate this debug node with its cpu.
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- offset and length of the DCSR space registers of the device
- configuration block.
-
-EXAMPLE
- dcsr-cpu-sb-proxy@40000 {
- compatible = "fsl,dcsr-e500mc-sb-proxy",
- "fsl,dcsr-cpu-sb-proxy";
- cpu-handle = <&cpu0>;
- reg = <0x40000 0x1000>;
- };
- dcsr-cpu-sb-proxy@41000 {
- compatible = "fsl,dcsr-e500mc-sb-proxy",
- "fsl,dcsr-cpu-sb-proxy";
- cpu-handle = <&cpu1>;
- reg = <0x41000 0x1000>;
- };
-
-=======================================================================