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| author | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
|---|---|---|
| committer | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
| commit | 7d558cd9c7b18e4b16953265aa0da45e63f3b968 (patch) | |
| tree | 7135d5a810768c9c619346282ee9cfdf1765e225 /arch/tile/include/asm/cache.h | |
| parent | 985ef6b2108ed28ffd5f6630e1e0fce2e2a775f2 (diff) | |
| download | kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.gz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.xz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.zip | |
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/tile/include/asm/cache.h')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 392e5333dd8..a9a529964e0 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -27,11 +27,17 @@ #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) /* - * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN. + * TILEPro I/O is not always coherent (networking typically uses coherent + * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the + * L2 cacheline size helps ensure that kernel heap allocations are aligned. + * TILE-Gx I/O is always coherent when used on hash-for-home pages. + * + * However, it's possible at runtime to request not to use hash-for-home + * for the kernel heap, in which case the kernel will use flush-and-inval + * to manage coherence. As a result, we use L2_CACHE_BYTES for the + * DMA minimum alignment to avoid false sharing in the kernel heap. */ -#ifndef __tilegx__ #define ARCH_DMA_MINALIGN L2_CACHE_BYTES -#endif /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT |