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authorAnton Arapov <anton@redhat.com>2012-06-08 12:58:00 +0200
committerAnton Arapov <anton@redhat.com>2012-06-08 12:58:00 +0200
commit6792a3f47a2e42d7164292bf7f1a55cfc4c91652 (patch)
treeb90c002bfbbeaec92f5d8a2383dcabf6524016f7 /arch/m68k/include/asm/m527xsim.h
parentfe2895d3d55146cac65b273c0f83e2c7e543cd0e (diff)
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fedora kernel: b920e9b748c595f970bf80ede7832d39f8d567dav3.4.1-2
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/m68k/include/asm/m527xsim.h')
-rw-r--r--arch/m68k/include/asm/m527xsim.h53
1 files changed, 48 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 758810ef91e..83db8106f50 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,8 +38,29 @@
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+#define MCFINT2_VECBASE 128 /* Vector base number 2 */
+#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
+#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
+#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
+#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
+#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
/*
* SDRAM configuration registers.
*/
@@ -72,9 +93,9 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
-#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
-#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
@@ -84,6 +105,28 @@
#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
#define MCFFEC_SIZE1 0x800
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#ifdef CONFIG_M5271
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 99
+#define MCFQSPI_CS3 103
+#endif
+#ifdef CONFIG_M5275
+#define MCFQSPI_CS0 59
+#define MCFQSPI_CS1 60
+#define MCFQSPI_CS2 61
+#define MCFQSPI_CS3 62
+#endif
+
+/*
+ * GPIO module.
+ */
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
@@ -285,8 +328,8 @@
/*
* Reset Control Unit (relative to IPSBAR).
*/
-#define MCF_RCR 0x110000
-#define MCF_RSR 0x110001
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */