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authorAnton Arapov <anton@redhat.com>2012-10-29 11:15:37 +0100
committerAnton Arapov <anton@redhat.com>2012-10-29 11:15:37 +0100
commit7d558cd9c7b18e4b16953265aa0da45e63f3b968 (patch)
tree7135d5a810768c9c619346282ee9cfdf1765e225 /arch/blackfin/mach-bf609
parent985ef6b2108ed28ffd5f6630e1e0fce2e2a775f2 (diff)
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fedora kernel: cd394142aac30b5c751f25b517572e2448695641v3.6.3-2f17
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/blackfin/mach-bf609')
-rw-r--r--arch/blackfin/mach-bf609/Kconfig8
-rw-r--r--arch/blackfin/mach-bf609/Makefile4
-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c304
-rw-r--r--arch/blackfin/mach-bf609/clock.c3
-rw-r--r--arch/blackfin/mach-bf609/dpm.S157
-rw-r--r--arch/blackfin/mach-bf609/hibernate.S65
-rw-r--r--arch/blackfin/mach-bf609/include/mach/anomaly.h141
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF60x_base.h1
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h4
-rw-r--r--arch/blackfin/mach-bf609/include/mach/pm.h9
-rw-r--r--arch/blackfin/mach-bf609/ints-priority.c156
-rw-r--r--arch/blackfin/mach-bf609/pm.c130
13 files changed, 754 insertions, 230 deletions
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 2cb72724377..101b33ee9bb 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -51,6 +51,14 @@ config PINT5_ASSIGN
endmenu
+config SEC_IRQ_PRIORITY_LEVELS
+ int "SEC interrupt priority levels"
+ default 7
+ range 0 7
+ help
+ Devide the total number of interrupt priority levels into sub-levels.
+ There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
+
endmenu
endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
index 2a27f817454..234fe1b4bb0 100644
--- a/arch/blackfin/mach-bf609/Makefile
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -2,5 +2,5 @@
# arch/blackfin/mach-bf609/Makefile
#
-obj-y := dma.o clock.o
-obj-$(CONFIG_PM) += pm.o hibernate.o
+obj-y := dma.o clock.o ints-priority.o
+obj-$(CONFIG_PM) += pm.o dpm.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index ac64f47217c..c2cf1ae3118 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -677,11 +677,28 @@ int bf609_nor_flash_init(struct platform_device *dev)
return 0;
}
+void bf609_nor_flash_exit(struct platform_device *dev)
+{
+ const unsigned short pins[] = {
+ P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+ P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+ };
+
+ peripheral_free_list(pins);
+
+ bfin_write32(SMC_GCTL, 0);
+}
+
static struct physmap_flash_data ezkit_flash_data = {
.width = 2,
.parts = ezkit_partitions,
- .init = bf609_nor_flash_init,
+ .init = bf609_nor_flash_init,
+ .exit = bf609_nor_flash_exit,
.nr_parts = ARRAY_SIZE(ezkit_partitions),
+#ifdef CONFIG_ROMKERNEL
+ .probe_type = "map_rom",
+#endif
};
static struct resource ezkit_flash_resource = {
@@ -739,7 +756,7 @@ static struct bfin6xx_spi_chip spidev_chip_info = {
};
#endif
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
static struct platform_device bfin_i2s_pcm = {
.name = "bfin-i2s-pcm-audio",
.id = -1,
@@ -825,6 +842,12 @@ static struct adau1761_platform_data adau1761_info = {
static const unsigned short ppi_req[] = {
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
+ P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
+ P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
+#endif
P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
0,
};
@@ -855,7 +878,7 @@ static struct bcap_route vs6624_routes[] = {
},
};
-static const unsigned vs6624_ce_pin = GPIO_PD1;
+static const unsigned vs6624_ce_pin = GPIO_PE4;
static struct bfin_capture_config bfin_capture_data = {
.card_name = "BF609",
@@ -871,7 +894,128 @@ static struct bfin_capture_config bfin_capture_data = {
.ppi_info = &ppi_info,
.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
| EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- .blank_clocks = 8,
+ .blank_pixels = 4,
+};
+#endif
+
+#if defined(CONFIG_VIDEO_ADV7842) \
+ || defined(CONFIG_VIDEO_ADV7842_MODULE)
+#include <media/adv7842.h>
+
+static struct v4l2_input adv7842_inputs[] = {
+ {
+ .index = 0,
+ .name = "Composite",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .std = V4L2_STD_ALL,
+ .capabilities = V4L2_IN_CAP_STD,
+ },
+ {
+ .index = 1,
+ .name = "S-Video",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .std = V4L2_STD_ALL,
+ .capabilities = V4L2_IN_CAP_STD,
+ },
+ {
+ .index = 2,
+ .name = "Component",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+ },
+ {
+ .index = 3,
+ .name = "VGA",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+ },
+ {
+ .index = 4,
+ .name = "HDMI",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+ },
+};
+
+static struct bcap_route adv7842_routes[] = {
+ {
+ .input = 3,
+ .output = 0,
+ .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+ | EPPI_CTL_ACTIVE656),
+ },
+ {
+ .input = 4,
+ .output = 0,
+ },
+ {
+ .input = 2,
+ .output = 0,
+ },
+ {
+ .input = 1,
+ .output = 0,
+ },
+ {
+ .input = 0,
+ .output = 1,
+ .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+ | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
+ | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
+ },
+};
+
+static struct adv7842_output_format adv7842_opf[] = {
+ {
+ .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
+ .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
+ .op_656_range = 1,
+ .blank_data = 1,
+ .insert_av_codes = 1,
+ },
+ {
+ .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
+ .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
+ .op_656_range = 1,
+ .blank_data = 1,
+ },
+};
+
+static struct adv7842_platform_data adv7842_data = {
+ .opf = adv7842_opf,
+ .num_opf = ARRAY_SIZE(adv7842_opf),
+ .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
+ .prim_mode = ADV7842_PRIM_MODE_SDP,
+ .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
+ .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
+ .i2c_sdp_io = 0x40,
+ .i2c_sdp = 0x41,
+ .i2c_cp = 0x42,
+ .i2c_vdp = 0x43,
+ .i2c_afe = 0x44,
+ .i2c_hdmi = 0x45,
+ .i2c_repeater = 0x46,
+ .i2c_edid = 0x47,
+ .i2c_infoframe = 0x48,
+ .i2c_cec = 0x49,
+ .i2c_avlink = 0x4a,
+ .i2c_ex = 0x26,
+};
+
+static struct bfin_capture_config bfin_capture_data = {
+ .card_name = "BF609",
+ .inputs = adv7842_inputs,
+ .num_inputs = ARRAY_SIZE(adv7842_inputs),
+ .routes = adv7842_routes,
+ .i2c_adapter_id = 0,
+ .board_info = {
+ .type = "adv7842",
+ .addr = 0x20,
+ .platform_data = (void *)&adv7842_data,
+ },
+ .ppi_info = &ppi_info,
+ .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+ | EPPI_CTL_ACTIVE656),
};
#endif
@@ -883,6 +1027,80 @@ static struct platform_device bfin_capture_device = {
};
#endif
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+ || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_display.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req_disp[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const struct ppi_info ppi_info = {
+ .type = PPI_TYPE_EPPI3,
+ .dma_ch = CH_EPPI0_CH0,
+ .irq_err = IRQ_EPPI0_STAT,
+ .base = (void __iomem *)EPPI0_STAT,
+ .pin_req = ppi_req_disp,
+};
+
+#if defined(CONFIG_VIDEO_ADV7511) \
+ || defined(CONFIG_VIDEO_ADV7511_MODULE)
+#include <media/adv7511.h>
+
+static struct v4l2_output adv7511_outputs[] = {
+ {
+ .index = 0,
+ .name = "HDMI",
+ .type = V4L2_INPUT_TYPE_CAMERA,
+ .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+ },
+};
+
+static struct disp_route adv7511_routes[] = {
+ {
+ .output = 0,
+ },
+};
+
+static struct adv7511_platform_data adv7511_data = {
+ .edid_addr = 0x7e,
+ .i2c_ex = 0x25,
+};
+
+static struct bfin_display_config bfin_display_data = {
+ .card_name = "BF609",
+ .outputs = adv7511_outputs,
+ .num_outputs = ARRAY_SIZE(adv7511_outputs),
+ .routes = adv7511_routes,
+ .i2c_adapter_id = 0,
+ .board_info = {
+ .type = "adv7511",
+ .addr = 0x39,
+ .platform_data = (void *)&adv7511_data,
+ },
+ .ppi_info = &ppi_info,
+ .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+ | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
+ | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
+ | EPPI_CTL_NON656 | EPPI_CTL_DIR),
+};
+#endif
+
+static struct platform_device bfin_display_device = {
+ .name = "bfin_display",
+ .dev = {
+ .platform_data = &bfin_display_data,
+ },
+};
+#endif
+
#if defined(CONFIG_BFIN_CRC)
#define BFIN_CRC_NAME "bfin-crc"
@@ -947,6 +1165,39 @@ static struct platform_device bfin_crc1_device = {
};
#endif
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
+#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
+
+static struct resource bfin_crypto_crc_resources[] = {
+ {
+ .start = REG_CRC0_CTL,
+ .end = REG_CRC0_REVID+4,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_CRC0_DCNTEXP,
+ .end = IRQ_CRC0_DCNTEXP,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = CH_MEM_STREAM0_SRC_CRC0,
+ .end = CH_MEM_STREAM0_SRC_CRC0,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct platform_device bfin_crypto_crc_device = {
+ .name = BFIN_CRYPTO_CRC_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
+ .resource = bfin_crypto_crc_resources,
+ .dev = {
+ .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
+ },
+};
+#endif
+
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
.model = 7877,
@@ -963,6 +1214,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
@@ -981,10 +1254,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
{
.modalias = "ad7877",
.platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
+ .irq = IRQ_PD9,
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
- .chip_select = 2,
+ .chip_select = 4,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1050,7 +1323,7 @@ static struct resource bfin_spi1_resource[] = {
/* SPI controller data */
static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
- .num_chipselect = 4,
+ .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
@@ -1065,7 +1338,7 @@ static struct platform_device bf60x_spi_master0 = {
};
static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
- .num_chipselect = 4,
+ .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
@@ -1146,6 +1419,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
.platform_data = (void *)&adau1761_info
},
#endif
+#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+ {
+ I2C_BOARD_INFO("ssm2602", 0x1b),
+ },
+#endif
};
static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
@@ -1261,6 +1539,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
&bfin_crc0_device,
&bfin_crc1_device,
#endif
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+ &bfin_crypto_crc_device,
+#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
&bfin_device_gpiokeys,
@@ -1269,7 +1550,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&ezkit_flash_device,
#endif
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s_pcm,
#endif
#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
@@ -1284,6 +1565,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
|| defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
&bfin_capture_device,
#endif
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+ || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+ &bfin_display_device,
+#endif
+
};
static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index 7f8f529693a..437d56c8228 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -97,9 +97,10 @@ int wait_for_pll_align(void)
while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
- printk(KERN_DEBUG "fail to align clk\n");
+ printk(KERN_CRIT "fail to align clk\n");
return -1;
}
+
return 0;
}
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
new file mode 100644
index 00000000000..54d50c689db
--- /dev/null
+++ b/arch/blackfin/mach-bf609/dpm.S
@@ -0,0 +1,157 @@
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/dpmc.h>
+
+#include <asm/context.S>
+
+#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+
+.section .l1.text
+ENTRY(_enter_hibernate)
+ /* switch stack to L1 scratch, prepare for ddr srfr */
+ P0.H = HI(PM_STACK);
+ P0.L = LO(PM_STACK);
+ SP = P0;
+
+ call _bf609_ddr_sr;
+ call _bfin_hibernate_syscontrol;
+
+ P0.H = HI(DPM0_RESTORE4);
+ P0.L = LO(DPM0_RESTORE4);
+ P1.H = _bf609_pm_data;
+ P1.L = _bf609_pm_data;
+ [P0] = P1;
+
+ P0.H = HI(DPM0_CTL);
+ P0.L = LO(DPM0_CTL);
+ R3.H = HI(0x00000010);
+ R3.L = LO(0x00000010);
+
+ bfin_init_pm_bench_cycles;
+
+ [P0] = R3;
+
+ SSYNC;
+ENDPROC(_enter_hibernate)
+
+/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
+ * is disabled. This behavior differ from bf5xx serial processor.
+ */
+ENTRY(_dummy_deepsleep)
+ [--sp] = SYSCFG;
+ [--sp] = (R7:0,P5:0);
+ cli r0;
+
+ /* get wake up interrupt ID */
+ P0.l = LO(SEC_SCI_BASE + SEC_CSID);
+ P0.h = HI(SEC_SCI_BASE + SEC_CSID);
+ R0 = [P0];
+
+ /* ACK wake up interrupt in SEC */
+ P1.l = LO(SEC_END);
+ P1.h = HI(SEC_END);
+
+ [P1] = R0;
+ SSYNC;
+
+ /* restore EVT 11 entry */
+ p0.h = hi(EVT11);
+ p0.l = lo(EVT11);
+ p1.h = _evt_evt11;
+ p1.l = _evt_evt11;
+
+ [p0] = p1;
+ SSYNC;
+
+ (R7:0,P5:0) = [sp++];
+ SYSCFG = [sp++];
+ RTI;
+ENDPROC(_dummy_deepsleep)
+
+ENTRY(_enter_deepsleep)
+ LINK 0xC;
+ [--sp] = (R7:0,P5:0);
+
+ /* Change EVT 11 entry to dummy handler for wake up event */
+ p0.h = hi(EVT11);
+ p0.l = lo(EVT11);
+ p1.h = _dummy_deepsleep;
+ p1.l = _dummy_deepsleep;
+
+ [p0] = p1;
+
+ P0.H = HI(PM_STACK);
+ P0.L = LO(PM_STACK);
+
+ EX_SCRATCH_REG = SP;
+ SP = P0;
+
+ SSYNC;
+
+ /* should put ddr to self refresh mode before sleep */
+ call _bf609_ddr_sr;
+
+ /* Set DPM controller to deep sleep mode */
+ P0.H = HI(DPM0_CTL);
+ P0.L = LO(DPM0_CTL);
+ R3.H = HI(0x00000008);
+ R3.L = LO(0x00000008);
+ [P0] = R3;
+ CSYNC;
+
+ /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
+ r0.l = 0x800;
+ r0.h = 0;
+ sti r0;
+ SSYNC;
+
+ bfin_init_pm_bench_cycles;
+
+ /* Fall into deep sleep in idle*/
+ idle;
+ SSYNC;
+
+ /* Restore PLL after wake up from deep sleep */
+ call _bf609_resume_ccbuf;
+
+ /* turn ddr out of self refresh mode */
+ call _bf609_ddr_sr_exit;
+
+ SP = EX_SCRATCH_REG;
+
+ (R7:0,P5:0) = [SP++];
+ UNLINK;
+ RTS;
+ENDPROC(_enter_deepsleep)
+
+.section .text
+ENTRY(_bf609_hibernate)
+ bfin_cpu_reg_save;
+ bfin_core_mmr_save;
+
+ P0.H = _bf609_pm_data;
+ P0.L = _bf609_pm_data;
+ R1.H = 0xDEAD;
+ R1.L = 0xBEEF;
+ R2.H = .Lpm_resume_here;
+ R2.L = .Lpm_resume_here;
+ [P0++] = R1;
+ [P0++] = R2;
+ [P0++] = SP;
+
+ P1.H = _enter_hibernate;
+ P1.L = _enter_hibernate;
+
+ call (P1);
+.Lpm_resume_here:
+
+ bfin_core_mmr_restore;
+ bfin_cpu_reg_restore;
+
+ [--sp] = RETI; /* Clear Global Interrupt Disable */
+ SP += 4;
+
+ RTS;
+
+ENDPROC(_bf609_hibernate)
+
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S
deleted file mode 100644
index d37a532519c..00000000000
--- a/arch/blackfin/mach-bf609/hibernate.S
+++ /dev/null
@@ -1,65 +0,0 @@
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
- /* switch stack to L1 scratch, prepare for ddr srfr */
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
- SP = P0;
-
- call _bf609_ddr_sr;
- call _bfin_hibernate_syscontrol;
-
- P0.H = HI(DPM0_RESTORE4);
- P0.L = LO(DPM0_RESTORE4);
- P1.H = _bf609_pm_data;
- P1.L = _bf609_pm_data;
- [P0] = P1;
-
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000010);
- R3.L = LO(0x00000010);
-
- bfin_init_pm_bench_cycles;
-
- [P0] = R3;
-
- SSYNC;
-ENDPROC(_enter_hibernate_mode)
-
-.section .text
-ENTRY(_bf609_hibernate)
- bfin_cpu_reg_save;
- bfin_core_mmr_save;
-
- P0.H = _bf609_pm_data;
- P0.L = _bf609_pm_data;
- R1.H = 0xDEAD;
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1;
- [P0++] = R2;
- [P0++] = SP;
-
- P1.H = _enter_hibernate;
- P1.L = _enter_hibernate;
-
- call (P1);
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index bdd39aefb56..7a07374308a 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -5,126 +5,99 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2011 Analog Devices Inc.
+ * Copyright 2004-2012 Analog Devices Inc.
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
+ * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
*/
#if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
+# error will not work on BF609 silicon version
#endif
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
+#define ANOMALY_16000010 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
-#define ANOMALY_05000491 (1)
-/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
-#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
+#define ANOMALY_05000456 (0)
#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
index 6aac38544cc..f1a6afae1a7 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -2665,7 +2665,6 @@
#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
-
/* =========================
L2CTL Registers
========================= */
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index 127586b1e04..c32c8cc8db2 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -123,6 +123,8 @@
#define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS 6
+#define NR_PINTS 112
#ifndef __ASSEMBLY__
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index 0004552433b..23e74cdeeee 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -293,9 +293,13 @@
#define NR_MACH_IRQS (IRQ_PG15 + 1)
+#define SEC_SCTL_PRIO_OFFSET 8
+
#ifndef __ASSEMBLY__
#include <linux/types.h>
+extern u8 sec_int_priority[];
+
/*
* bfin pint registers layout
*/
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
index 036d9bdc889..3ca0fb96563 100644
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ b/arch/blackfin/mach-bf609/include/mach/pm.h
@@ -11,11 +11,14 @@
#include <linux/suspend.h>
-int bfin609_pm_enter(suspend_state_t state);
-int bf609_pm_prepare(void);
-void bf609_pm_finish(void);
+extern int bfin609_pm_enter(suspend_state_t state);
+extern int bf609_pm_prepare(void);
+extern void bf609_pm_finish(void);
void bf609_hibernate(void);
void bfin_sec_raise_irq(unsigned int sid);
void coreb_enable(void);
+
+int bf609_nor_flash_init(void);
+void bf609_nor_flash_exit(void);
#endif
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
new file mode 100644
index 00000000000..f68abb9aa79
--- /dev/null
+++ b/arch/blackfin/mach-bf609/ints-priority.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * Set up the interrupt priorities
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+u8 sec_int_priority[] = {
+ 255, /* IRQ_SEC_ERR */
+ 255, /* IRQ_CGU_EVT */
+ 254, /* IRQ_WATCH0 */
+ 254, /* IRQ_WATCH1 */
+ 253, /* IRQ_L2CTL0_ECC_ERR */
+ 253, /* IRQ_L2CTL0_ECC_WARN */
+ 253, /* IRQ_C0_DBL_FAULT */
+ 253, /* IRQ_C1_DBL_FAULT */
+ 252, /* IRQ_C0_HW_ERR */
+ 252, /* IRQ_C1_HW_ERR */
+ 255, /* IRQ_C0_NMI_L1_PARITY_ERR */
+ 255, /* IRQ_C1_NMI_L1_PARITY_ERR */
+
+ 50, /* IRQ_TIMER0 */
+ 50, /* IRQ_TIMER1 */
+ 50, /* IRQ_TIMER2 */
+ 50, /* IRQ_TIMER3 */
+ 50, /* IRQ_TIMER4 */
+ 50, /* IRQ_TIMER5 */
+ 50, /* IRQ_TIMER6 */
+ 50, /* IRQ_TIMER7 */
+ 50, /* IRQ_TIMER_STAT */
+ 0, /* IRQ_PINT0 */
+ 0, /* IRQ_PINT1 */
+ 0, /* IRQ_PINT2 */
+ 0, /* IRQ_PINT3 */
+ 0, /* IRQ_PINT4 */
+ 0, /* IRQ_PINT5 */
+ 0, /* IRQ_CNT */
+ 50, /* RQ_PWM0_TRIP */
+ 50, /* IRQ_PWM0_SYNC */
+ 50, /* IRQ_PWM1_TRIP */
+ 50, /* IRQ_PWM1_SYNC */
+ 0, /* IRQ_TWI0 */
+ 0, /* IRQ_TWI1 */
+ 10, /* IRQ_SOFT0 */
+ 10, /* IRQ_SOFT1 */
+ 10, /* IRQ_SOFT2 */
+ 10, /* IRQ_SOFT3 */
+ 0, /* IRQ_ACM_EVT_MISS */
+ 0, /* IRQ_ACM_EVT_COMPLETE */
+ 0, /* IRQ_CAN0_RX */
+ 0, /* IRQ_CAN0_TX */
+ 0, /* IRQ_CAN0_STAT */
+ 100, /* IRQ_SPORT0_TX */
+ 100, /* IRQ_SPORT0_TX_STAT */
+ 100, /* IRQ_SPORT0_RX */
+ 100, /* IRQ_SPORT0_RX_STAT */
+ 100, /* IRQ_SPORT1_TX */
+ 100, /* IRQ_SPORT1_TX_STAT */
+ 100, /* IRQ_SPORT1_RX */
+ 100, /* IRQ_SPORT1_RX_STAT */
+ 100, /* IRQ_SPORT2_TX */
+ 100, /* IRQ_SPORT2_TX_STAT */
+ 100, /* IRQ_SPORT2_RX */
+ 100, /* IRQ_SPORT2_RX_STAT */
+ 0, /* IRQ_SPI0_TX */
+ 0, /* IRQ_SPI0_RX */
+ 0, /* IRQ_SPI0_STAT */
+ 0, /* IRQ_SPI1_TX */
+ 0, /* IRQ_SPI1_RX */
+ 0, /* IRQ_SPI1_STAT */
+ 0, /* IRQ_RSI */
+ 0, /* IRQ_RSI_INT0 */
+ 0, /* IRQ_RSI_INT1 */
+ 0, /* DMA11 Data (SDU) */
+ 0, /* DMA12 Data (Reserved) */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 30, /* IRQ_EMAC0_STAT */
+ 0, /* EMAC0 Power (Reserved) */
+ 30, /* IRQ_EMAC1_STAT */
+ 0, /* EMAC1 Power (Reserved) */
+ 0, /* IRQ_LP0 */
+ 0, /* IRQ_LP0_STAT */
+ 0, /* IRQ_LP1 */
+ 0, /* IRQ_LP1_STAT */
+ 0, /* IRQ_LP2 */
+ 0, /* IRQ_LP2_STAT */
+ 0, /* IRQ_LP3 */
+ 0, /* IRQ_LP3_STAT */
+ 0, /* IRQ_UART0_TX */
+ 0, /* IRQ_UART0_RX */
+ 0, /* IRQ_UART0_STAT */
+ 0, /* IRQ_UART1_TX */
+ 0, /* IRQ_UART1_RX */
+ 0, /* IRQ_UART1_STAT */
+ 0, /* IRQ_MDMA0_SRC_CRC0 */
+ 0, /* IRQ_MDMA0_DEST_CRC0 */
+ 0, /* IRQ_CRC0_DCNTEXP */
+ 0, /* IRQ_CRC0_ERR */
+ 0, /* IRQ_MDMA1_SRC_CRC1 */
+ 0, /* IRQ_MDMA1_DEST_CRC1 */
+ 0, /* IRQ_CRC1_DCNTEXP */
+ 0, /* IRQ_CRC1_ERR */
+ 0, /* IRQ_MDMA2_SRC */
+ 0, /* IRQ_MDMA2_DEST */
+ 0, /* IRQ_MDMA3_SRC */
+ 0, /* IRQ_MDMA3_DEST */
+ 120, /* IRQ_EPPI0_CH0 */
+ 120, /* IRQ_EPPI0_CH1 */
+ 120, /* IRQ_EPPI0_STAT */
+ 120, /* IRQ_EPPI2_CH0 */
+ 120, /* IRQ_EPPI2_CH1 */
+ 120, /* IRQ_EPPI2_STAT */
+ 120, /* IRQ_EPPI1_CH0 */
+ 120, /* IRQ_EPPI1_CH1 */
+ 120, /* IRQ_EPPI1_STAT */
+ 120, /* IRQ_PIXC_CH0 */
+ 120, /* IRQ_PIXC_CH1 */
+ 120, /* IRQ_PIXC_CH2 */
+ 120, /* IRQ_PIXC_STAT */
+ 120, /* IRQ_PVP_CPDOB */
+ 120, /* IRQ_PVP_CPDOC */
+ 120, /* IRQ_PVP_CPSTAT */
+ 120, /* IRQ_PVP_CPCI */
+ 120, /* IRQ_PVP_STAT0 */
+ 120, /* IRQ_PVP_MPDO */
+ 120, /* IRQ_PVP_MPDI */
+ 120, /* IRQ_PVP_MPSTAT */
+ 120, /* IRQ_PVP_MPCI */
+ 120, /* IRQ_PVP_CPDOA */
+ 120, /* IRQ_PVP_STAT1 */
+ 0, /* IRQ_USB_STAT */
+ 0, /* IRQ_USB_DMA */
+ 0, /* IRQ_TRU_INT0 */
+ 0, /* IRQ_TRU_INT1 */
+ 0, /* IRQ_TRU_INT2 */
+ 0, /* IRQ_TRU_INT3 */
+ 0, /* IRQ_DMAC0_ERROR */
+ 0, /* IRQ_CGU0_ERROR */
+ 0, /* Reserved */
+ 0, /* IRQ_DPM */
+ 0, /* Reserved */
+ 0, /* IRQ_SWU0 */
+ 0, /* IRQ_SWU1 */
+ 0, /* IRQ_SWU2 */
+ 0, /* IRQ_SWU3 */
+ 0, /* IRQ_SWU4 */
+ 0, /* IRQ_SWU4 */
+ 0, /* IRQ_SWU6 */
+};
+
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
index b76966eb16a..dacafc163f7 100644
--- a/arch/blackfin/mach-bf609/pm.c
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -11,13 +11,14 @@
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/irq.h>
-
#include <linux/delay.h>
+#include <linux/syscore_ops.h>
#include <asm/dpmc.h>
#include <asm/pm.h>
#include <mach/pm.h>
#include <asm/blackfin.h>
+#include <asm/mem_init.h>
/***********************************************************/
/* */
@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void)
}
__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask)
+void bf609_ddr_sr(void)
{
- uint32_t dpm0_ctl;
-
- bfin_write32(DPM0_WAKE_EN, 0x10);
- bfin_write32(DPM0_WAKE_POL, 0x10);
- dpm0_ctl = 0x00000008;
- bfin_write32(DPM0_CTL, dpm0_ctl);
- SSYNC();
- __asm__ __volatile__( \
- ".align 8;" \
- "idle;" \
- : : \
- );
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- __asm__ __volatile__(
- "R0 = 0;"
- "CYCLES = R0;"
- "CYCLES2 = R0;"
- "R0 = SYSCFG;"
- "BITSET(R0, 1);"
- "SYSCFG = R0;"
- : : : "R0"
- );
-#endif
-
+ dmc_enter_self_refresh();
}
__attribute__((l1_text))
-void bf609_ddr_sr(void)
+void bf609_ddr_sr_exit(void)
{
- uint32_t reg;
-
- reg = bfin_read_DMC0_CTL();
- reg |= 0x8;
- bfin_write_DMC0_CTL(reg);
+ dmc_exit_self_refresh();
- while (!(bfin_read_DMC0_STAT() & 0x8))
+ /* After wake up from deep sleep and exit DDR from self refress mode,
+ * should wait till CGU PLL is locked.
+ */
+ while (bfin_read32(CGU0_STAT) & CLKSALGN)
continue;
}
__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
+void bf609_resume_ccbuf(void)
{
- uint32_t reg;
- while (!(bfin_read_DMC0_STAT() & 0x1))
- continue;
+ bfin_write32(DPM0_CCBF_EN, 3);
+ bfin_write32(DPM0_CTL, 2);
- reg = bfin_read_DMC0_CTL();
- reg &= ~0x8;
- bfin_write_DMC0_CTL(reg);
-
- while ((bfin_read_DMC0_STAT() & 0x8))
- continue;
+ while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
}
__attribute__((l1_text))
@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void)
bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
}
-#ifndef CONFIG_BF60x
-# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
-#else
-# define SIC_SYSIRQ(irq) ((irq) - IVG15)
-#endif
-void bfin_hibernate(unsigned long mask)
+#define IRQ_SID(irq) ((irq) - IVG15)
+asmlinkage void enter_deepsleep(void);
+
+__attribute__((l1_text))
+void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
{
- bfin_write32(DPM0_WAKE_EN, 0x10);
- bfin_write32(DPM0_WAKE_POL, 0x10);
+ bfin_write32(DPM0_WAKE_EN, mask);
+ bfin_write32(DPM0_WAKE_POL, pol_mask);
+ SSYNC();
+ enter_deepsleep();
+}
+
+void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
+{
+ bfin_write32(DPM0_WAKE_EN, mask);
+ bfin_write32(DPM0_WAKE_POL, pol_mask);
bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
bfin_write32(DPM0_HIB_DIS, 0xFFFF);
- printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
-
bf609_hibernate();
}
@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state)
printk(KERN_DEBUG "Unable to get irq wake\n");
if (state == PM_SUSPEND_STANDBY)
- bfin_deepsleep(wakeup);
+ bfin_deepsleep(wakeup, wakeup_pol);
else {
- bfin_hibernate(wakeup);
+ bfin_hibernate(wakeup, wakeup_pol);
}
+
}
int bf609_cpu_pm_prepare(void)
@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = {
.finish = bf609_cpu_pm_finish,
};
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static int smc_pm_syscore_suspend(void)
+{
+ bf609_nor_flash_exit();
+ return 0;
+}
+
+static void smc_pm_syscore_resume(void)
+{
+ bf609_nor_flash_init();
+}
+
+static struct syscore_ops smc_pm_syscore_ops = {
+ .suspend = smc_pm_syscore_suspend,
+ .resume = smc_pm_syscore_resume,
+};
+#endif
+
static irqreturn_t test_isr(int irq, void *dev_id)
{
printk(KERN_DEBUG "gpio irq %d\n", irq);
+ if (irq == 231)
+ bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1));
return IRQ_HANDLED;
}
static irqreturn_t dpm0_isr(int irq, void *dev_id)
{
- uint32_t wake_stat;
-
- wake_stat = bfin_read32(DPM0_WAKE_STAT);
- printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
-
- bfin_write32(DPM0_WAKE_STAT, wake_stat);
+ bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
+ bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
return IRQ_HANDLED;
}
@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void)
int irq;
int error;
-#if CONFIG_PM_BFIN_WAKE_PE12
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+ register_syscore_ops(&smc_pm_syscore_ops);
+#endif
+
+#ifdef CONFIG_PM_BFIN_WAKE_PE12
irq = gpio_to_irq(GPIO_PE12);
if (irq < 0) {
error = irq;
@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void)
GPIO_PE12, error);
}
- error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
+ error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
+ | IRQF_FORCE_RESUME, "gpiope12", NULL);
if(error < 0)
printk(KERN_DEBUG "Unable to get irq\n");
#endif
- error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
+ error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
+ IRQF_FORCE_RESUME, "cgu0 event", NULL);
if(error < 0)
printk(KERN_DEBUG "Unable to get irq\n");
- error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
+ error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
+ IRQF_FORCE_RESUME, "dpm0 event", NULL);
if (error < 0)
printk(KERN_DEBUG "Unable to get irq\n");