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| author | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
|---|---|---|
| committer | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
| commit | 7d558cd9c7b18e4b16953265aa0da45e63f3b968 (patch) | |
| tree | 7135d5a810768c9c619346282ee9cfdf1765e225 /arch/arm/plat-omap/counter_32k.c | |
| parent | 985ef6b2108ed28ffd5f6630e1e0fce2e2a775f2 (diff) | |
| download | kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.gz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.xz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.zip | |
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/arm/plat-omap/counter_32k.c')
| -rw-r--r-- | arch/arm/plat-omap/counter_32k.c | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 2132c4f389e..2bc51fb1f71 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -29,7 +29,10 @@ #include <plat/clock.h> /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ -#define OMAP2_32KSYNCNT_CR_OFF 0x10 +#define OMAP2_32KSYNCNT_REV_OFF 0x0 +#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) +#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 +#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 /* * 32KHz clocksource ... always available, on pretty most chips except @@ -52,22 +55,29 @@ static u32 notrace omap_32k_read_sched_clock(void) * nsecs and adds to a monotonically increasing timespec. */ static struct timespec persistent_ts; -static cycles_t cycles, last_cycles; +static cycles_t cycles; static unsigned int persistent_mult, persistent_shift; +static DEFINE_SPINLOCK(read_persistent_clock_lock); + static void omap_read_persistent_clock(struct timespec *ts) { unsigned long long nsecs; - cycles_t delta; - struct timespec *tsp = &persistent_ts; + cycles_t last_cycles; + unsigned long flags; + + spin_lock_irqsave(&read_persistent_clock_lock, flags); last_cycles = cycles; cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; - delta = cycles - last_cycles; - nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift); + nsecs = clocksource_cyc2ns(cycles - last_cycles, + persistent_mult, persistent_shift); + + timespec_add_ns(&persistent_ts, nsecs); + + *ts = persistent_ts; - timespec_add_ns(tsp, nsecs); - *ts = *tsp; + spin_unlock_irqrestore(&read_persistent_clock_lock, flags); } /** @@ -84,9 +94,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) int ret; /* - * 32k sync Counter register offset is at 0x10 + * 32k sync Counter IP register offsets vary between the + * highlander version and the legacy ones. + * The 'SCHEME' bits(30-31) of the revision register is used + * to identify the version. */ - sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF; + if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & + OMAP2_32KSYNCNT_REV_SCHEME) + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; + else + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; /* * 120000 rough estimate from the calculations in |