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authorAnton Arapov <anton@redhat.com>2012-04-16 10:05:28 +0200
committerAnton Arapov <anton@redhat.com>2012-04-16 10:05:28 +0200
commitb4b6116a13633898cf868f2f103c96a90c4c20f8 (patch)
tree93d1b7e2cfcdf473d8d4ff3ad141fa864f8491f6 /arch/arm/mach-vexpress
parentedd4be777c953e5faafc80d091d3084b4343f5d3 (diff)
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fedora kernel: d9aad82f3319f3cfd1aebc01234254ef0c37ad84v3.3.2-1
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/arm/mach-vexpress')
-rw-r--r--arch/arm/mach-vexpress/Kconfig14
-rw-r--r--arch/arm/mach-vexpress/Makefile8
-rw-r--r--arch/arm/mach-vexpress/Makefile.boot3
-rw-r--r--arch/arm/mach-vexpress/core.h19
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c253
-rw-r--r--arch/arm/mach-vexpress/hotplug.c124
-rw-r--r--arch/arm/mach-vexpress/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-vexpress/include/mach/ct-ca9x4.h50
-rw-r--r--arch/arm/mach-vexpress/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-vexpress/include/mach/entry-macro.S5
-rw-r--r--arch/arm/mach-vexpress/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-vexpress/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-vexpress/include/mach/io.h26
-rw-r--r--arch/arm/mach-vexpress/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-vexpress/include/mach/motherboard.h143
-rw-r--r--arch/arm/mach-vexpress/include/mach/system.h33
-rw-r--r--arch/arm/mach-vexpress/include/mach/timex.h23
-rw-r--r--arch/arm/mach-vexpress/include/mach/uncompress.h52
-rw-r--r--arch/arm/mach-vexpress/platsmp.c49
-rw-r--r--arch/arm/mach-vexpress/v2m.c454
20 files changed, 1298 insertions, 0 deletions
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
new file mode 100644
index 00000000000..88c3ba151e8
--- /dev/null
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -0,0 +1,14 @@
+menu "Versatile Express platform type"
+ depends on ARCH_VEXPRESS
+
+config ARCH_VEXPRESS_CA9X4
+ bool "Versatile Express Cortex-A9x4 tile"
+ select CPU_V7
+ select ARM_GIC
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select PL310_ERRATA_753970
+ select HAVE_SMP
+ select MIGHT_HAVE_CACHE_L2X0
+
+endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
new file mode 100644
index 00000000000..90551b9780a
--- /dev/null
+++ b/arch/arm/mach-vexpress/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y := v2m.o
+obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
+obj-$(CONFIG_SMP) += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
new file mode 100644
index 00000000000..8630b3d10a4
--- /dev/null
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y += 0x60008000
+params_phys-y := 0x60000100
+initrd_phys-y := 0x60800000
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
new file mode 100644
index 00000000000..f4397159c17
--- /dev/null
+++ b/arch/arm/mach-vexpress/core.h
@@ -0,0 +1,19 @@
+#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
+#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
+
+#define AMBA_DEVICE(name,busid,base,plat) \
+struct amba_device name##_device = { \
+ .dev = { \
+ .coherent_dma_mask = ~0UL, \
+ .init_name = busid, \
+ .platform_data = plat, \
+ }, \
+ .res = { \
+ .start = base, \
+ .end = base + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, \
+ .dma_mask = ~0UL, \
+ .irq = IRQ_##base, \
+ /* .dma = DMA_##base,*/ \
+}
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
new file mode 100644
index 00000000000..b1e87c184e5
--- /dev/null
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -0,0 +1,253 @@
+/*
+ * Versatile Express Core Tile Cortex A9x4 Support
+ */
+#include <linux/init.h>
+#include <linux/gfp.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clkdev.h>
+
+#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/pmu.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+
+#include <mach/ct-ca9x4.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include "core.h"
+
+#include <mach/motherboard.h>
+
+#include <plat/clcd.h>
+
+#define V2M_PA_CS7 0x10000000
+
+static struct map_desc ct_ca9x4_io_desc[] __initdata = {
+ {
+ .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
+ .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
+ .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
+ .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init ct_ca9x4_map_io(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = MMIO_P2V(A9_MPCORE_TWD);
+#endif
+ iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
+}
+
+static void __init ct_ca9x4_init_irq(void)
+{
+ gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
+ MMIO_P2V(A9_MPCORE_GIC_CPU));
+}
+
+#if 0
+static void __init ct_ca9x4_timer_init(void)
+{
+ writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
+ writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
+
+ sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
+ sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
+ "ct-timer0");
+}
+
+static struct sys_timer ct_ca9x4_timer = {
+ .init = ct_ca9x4_timer_init,
+};
+#endif
+
+static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
+{
+ v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
+ v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
+}
+
+static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
+{
+ unsigned long framesize = 1024 * 768 * 2;
+
+ fb->panel = versatile_clcd_get_panel("XVGA");
+ if (!fb->panel)
+ return -EINVAL;
+
+ return versatile_clcd_setup_dma(fb, framesize);
+}
+
+static struct clcd_board ct_ca9x4_clcd_data = {
+ .name = "CT-CA9X4",
+ .caps = CLCD_CAP_5551 | CLCD_CAP_565,
+ .check = clcdfb_check,
+ .decode = clcdfb_decode,
+ .enable = ct_ca9x4_clcd_enable,
+ .setup = ct_ca9x4_clcd_setup,
+ .mmap = versatile_clcd_mmap_dma,
+ .remove = versatile_clcd_remove_dma,
+};
+
+static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
+static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
+static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
+static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
+
+static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
+ &clcd_device,
+ &dmc_device,
+ &smc_device,
+ &gpio_device,
+};
+
+
+static long ct_round(struct clk *clk, unsigned long rate)
+{
+ return rate;
+}
+
+static int ct_set(struct clk *clk, unsigned long rate)
+{
+ return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
+}
+
+static const struct clk_ops osc1_clk_ops = {
+ .round = ct_round,
+ .set = ct_set,
+};
+
+static struct clk osc1_clk = {
+ .ops = &osc1_clk_ops,
+ .rate = 24000000,
+};
+
+static struct clk ct_sp804_clk = {
+ .rate = 1000000,
+};
+
+static struct clk_lookup lookups[] = {
+ { /* CLCD */
+ .dev_id = "ct:clcd",
+ .clk = &osc1_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "ct-timer0",
+ .clk = &ct_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "ct-timer1",
+ .clk = &ct_sp804_clk,
+ },
+};
+
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = IRQ_CT_CA9X4_PMU_CPU0,
+ .end = IRQ_CT_CA9X4_PMU_CPU0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = IRQ_CT_CA9X4_PMU_CPU1,
+ .end = IRQ_CT_CA9X4_PMU_CPU1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_CT_CA9X4_PMU_CPU2,
+ .end = IRQ_CT_CA9X4_PMU_CPU2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = IRQ_CT_CA9X4_PMU_CPU3,
+ .end = IRQ_CT_CA9X4_PMU_CPU3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
+static void __init ct_ca9x4_init_early(void)
+{
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}
+
+static void __init ct_ca9x4_init(void)
+{
+ int i;
+
+#ifdef CONFIG_CACHE_L2X0
+ void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+
+ /* set RAM latencies to 1 cycle for this core tile. */
+ writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+ writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+
+ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
+ amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
+
+ platform_device_register(&pmu_device);
+}
+
+#ifdef CONFIG_SMP
+static void __init ct_ca9x4_init_cpu_map(void)
+{
+ int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+
+ if (ncores > nr_cpu_ids) {
+ pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
+{
+ scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+}
+#endif
+
+struct ct_desc ct_ca9x4_desc __initdata = {
+ .id = V2M_CT_ID_CA9,
+ .name = "CA9x4",
+ .map_io = ct_ca9x4_map_io,
+ .init_early = ct_ca9x4_init_early,
+ .init_irq = ct_ca9x4_init_irq,
+ .init_tile = ct_ca9x4_init,
+#ifdef CONFIG_SMP
+ .init_cpu_map = ct_ca9x4_init_cpu_map,
+ .smp_enable = ct_ca9x4_smp_enable,
+#endif
+};
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
new file mode 100644
index 00000000000..3034a4dab4a
--- /dev/null
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -0,0 +1,124 @@
+/*
+ * linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/system.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ "mcr p15, 0, %1, c7, c5, 0\n"
+ " mcr p15, 0, %1, c7, c10, 4\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, %3\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile(
+ "mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+ /*
+ * there is no power-control hardware on this platform, so all
+ * we can do is put the core into WFI; this is safe as the calling
+ * code will have already disabled interrupts
+ */
+ for (;;) {
+ wfi();
+
+ if (pen_release == cpu_logical_map(cpu)) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * Getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * Just note it happening - when we're woken, we can report
+ * its occurrence.
+ */
+ (*spurious)++;
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+ int spurious = 0;
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu, &spurious);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+
+ if (spurious)
+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
new file mode 100644
index 00000000000..3f8307d73ca
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/clkdev.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#include <plat/clock.h>
+
+struct clk {
+ const struct clk_ops *ops;
+ unsigned long rate;
+ const struct icst_params *params;
+};
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
new file mode 100644
index 00000000000..a34d3d4faae
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -0,0 +1,50 @@
+#ifndef __MACH_CT_CA9X4_H
+#define __MACH_CT_CA9X4_H
+
+/*
+ * Physical base addresses
+ */
+#define CT_CA9X4_CLCDC (0x10020000)
+#define CT_CA9X4_AXIRAM (0x10060000)
+#define CT_CA9X4_DMC (0x100e0000)
+#define CT_CA9X4_SMC (0x100e1000)
+#define CT_CA9X4_SCC (0x100e2000)
+#define CT_CA9X4_SP804_TIMER (0x100e4000)
+#define CT_CA9X4_SP805_WDT (0x100e5000)
+#define CT_CA9X4_TZPC (0x100e6000)
+#define CT_CA9X4_GPIO (0x100e8000)
+#define CT_CA9X4_FASTAXI (0x100e9000)
+#define CT_CA9X4_SLOWAXI (0x100ea000)
+#define CT_CA9X4_TZASC (0x100ec000)
+#define CT_CA9X4_CORESIGHT (0x10200000)
+#define CT_CA9X4_MPIC (0x1e000000)
+#define CT_CA9X4_SYSTIMER (0x1e004000)
+#define CT_CA9X4_SYSWDT (0x1e007000)
+#define CT_CA9X4_L2CC (0x1e00a000)
+
+#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
+#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
+
+#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
+#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
+#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
+#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
+#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
+
+/*
+ * Interrupts. Those in {} are for AMBA devices
+ */
+#define IRQ_CT_CA9X4_CLCDC { 76 }
+#define IRQ_CT_CA9X4_DMC { -1 }
+#define IRQ_CT_CA9X4_SMC { 77, 78 }
+#define IRQ_CT_CA9X4_TIMER0 80
+#define IRQ_CT_CA9X4_TIMER1 81
+#define IRQ_CT_CA9X4_GPIO { 82 }
+#define IRQ_CT_CA9X4_PMU_CPU0 92
+#define IRQ_CT_CA9X4_PMU_CPU1 93
+#define IRQ_CT_CA9X4_PMU_CPU2 94
+#define IRQ_CT_CA9X4_PMU_CPU3 95
+
+extern struct ct_desc ct_ca9x4_desc;
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
new file mode 100644
index 00000000000..fd9e6c7ea49
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/* arch/arm/mach-realview/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG_LL_UART_OFFSET 0x00009000
+
+ .macro addruart,rp,rv,tmp
+ mov \rp, #DEBUG_LL_UART_OFFSET
+ orr \rv, \rp, #0xf8000000 @ virtual base
+ orr \rp, \rp, #0x10000000 @ physical base
+ .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
new file mode 100644
index 00000000000..a14f9e62ca9
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -0,0 +1,5 @@
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
diff --git a/arch/arm/mach-vexpress/include/mach/gpio.h b/arch/arm/mach-vexpress/include/mach/gpio.h
new file mode 100644
index 00000000000..40a8c178f10
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/hardware.h b/arch/arm/mach-vexpress/include/mach/hardware.h
new file mode 100644
index 00000000000..40a8c178f10
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/hardware.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
new file mode 100644
index 00000000000..13522d86685
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/io.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-vexpress/include/mach/io.h
+ *
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
new file mode 100644
index 00000000000..7054cbfc9de
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -0,0 +1,4 @@
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+#define NR_IRQS 128
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
new file mode 100644
index 00000000000..0a3a3751840
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -0,0 +1,143 @@
+#ifndef __MACH_MOTHERBOARD_H
+#define __MACH_MOTHERBOARD_H
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0 (V2M_PA_CS0)
+#define V2M_NOR1 (V2M_PA_CS1)
+#define V2M_SRAM (V2M_PA_CS2)
+#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
+#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
+#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
+
+/*
+ * Physical addresses, offset from V2M_PA_CS7
+ */
+#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000)
+#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000)
+#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000)
+
+#define V2M_AACI (V2M_PA_CS7 + 0x00004000)
+#define V2M_MMCI (V2M_PA_CS7 + 0x00005000)
+#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000)
+#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000)
+
+#define V2M_UART0 (V2M_PA_CS7 + 0x00009000)
+#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000)
+#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000)
+#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000)
+
+#define V2M_WDT (V2M_PA_CS7 + 0x0000f000)
+
+#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000)
+#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000)
+
+#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000)
+#define V2M_RTC (V2M_PA_CS7 + 0x00017000)
+
+#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
+#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
+
+#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
+#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
+#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
+#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
+#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
+#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
+#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
+#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
+#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
+#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
+#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
+#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
+#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
+#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
+#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
+#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
+#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
+#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
+#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
+
+#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
+#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
+
+#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
+#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
+
+
+/*
+ * Interrupts. Those in {} are for AMBA devices
+ */
+#define IRQ_V2M_WDT { (32 + 0) }
+#define IRQ_V2M_TIMER0 (32 + 2)
+#define IRQ_V2M_TIMER1 (32 + 2)
+#define IRQ_V2M_TIMER2 (32 + 3)
+#define IRQ_V2M_TIMER3 (32 + 3)
+#define IRQ_V2M_RTC { (32 + 4) }
+#define IRQ_V2M_UART0 { (32 + 5) }
+#define IRQ_V2M_UART1 { (32 + 6) }
+#define IRQ_V2M_UART2 { (32 + 7) }
+#define IRQ_V2M_UART3 { (32 + 8) }
+#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) }
+#define IRQ_V2M_AACI { (32 + 11) }
+#define IRQ_V2M_KMI0 { (32 + 12) }
+#define IRQ_V2M_KMI1 { (32 + 13) }
+#define IRQ_V2M_CLCD { (32 + 14) }
+#define IRQ_V2M_LAN9118 (32 + 15)
+#define IRQ_V2M_ISP1761 (32 + 16)
+#define IRQ_V2M_PCIE (32 + 17)
+
+
+/*
+ * Configuration
+ */
+#define SYS_CFG_START (1 << 31)
+#define SYS_CFG_WRITE (1 << 30)
+#define SYS_CFG_OSC (1 << 20)
+#define SYS_CFG_VOLT (2 << 20)
+#define SYS_CFG_AMP (3 << 20)
+#define SYS_CFG_TEMP (4 << 20)
+#define SYS_CFG_RESET (5 << 20)
+#define SYS_CFG_SCC (6 << 20)
+#define SYS_CFG_MUXFPGA (7 << 20)
+#define SYS_CFG_SHUTDOWN (8 << 20)
+#define SYS_CFG_REBOOT (9 << 20)
+#define SYS_CFG_DVIMODE (11 << 20)
+#define SYS_CFG_POWER (12 << 20)
+#define SYS_CFG_SITE_MB (0 << 16)
+#define SYS_CFG_SITE_DB1 (1 << 16)
+#define SYS_CFG_SITE_DB2 (2 << 16)
+#define SYS_CFG_STACK(n) ((n) << 12)
+
+#define SYS_CFG_ERR (1 << 1)
+#define SYS_CFG_COMPLETE (1 << 0)
+
+int v2m_cfg_write(u32 devfn, u32 data);
+int v2m_cfg_read(u32 devfn, u32 *data);
+
+/*
+ * Core tile IDs
+ */
+#define V2M_CT_ID_CA9 0x0c000191
+#define V2M_CT_ID_UNSUPPORTED 0xff000191
+#define V2M_CT_ID_MASK 0xff000fff
+
+struct ct_desc {
+ u32 id;
+ const char *name;
+ void (*map_io)(void);
+ void (*init_early)(void);
+ void (*init_irq)(void);
+ void (*init_tile)(void);
+#ifdef CONFIG_SMP
+ void (*init_cpu_map)(void);
+ void (*smp_enable)(unsigned int);
+#endif
+};
+
+extern struct ct_desc *ct_desc;
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/system.h b/arch/arm/mach-vexpress/include/mach/system.h
new file mode 100644
index 00000000000..f653a8e265b
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/system.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-vexpress/include/mach/system.h
+ *
+ * Copyright (C) 2003 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/timex.h b/arch/arm/mach-vexpress/include/mach/timex.h
new file mode 100644
index 00000000000..00029bacd43
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/timex.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-vexpress/include/mach/timex.h
+ *
+ * RealView architecture timex specifications
+ *
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
new file mode 100644
index 00000000000..7972c5748d0
--- /dev/null
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-vexpress/include/mach/uncompress.h
+ *
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
+#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
+#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
+#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
+
+#define get_uart_base() (0x10000000 + 0x00009000)
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+ unsigned long base = get_uart_base();
+
+ while (AMBA_UART_FR(base) & (1 << 5))
+ barrier();
+
+ AMBA_UART_DR(base) = c;
+}
+
+static inline void flush(void)
+{
+ unsigned long base = get_uart_base();
+
+ while (AMBA_UART_FR(base) & (1 << 3))
+ barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
new file mode 100644
index 00000000000..124ffb16909
--- /dev/null
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <mach/motherboard.h>
+#define V2M_PA_CS7 0x10000000
+
+#include "core.h"
+
+extern void versatile_secondary_startup(void);
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ ct_desc->init_cpu_map();
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ ct_desc->smp_enable(max_cpus);
+
+ /*
+ * Write the address of secondary startup into the
+ * system-wide flags register. The boot monitor waits
+ * until it receives a soft interrupt, and then the
+ * secondary CPU branches to this address.
+ */
+ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
+ writel(virt_to_phys(versatile_secondary_startup),
+ MMIO_P2V(V2M_SYS_FLAGSSET));
+}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
new file mode 100644
index 00000000000..b4a28ca0e50
--- /dev/null
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -0,0 +1,454 @@
+/*
+ * Versatile Express V2M Motherboard Support
+ */
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/smsc911x.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/usb/isp1760.h>
+#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/mach-types.h>
+#include <asm/sizes.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
+#include <asm/hardware/sp810.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/ct-ca9x4.h>
+#include <mach/motherboard.h>
+
+#include <plat/sched_clock.h>
+
+#include "core.h"
+
+#define V2M_PA_CS0 0x40000000
+#define V2M_PA_CS1 0x44000000
+#define V2M_PA_CS2 0x48000000
+#define V2M_PA_CS3 0x4c000000
+#define V2M_PA_CS7 0x10000000
+
+static struct map_desc v2m_io_desc[] __initdata = {
+ {
+ .virtual = __MMIO_P2V(V2M_PA_CS7),
+ .pfn = __phys_to_pfn(V2M_PA_CS7),
+ .length = SZ_128K,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init v2m_timer_init(void)
+{
+ u32 scctrl;
+
+ /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
+ scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
+ scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
+ writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+
+ writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
+ writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+
+ sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
+ sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
+ "v2m-timer0");
+}
+
+static struct sys_timer v2m_timer = {
+ .init = v2m_timer_init,
+};
+
+
+static DEFINE_SPINLOCK(v2m_cfg_lock);
+
+int v2m_cfg_write(u32 devfn, u32 data)
+{
+ /* Configuration interface broken? */
+ u32 val;
+
+ printk("%s: writing %08x to %08x\n", __func__, data, devfn);
+
+ devfn |= SYS_CFG_START | SYS_CFG_WRITE;
+
+ spin_lock(&v2m_cfg_lock);
+ val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+
+ writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
+ writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+
+ do {
+ val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ } while (val == 0);
+ spin_unlock(&v2m_cfg_lock);
+
+ return !!(val & SYS_CFG_ERR);
+}
+
+int v2m_cfg_read(u32 devfn, u32 *data)
+{
+ u32 val;
+
+ devfn |= SYS_CFG_START;
+
+ spin_lock(&v2m_cfg_lock);
+ writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
+ writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+
+ mb();
+
+ do {
+ cpu_relax();
+ val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ } while (val == 0);
+
+ *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+ spin_unlock(&v2m_cfg_lock);
+
+ return !!(val & SYS_CFG_ERR);
+}
+
+
+static struct resource v2m_pcie_i2c_resource = {
+ .start = V2M_SERIAL_BUS_PCI,
+ .end = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device v2m_pcie_i2c_device = {
+ .name = "versatile-i2c",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &v2m_pcie_i2c_resource,
+};
+
+static struct resource v2m_ddc_i2c_resource = {
+ .start = V2M_SERIAL_BUS_DVI,
+ .end = V2M_SERIAL_BUS_DVI + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device v2m_ddc_i2c_device = {
+ .name = "versatile-i2c",
+ .id = 1,
+ .num_resources = 1,
+ .resource = &v2m_ddc_i2c_resource,
+};
+
+static struct resource v2m_eth_resources[] = {
+ {
+ .start = V2M_LAN9118,
+ .end = V2M_LAN9118 + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_V2M_LAN9118,
+ .end = IRQ_V2M_LAN9118,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct smsc911x_platform_config v2m_eth_config = {
+ .flags = SMSC911X_USE_32BIT,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device v2m_eth_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .resource = v2m_eth_resources,
+ .num_resources = ARRAY_SIZE(v2m_eth_resources),
+ .dev.platform_data = &v2m_eth_config,
+};
+
+static struct resource v2m_usb_resources[] = {
+ {
+ .start = V2M_ISP1761,
+ .end = V2M_ISP1761 + SZ_128K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_V2M_ISP1761,
+ .end = IRQ_V2M_ISP1761,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct isp1760_platform_data v2m_usb_config = {
+ .is_isp1761 = true,
+ .bus_width_16 = false,
+ .port1_otg = true,
+ .analog_oc = false,
+ .dack_polarity_high = false,
+ .dreq_polarity_high = false,
+};
+
+static struct platform_device v2m_usb_device = {
+ .name = "isp1760",
+ .id = -1,
+ .resource = v2m_usb_resources,
+ .num_resources = ARRAY_SIZE(v2m_usb_resources),
+ .dev.platform_data = &v2m_usb_config,
+};
+
+static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
+{
+ writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+}
+
+static struct physmap_flash_data v2m_flash_data = {
+ .width = 4,
+ .set_vpp = v2m_flash_set_vpp,
+};
+
+static struct resource v2m_flash_resources[] = {
+ {
+ .start = V2M_NOR0,
+ .end = V2M_NOR0 + SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = V2M_NOR1,
+ .end = V2M_NOR1 + SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device v2m_flash_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .resource = v2m_flash_resources,
+ .num_resources = ARRAY_SIZE(v2m_flash_resources),
+ .dev.platform_data = &v2m_flash_data,
+};
+
+static struct pata_platform_info v2m_pata_data = {
+ .ioport_shift = 2,
+};
+
+static struct resource v2m_pata_resources[] = {
+ {
+ .start = V2M_CF,
+ .end = V2M_CF + 0xff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = V2M_CF + 0x100,
+ .end = V2M_CF + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device v2m_cf_device = {
+ .name = "pata_platform",
+ .id = -1,
+ .resource = v2m_pata_resources,
+ .num_resources = ARRAY_SIZE(v2m_pata_resources),
+ .dev.platform_data = &v2m_pata_data,
+};
+
+static unsigned int v2m_mmci_status(struct device *dev)
+{
+ return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+}
+
+static struct mmci_platform_data v2m_mmci_data = {
+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+ .status = v2m_mmci_status,
+};
+
+static AMBA_DEVICE(aaci, "mb:aaci", V2M_AACI, NULL);
+static AMBA_DEVICE(mmci, "mb:mmci", V2M_MMCI, &v2m_mmci_data);
+static AMBA_DEVICE(kmi0, "mb:kmi0", V2M_KMI0, NULL);
+static AMBA_DEVICE(kmi1, "mb:kmi1", V2M_KMI1, NULL);
+static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL);
+static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL);
+static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL);
+static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL);
+static AMBA_DEVICE(wdt, "mb:wdt", V2M_WDT, NULL);
+static AMBA_DEVICE(rtc, "mb:rtc", V2M_RTC, NULL);
+
+static struct amba_device *v2m_amba_devs[] __initdata = {
+ &aaci_device,
+ &mmci_device,
+ &kmi0_device,
+ &kmi1_device,
+ &uart0_device,
+ &uart1_device,
+ &uart2_device,
+ &uart3_device,
+ &wdt_device,
+ &rtc_device,
+};
+
+
+static long v2m_osc_round(struct clk *clk, unsigned long rate)
+{
+ return rate;
+}
+
+static int v2m_osc1_set(struct clk *clk, unsigned long rate)
+{
+ return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
+}
+
+static const struct clk_ops osc1_clk_ops = {
+ .round = v2m_osc_round,
+ .set = v2m_osc1_set,
+};
+
+static struct clk osc1_clk = {
+ .ops = &osc1_clk_ops,
+ .rate = 24000000,
+};
+
+static struct clk osc2_clk = {
+ .rate = 24000000,
+};
+
+static struct clk v2m_sp804_clk = {
+ .rate = 1000000,
+};
+
+static struct clk v2m_ref_clk = {
+ .rate = 32768,
+};
+
+static struct clk dummy_apb_pclk;
+
+static struct clk_lookup v2m_lookups[] = {
+ { /* AMBA bus clock */
+ .con_id = "apb_pclk",
+ .clk = &dummy_apb_pclk,
+ }, { /* UART0 */
+ .dev_id = "mb:uart0",
+ .clk = &osc2_clk,
+ }, { /* UART1 */
+ .dev_id = "mb:uart1",
+ .clk = &osc2_clk,
+ }, { /* UART2 */
+ .dev_id = "mb:uart2",
+ .clk = &osc2_clk,
+ }, { /* UART3 */
+ .dev_id = "mb:uart3",
+ .clk = &osc2_clk,
+ }, { /* KMI0 */
+ .dev_id = "mb:kmi0",
+ .clk = &osc2_clk,
+ }, { /* KMI1 */
+ .dev_id = "mb:kmi1",
+ .clk = &osc2_clk,
+ }, { /* MMC0 */
+ .dev_id = "mb:mmci",
+ .clk = &osc2_clk,
+ }, { /* CLCD */
+ .dev_id = "mb:clcd",
+ .clk = &osc1_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "mb:wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer0",
+ .clk = &v2m_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer1",
+ .clk = &v2m_sp804_clk,
+ },
+};
+
+static void __init v2m_init_early(void)
+{
+ ct_desc->init_early();
+ clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
+ versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+}
+
+static void v2m_power_off(void)
+{
+ if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
+ printk(KERN_EMERG "Unable to shutdown\n");
+}
+
+static void v2m_restart(char str, const char *cmd)
+{
+ if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+ printk(KERN_EMERG "Unable to reboot\n");
+}
+
+struct ct_desc *ct_desc;
+
+static struct ct_desc *ct_descs[] __initdata = {
+#ifdef CONFIG_ARCH_VEXPRESS_CA9X4
+ &ct_ca9x4_desc,
+#endif
+};
+
+static void __init v2m_populate_ct_desc(void)
+{
+ int i;
+ u32 current_tile_id;
+
+ ct_desc = NULL;
+ current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+
+ for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
+ if (ct_descs[i]->id == current_tile_id)
+ ct_desc = ct_descs[i];
+
+ if (!ct_desc)
+ panic("vexpress: failed to populate core tile description "
+ "for tile ID 0x%8x\n", current_tile_id);
+}
+
+static void __init v2m_map_io(void)
+{
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ v2m_populate_ct_desc();
+ ct_desc->map_io();
+}
+
+static void __init v2m_init_irq(void)
+{
+ ct_desc->init_irq();
+}
+
+static void __init v2m_init(void)
+{
+ int i;
+
+ platform_device_register(&v2m_pcie_i2c_device);
+ platform_device_register(&v2m_ddc_i2c_device);
+ platform_device_register(&v2m_flash_device);
+ platform_device_register(&v2m_cf_device);
+ platform_device_register(&v2m_eth_device);
+ platform_device_register(&v2m_usb_device);
+
+ for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
+ amba_device_register(v2m_amba_devs[i], &iomem_resource);
+
+ pm_power_off = v2m_power_off;
+
+ ct_desc->init_tile();
+}
+
+MACHINE_START(VEXPRESS, "ARM-Versatile Express")
+ .atag_offset = 0x100,
+ .map_io = v2m_map_io,
+ .init_early = v2m_init_early,
+ .init_irq = v2m_init_irq,
+ .timer = &v2m_timer,
+ .handle_irq = gic_handle_irq,
+ .init_machine = v2m_init,
+ .restart = v2m_restart,
+MACHINE_END