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authorAnton Arapov <anton@redhat.com>2012-06-08 12:58:00 +0200
committerAnton Arapov <anton@redhat.com>2012-06-08 12:58:00 +0200
commit6792a3f47a2e42d7164292bf7f1a55cfc4c91652 (patch)
treeb90c002bfbbeaec92f5d8a2383dcabf6524016f7 /arch/arm/mach-exynos
parentfe2895d3d55146cac65b273c0f83e2c7e543cd0e (diff)
downloadkernel-uprobes-6792a3f47a2e42d7164292bf7f1a55cfc4c91652.tar.gz
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fedora kernel: b920e9b748c595f970bf80ede7832d39f8d567dav3.4.1-2
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig57
-rw-r--r--arch/arm/mach-exynos/Makefile10
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1581
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h30
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c48
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c32
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1247
-rw-r--r--arch/arm/mach-exynos/clock.c1564
-rw-r--r--arch/arm/mach-exynos/common.c547
-rw-r--r--arch/arm/mach-exynos/common.h40
-rw-r--r--arch/arm/mach-exynos/cpuidle.c151
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c4
-rw-r--r--arch/arm/mach-exynos/dev-audio.c4
-rw-r--r--arch/arm/mach-exynos/dev-dwmci.c13
-rw-r--r--arch/arm/mach-exynos/dev-pd.c139
-rw-r--r--arch/arm/mach-exynos/dev-uart.c78
-rw-r--r--arch/arm/mach-exynos/dma.c155
-rw-r--r--arch/arm/mach-exynos/hotplug.c1
-rw-r--r--arch/arm/mach-exynos/include/mach/cpufreq.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S16
-rw-r--r--arch/arm/mach-exynos/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h239
-rw-r--r--arch/arm/mach-exynos/include/mach/io.h26
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h597
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h59
-rw-r--r--arch/arm/mach-exynos/include/mach/pmu.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h484
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h32
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c78
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c147
-rw-r--r--arch/arm/mach-exynos/mach-origen.c53
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c15
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c117
-rw-r--r--arch/arm/mach-exynos/mct.c62
-rw-r--r--arch/arm/mach-exynos/platsmp.c9
-rw-r--r--arch/arm/mach-exynos/pm.c55
-rw-r--r--arch/arm/mach-exynos/pm_domains.c201
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c9
43 files changed, 5323 insertions, 2681 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f68a0e..b8df521fb68 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
menu "SAMSUNG EXYNOS SoCs Support"
-choice
- prompt "EXYNOS System Type"
- default ARCH_EXYNOS4
-
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
+ default y
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 SoCs based systems
-endchoice
+config ARCH_EXYNOS5
+ bool "SAMSUNG EXYNOS5"
+ select HAVE_SMP
+ help
+ Samsung EXYNOS5 (Cortex-A15) SoC based systems
comment "EXYNOS SoCs"
@@ -34,6 +35,7 @@ config CPU_EXYNOS4210
select ARM_CPU_SUSPEND if PM
select S5P_PM if PM
select S5P_SLEEP if PM
+ select PM_GENERIC_DOMAINS
help
Enable EXYNOS4210 CPU support
@@ -41,6 +43,7 @@ config SOC_EXYNOS4212
bool "SAMSUNG EXYNOS4212"
default y
depends on ARCH_EXYNOS4
+ select SAMSUNG_DMADEV
select S5P_PM if PM
select S5P_SLEEP if PM
help
@@ -50,9 +53,17 @@ config SOC_EXYNOS4412
bool "SAMSUNG EXYNOS4412"
default y
depends on ARCH_EXYNOS4
+ select SAMSUNG_DMADEV
help
Enable EXYNOS4412 SoC support
+config SOC_EXYNOS5250
+ bool "SAMSUNG EXYNOS5250"
+ default y
+ depends on ARCH_EXYNOS5
+ help
+ Enable EXYNOS5250 SoC support
+
config EXYNOS4_MCT
bool
default y
@@ -74,11 +85,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.
-config EXYNOS4_DEV_PD
- bool
- help
- Compile in platform device definitions for Power Domain
-
config EXYNOS4_DEV_SYSMMU
bool
help
@@ -183,7 +189,9 @@ config MACH_SMDKV310
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
+ select S5P_DEV_G2D
select S5P_DEV_I2C_HDMIPHY
+ select S5P_DEV_JPEG
select S5P_DEV_MFC
select S5P_DEV_TV
select S5P_DEV_USB_EHCI
@@ -195,7 +203,6 @@ config MACH_SMDKV310
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_DMA
- select EXYNOS4_DEV_PD
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_USB_OHCI
select EXYNOS4_DEV_SYSMMU
@@ -225,12 +232,17 @@ config MACH_ARMLEX4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210
+ select S5P_HRT
+ select CLKSRC_MMIO
+ select HAVE_SCHED_CLOCK
select S5P_GPIO_INT
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
+ select S5P_DEV_G2D
select S5P_DEV_CSIS0
+ select S5P_DEV_JPEG
select S5P_DEV_FIMD0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
@@ -243,7 +255,6 @@ config MACH_UNIVERSAL_C210
select S5P_DEV_ONENAND
select S5P_DEV_TV
select EXYNOS4_DEV_DMA
- select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
@@ -268,21 +279,24 @@ config MACH_NURI
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
+ select S3C_DEV_I2C6
select S5P_DEV_CSIS0
+ select S5P_DEV_JPEG
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
+ select S5P_DEV_G2D
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
select S5P_SETUP_MIPIPHY
select EXYNOS4_DEV_DMA
- select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_FIMC
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
+ select EXYNOS4_SETUP_I2C6
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select S5P_SETUP_MIPIPHY
@@ -303,14 +317,15 @@ config MACH_ORIGEN
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S5P_DEV_FIMD0
+ select S5P_DEV_G2D
select S5P_DEV_I2C_HDMIPHY
+ select S5P_DEV_JPEG
select S5P_DEV_MFC
select S5P_DEV_TV
select S5P_DEV_USB_EHCI
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_DMA
- select EXYNOS4_DEV_PD
select EXYNOS4_DEV_USB_OHCI
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_SDHCI
@@ -333,6 +348,7 @@ config MACH_SMDK4212
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
+ select EXYNOS4_DEV_DMA
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C7
@@ -351,10 +367,11 @@ config MACH_SMDK4412
Machine support for Samsung SMDK4412
endif
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT
bool "Samsung Exynos4 Machine using device tree"
+ depends on ARCH_EXYNOS4
select CPU_EXYNOS4210
select USE_OF
select ARM_AMBA
@@ -365,6 +382,16 @@ config MACH_EXYNOS4_DT
Note: This is under development and not all peripherals can be supported
with this machine file.
+config MACH_EXYNOS5_DT
+ bool "SAMSUNG EXYNOS5 Machine using device tree"
+ depends on ARCH_EXYNOS5
+ select SOC_EXYNOS5250
+ select USE_OF
+ select ARM_AMBA
+ help
+ Machine support for Samsung Exynos4 machine with device tree enabled.
+ Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
if ARCH_EXYNOS4
comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb..8631840d1b5 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,11 +12,14 @@ obj- :=
# Core
-obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS) += common.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
@@ -40,18 +43,19 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
# device support
+obj-y += dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
-obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 00000000000..6efd1e5919f
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1581 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+ SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+ SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+ SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+ SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+ SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+ SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+ SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+ SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+ SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+ SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+ SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+ SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+ SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+
+static struct clk exynos4_clk_sclk_hdmi27m = {
+ .name = "sclk_hdmi27m",
+ .rate = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+};
+
+static struct clk exynos4_clk_sclk_usbphy0 = {
+ .name = "sclk_usbphy0",
+ .rate = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_usbphy1 = {
+ .name = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+ .name = "apb_pclk",
+ .id = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+ .clk = {
+ .name = "mout_apll",
+ },
+ .sources = &clk_src_apll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+ .clk = {
+ .name = "sclk_apll",
+ .parent = &exynos4_clk_mout_apll.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_mout_epll = {
+ .clk = {
+ .name = "mout_epll",
+ },
+ .sources = &clk_src_epll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+ .clk = {
+ .name = "mout_mpll",
+ },
+ .sources = &clk_src_mpll,
+
+ /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+ [0] = &exynos4_clk_mout_apll.clk,
+ [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+ .sources = exynos4_clkset_moutcore_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+ .clk = {
+ .name = "moutcore",
+ },
+ .sources = &exynos4_clkset_moutcore,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+ .clk = {
+ .name = "core_clk",
+ .parent = &exynos4_clk_moutcore.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+ .clk = {
+ .name = "armclk",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+ .clk = {
+ .name = "aclk_corem0",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+ .clk = {
+ .name = "aclk_cores",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+ .clk = {
+ .name = "aclk_corem1",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+ .clk = {
+ .name = "periphclk",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *exynos4_clkset_corebus_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+ .sources = exynos4_clkset_corebus_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+ .clk = {
+ .name = "mout_corebus",
+ },
+ .sources = &exynos4_clkset_mout_corebus,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+ .clk = {
+ .name = "sclk_dmc",
+ .parent = &exynos4_clk_mout_corebus.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+ .clk = {
+ .name = "aclk_cored",
+ .parent = &exynos4_clk_sclk_dmc.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+ .clk = {
+ .name = "aclk_corep",
+ .parent = &exynos4_clk_aclk_cored.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+ .clk = {
+ .name = "aclk_acp",
+ .parent = &exynos4_clk_mout_corebus.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+ .clk = {
+ .name = "pclk_acp",
+ .parent = &exynos4_clk_aclk_acp.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk = {
+ .sources = exynos4_clkset_aclk_top_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+ .clk = {
+ .name = "aclk_200",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+ .clk = {
+ .name = "aclk_100",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+ .clk = {
+ .name = "aclk_160",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+ .clk = {
+ .name = "aclk_133",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+ [0] = &clk_fin_vpll,
+ [1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+ .sources = exynos4_clkset_vpllsrc_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+ .clk = {
+ .name = "vpll_src",
+ .enable = exynos4_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_vpllsrc,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+ [0] = &exynos4_clk_vpllsrc.clk,
+ [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+ .sources = exynos4_clkset_sclk_vpll_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+ .clk = {
+ .name = "sclk_vpll",
+ },
+ .sources = &exynos4_clkset_sclk_vpll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+ {
+ .name = "timers",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1<<24),
+ }, {
+ .name = "csis",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "csis",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "jpeg",
+ .id = 0,
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.0",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.1",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.2",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.3",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "dwmmc",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "dac",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "mixer",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "vp",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "hdmiphy",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_hdmiphy_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "dacphy",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_dac_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "adc",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "keypad",
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "rtc",
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "watchdog",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "usbhost",
+ .enable = exynos4_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "otg",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "spi",
+ .devname = "s3c64xx-spi.0",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "s3c64xx-spi.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "s3c64xx-spi.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.0",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
+ .name = "ac97",
+ .devname = "samsung-ac97",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 27),
+ }, {
+ .name = "fimg2d",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "mfc",
+ .devname = "s5p-mfc",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.0",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.1",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.2",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.3",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.4",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.5",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.6",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.7",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-hdmiphy-i2c",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "SYSMMU_MDMA",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "SYSMMU_FIMC0",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "SYSMMU_FIMC1",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "SYSMMU_FIMC2",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "SYSMMU_FIMC3",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "SYSMMU_JPEG",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "SYSMMU_FIMD0",
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "SYSMMU_FIMD1",
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "SYSMMU_PCIe",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "SYSMMU_G2D",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "SYSMMU_ROTATOR",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "SYSMMU_TV",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "SYSMMU_MFC_L",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "SYSMMU_MFC_R",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 2),
+ }
+};
+
+static struct clk exynos4_init_clocks_on[] = {
+ {
+ .name = "uart",
+ .devname = "s5pv210-uart.0",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.3",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.4",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.5",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 5),
+ }
+};
+
+static struct clk exynos4_clk_pdma0 = {
+ .name = "dma",
+ .devname = "dma-pl330.0",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
+static struct clk exynos4_clk_pdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.1",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 1),
+};
+
+static struct clk exynos4_clk_mdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.2",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
+static struct clk exynos4_clk_fimd0 = {
+ .name = "fimd",
+ .devname = "exynos4-fb.0",
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &clk_xusbxti,
+ [2] = &exynos4_clk_sclk_hdmi27m,
+ [3] = &exynos4_clk_sclk_usbphy0,
+ [4] = &exynos4_clk_sclk_usbphy1,
+ [5] = &exynos4_clk_sclk_hdmiphy,
+ [6] = &exynos4_clk_mout_mpll.clk,
+ [7] = &exynos4_clk_mout_epll.clk,
+ [8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+ .sources = exynos4_clkset_group_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+ .sources = exynos4_clkset_mout_g2d0_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
+ .clk = {
+ .name = "mout_g2d0",
+ },
+ .sources = &exynos4_clkset_mout_g2d0,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+ [0] = &exynos4_clk_mout_epll.clk,
+ [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+ .sources = exynos4_clkset_mout_g2d1_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
+ .clk = {
+ .name = "mout_g2d1",
+ },
+ .sources = &exynos4_clkset_mout_g2d1,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+ [0] = &exynos4_clk_mout_g2d0.clk,
+ [1] = &exynos4_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+ .sources = exynos4_clkset_mout_g2d_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+ .sources = exynos4_clkset_mout_mfc0_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+ .clk = {
+ .name = "mout_mfc0",
+ },
+ .sources = &exynos4_clkset_mout_mfc0,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+ [0] = &exynos4_clk_mout_epll.clk,
+ [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+ .sources = exynos4_clkset_mout_mfc1_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+ .clk = {
+ .name = "mout_mfc1",
+ },
+ .sources = &exynos4_clkset_mout_mfc1,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+ [0] = &exynos4_clk_mout_mfc0.clk,
+ [1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+ .sources = exynos4_clkset_mout_mfc_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+ [0] = &exynos4_clk_sclk_vpll.clk,
+ [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+ .sources = exynos4_clkset_sclk_dac_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+ .clk = {
+ .name = "sclk_dac",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_sclk_dac,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .parent = &exynos4_clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+ [0] = &exynos4_clk_sclk_pixel.clk,
+ [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+ .sources = exynos4_clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_sclk_hdmi,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+ [0] = &exynos4_clk_sclk_dac.clk,
+ [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+ .sources = exynos4_clkset_sclk_mixer_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+ .clk = {
+ .name = "sclk_mixer",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_sclk_mixer,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+ &exynos4_clk_sclk_dac,
+ &exynos4_clk_sclk_pixel,
+ &exynos4_clk_sclk_hdmi,
+ &exynos4_clk_sclk_mixer,
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_pwm",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.2",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.3",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos4-fb.0",
+ .enable = exynos4_clksrc_mask_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimg2d",
+ },
+ .sources = &exynos4_clkset_mout_g2d,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_mfc",
+ .devname = "s5p-mfc",
+ },
+ .sources = &exynos4_clkset_mout_mfc,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_dwmmc",
+ .parent = &exynos4_clk_dout_mmc4.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+ }
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.0",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.1",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.2",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.3",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos4_clk_dout_mmc0.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos4_clk_dout_mmc1.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos4_clk_dout_mmc2.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos4_clk_dout_mmc3.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "s3c64xx-spi.2",
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+ &exynos4_clk_mout_apll,
+ &exynos4_clk_sclk_apll,
+ &exynos4_clk_mout_epll,
+ &exynos4_clk_mout_mpll,
+ &exynos4_clk_moutcore,
+ &exynos4_clk_coreclk,
+ &exynos4_clk_armclk,
+ &exynos4_clk_aclk_corem0,
+ &exynos4_clk_aclk_cores,
+ &exynos4_clk_aclk_corem1,
+ &exynos4_clk_periphclk,
+ &exynos4_clk_mout_corebus,
+ &exynos4_clk_sclk_dmc,
+ &exynos4_clk_aclk_cored,
+ &exynos4_clk_aclk_corep,
+ &exynos4_clk_aclk_acp,
+ &exynos4_clk_pclk_acp,
+ &exynos4_clk_vpllsrc,
+ &exynos4_clk_sclk_vpll,
+ &exynos4_clk_aclk_200,
+ &exynos4_clk_aclk_100,
+ &exynos4_clk_aclk_160,
+ &exynos4_clk_aclk_133,
+ &exynos4_clk_dout_mmc0,
+ &exynos4_clk_dout_mmc1,
+ &exynos4_clk_dout_mmc2,
+ &exynos4_clk_dout_mmc3,
+ &exynos4_clk_dout_mmc4,
+ &exynos4_clk_mout_mfc0,
+ &exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+ &exynos4_clk_pdma0,
+ &exynos4_clk_pdma1,
+ &exynos4_clk_mdma1,
+ &exynos4_clk_fimd0,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+ &exynos4_clk_sclk_uart0,
+ &exynos4_clk_sclk_uart1,
+ &exynos4_clk_sclk_uart2,
+ &exynos4_clk_sclk_uart3,
+ &exynos4_clk_sclk_mmc0,
+ &exynos4_clk_sclk_mmc1,
+ &exynos4_clk_sclk_mmc2,
+ &exynos4_clk_sclk_mmc3,
+ &exynos4_clk_sclk_spi0,
+ &exynos4_clk_sclk_spi1,
+ &exynos4_clk_sclk_spi2,
+
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+ CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+ CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+ CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+ CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
+ CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+ CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+ CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+ CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+ if (soc_is_exynos4210())
+ return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+ pll_4508);
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+ else
+ return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+ .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 exynos4_vpll_div[][8] = {
+ { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
+ { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int vpll_con0, vpll_con1 = 0;
+ unsigned int i;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+ vpll_con0 &= ~(0x1 << 27 | \
+ PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
+ PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+ PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+ vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
+ PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+ PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+ if (exynos4_vpll_div[i][0] == rate) {
+ vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+ __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+ /* Wait for VPLL lock */
+ while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+ continue;
+
+ clk->rate = rate;
+ return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+ .get_rate = exynos4_vpll_get_rate,
+ .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+ struct clk *xtal_clk;
+ unsigned long apll = 0;
+ unsigned long mpll = 0;
+ unsigned long epll = 0;
+ unsigned long vpll = 0;
+ unsigned long vpllsrc;
+ unsigned long xtal;
+ unsigned long armclk;
+ unsigned long sclk_dmc;
+ unsigned long aclk_200;
+ unsigned long aclk_100;
+ unsigned long aclk_160;
+ unsigned long aclk_133;
+ unsigned int ptr;
+
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+ xtal_clk = clk_get(NULL, "xtal");
+ BUG_ON(IS_ERR(xtal_clk));
+
+ xtal = clk_get_rate(xtal_clk);
+
+ xtal_rate = xtal;
+
+ clk_put(xtal_clk);
+
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+ if (soc_is_exynos4210()) {
+ apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+ pll_4508);
+ mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+ pll_4508);
+ epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+ __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+ vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+ vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+ __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+ __raw_readl(EXYNOS4_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+ __raw_readl(EXYNOS4_VPLL_CON1));
+ } else {
+ /* nothing */
+ }
+
+ clk_fout_apll.ops = &exynos4_fout_apll_ops;
+ clk_fout_mpll.rate = mpll;
+ clk_fout_epll.rate = epll;
+ clk_fout_vpll.ops = &exynos4_vpll_ops;
+ clk_fout_vpll.rate = vpll;
+
+ printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+ apll, mpll, epll, vpll);
+
+ armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+ sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+ aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+ aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+ aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+ aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+ printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+ "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+ armclk, sclk_dmc, aclk_200,
+ aclk_100, aclk_160, aclk_133);
+
+ clk_f.rate = armclk;
+ clk_h.rate = sclk_dmc;
+ clk_p.rate = aclk_100;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+ s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+ &exynos4_clk_sclk_hdmi27m,
+ &exynos4_clk_sclk_hdmiphy,
+ &exynos4_clk_sclk_usbphy0,
+ &exynos4_clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+ return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4_clock_syscore_ops = {
+ .suspend = exynos4_clock_suspend,
+ .resume = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+ int ptr;
+
+ s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+ s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+ s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+ s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+
+ s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+ s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+
+ s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+ s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+
+ s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+ s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+ clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+
+ register_syscore_ops(&exynos4_clock_syscore_ops);
+ s3c24xx_register_clock(&dummy_apb_pclk);
+
+ s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 00000000000..cb71c29c14d
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 13312ccb2d9..3b131e4b6ef 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
/*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
#include "common.h"
+#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = {
- SAVE_ITEM(S5P_CLKSRC_IMAGE),
- SAVE_ITEM(S5P_CLKSRC_LCD1),
- SAVE_ITEM(S5P_CLKDIV_IMAGE),
- SAVE_ITEM(S5P_CLKDIV_LCD1),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
- SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+ SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+ SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+ SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
};
#endif
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
- return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+ return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
- .sources = &clkset_mout_corebus,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ .sources = &exynos4_clkset_mout_corebus,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
},
};
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
{
.name = "sataphy",
.id = -1,
- .parent = &clk_aclk_133.clk,
+ .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sata",
.id = -1,
- .parent = &clk_aclk_133.clk,
+ .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
#define exynos4210_clock_resume NULL
#endif
-struct syscore_ops exynos4210_clock_syscore_ops = {
+static struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
{
int ptr;
- clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
- clk_mout_mpll.reg_src.shift = 8;
- clk_mout_mpll.reg_src.size = 1;
+ exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+ exynos4_clk_mout_mpll.reg_src.shift = 8;
+ exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 48af28566fa..3ecc01e06f7 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
/*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
#include "common.h"
+#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = {
- SAVE_ITEM(S5P_CLKSRC_IMAGE),
- SAVE_ITEM(S5P_CLKDIV_IMAGE),
- SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+ SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+ SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+ SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+ SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
};
#endif
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
- [1] = &clk_mout_mpll.clk,
+ [1] = &exynos4_clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
.name = "mout_mpll_user",
},
.sources = &clk_src_mpll_user,
- .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};
static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
#define exynos4212_clock_resume NULL
#endif
-struct syscore_ops exynos4212_clock_syscore_ops = {
+static struct syscore_ops exynos4212_clock_syscore_ops = {
.suspend = exynos4212_clock_suspend,
.resume = exynos4212_clock_resume,
};
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
int ptr;
/* usbphy1 is removed */
- clkset_group_list[4] = NULL;
+ exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used */
- clkset_group_list[6] = &clk_mout_mpll_user.clk;
- clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+ exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+ exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
- clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
- clk_mout_mpll.reg_src.shift = 12;
- clk_mout_mpll.reg_src.size = 1;
+ exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+ exynos4_clk_mout_mpll.reg_src.shift = 12;
+ exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 00000000000..7ac6ff4c46b
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+ /* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+ .name = "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+ .name = "sclk_hdmi24m",
+ .rate = 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+ .name = "sclk_hdmi27m",
+ .rate = 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+ .name = "sclk_usbphy",
+ .rate = 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+ .clk = {
+ .name = "mout_apll",
+ },
+ .sources = &clk_src_apll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+ .clk = {
+ .name = "sclk_apll",
+ .parent = &exynos5_clk_mout_apll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+ .clk = {
+ .name = "mout_bpll",
+ },
+ .sources = &clk_src_bpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+ .sources = exynos5_clk_src_bpll_user_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+ .clk = {
+ .name = "mout_bpll_user",
+ },
+ .sources = &exynos5_clk_src_bpll_user,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+ .clk = {
+ .name = "mout_cpll",
+ },
+ .sources = &clk_src_cpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+ .clk = {
+ .name = "mout_epll",
+ },
+ .sources = &clk_src_epll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+ .clk = {
+ .name = "mout_mpll",
+ },
+ .sources = &clk_src_mpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+ [0] = &clk_fin_vpll,
+ [1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+ .sources = exynos_clkset_vpllsrc_list,
+ .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+ .clk = {
+ .name = "vpll_src",
+ .enable = exynos5_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_vpllsrc,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+ [0] = &exynos5_clk_vpllsrc.clk,
+ [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+ .sources = exynos5_clkset_sclk_vpll_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+ .clk = {
+ .name = "sclk_vpll",
+ },
+ .sources = &exynos5_clkset_sclk_vpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .parent = &exynos5_clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+ [0] = &exynos5_clk_sclk_pixel.clk,
+ [1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+ .sources = exynos5_clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos5_clkset_sclk_hdmi,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+ &exynos5_clk_sclk_pixel,
+ &exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+ .sources = exynos5_clk_src_mpll_user_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+ .clk = {
+ .name = "mout_mpll_user",
+ },
+ .sources = &exynos5_clk_src_mpll_user,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+ [0] = &exynos5_clk_mout_apll.clk,
+ [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+ .sources = exynos5_clkset_mout_cpu_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+ .clk = {
+ .name = "mout_cpu",
+ },
+ .sources = &exynos5_clkset_mout_cpu,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+ .clk = {
+ .name = "dout_armclk",
+ .parent = &exynos5_clk_mout_cpu.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+ .clk = {
+ .name = "dout_arm2clk",
+ .parent = &exynos5_clk_dout_armclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+ .name = "armclk",
+ .parent = &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+ .sources = exynos5_clkset_cdrex_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+ .clk = {
+ .name = "clk_cdrex",
+ },
+ .sources = &exynos5_clkset_cdrex,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+ .clk = {
+ .name = "aclk_acp",
+ .parent = &exynos5_clk_mout_mpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+ .clk = {
+ .name = "pclk_acp",
+ .parent = &exynos5_clk_aclk_acp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+ [0] = &exynos5_clk_mout_mpll_user.clk,
+ [1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+ .sources = exynos5_clkset_aclk_top_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+ .clk = {
+ .name = "aclk_400",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+ [0] = &exynos5_clk_mout_cpll.clk,
+ [1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+ .sources = exynos5_clkset_aclk_333_166_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+ .clk = {
+ .name = "aclk_333",
+ },
+ .sources = &exynos5_clkset_aclk_333_166,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+ .clk = {
+ .name = "aclk_166",
+ },
+ .sources = &exynos5_clkset_aclk_333_166,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+ .clk = {
+ .name = "aclk_266",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+ .clk = {
+ .name = "aclk_200",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+ .clk = {
+ .name = "aclk_66_pre",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+ .clk = {
+ .name = "aclk_66",
+ .parent = &exynos5_clk_aclk_66_pre.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+ {
+ .name = "timers",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 24),
+ }, {
+ .name = "rtc",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "dwmci",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "sata",
+ .devname = "ahci",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "sata_phy",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ }, {
+ .name = "sata_phy_i2c",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 25),
+ }, {
+ .name = "mfc",
+ .devname = "s5p-mfc",
+ .enable = exynos5_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .devname = "exynos4-hdmi",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "mixer",
+ .devname = "s5p-mixer",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "jpeg",
+ .enable = exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "dsim0",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 22),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 23),
+ }, {
+ .name = "spdif",
+ .devname = "samsung-spdif",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 26),
+ }, {
+ .name = "ac97",
+ .devname = "samsung-ac97",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 27),
+ }, {
+ .name = "usbhost",
+ .enable = exynos5_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "usbotg",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "gps",
+ .enable = exynos5_clk_ip_gps_ctrl,
+ .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
+ }, {
+ .name = "nfcon",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 22),
+ }, {
+ .name = "iop",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
+ }, {
+ .name = "core_iop",
+ .enable = exynos5_clk_ip_core_ctrl,
+ .ctrlbit = ((1 << 21) | (1 << 3)),
+ }, {
+ .name = "mcu_iop",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.3",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.4",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.5",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.6",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.7",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-hdmiphy-i2c",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 14),
+ }
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+ {
+ .name = "uart",
+ .devname = "s5pv210-uart.0",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.3",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.4",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.5",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 5),
+ }
+};
+
+static struct clk exynos5_clk_pdma0 = {
+ .name = "dma",
+ .devname = "dma-pl330.0",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.1",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 2),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.2",
+ .enable = exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 4),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = NULL,
+ [2] = &exynos5_clk_sclk_hdmi24m,
+ [3] = &exynos5_clk_sclk_dptxphy,
+ [4] = &exynos5_clk_sclk_usbphy,
+ [5] = &exynos5_clk_sclk_hdmiphy,
+ [6] = &exynos5_clk_mout_mpll_user.clk,
+ [7] = &exynos5_clk_mout_epll.clk,
+ [8] = &exynos5_clk_sclk_vpll.clk,
+ [9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+ .sources = exynos5_clkset_group_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+ .sources = clk_src_gscl_266_list,
+ .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.0",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.1",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.2",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.3",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos5_clk_dout_mmc0.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos5_clk_dout_mmc1.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos5_clk_dout_mmc2.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos5_clk_dout_mmc3.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_dwmci",
+ .parent = &exynos5_clk_dout_mmc4.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "s3cfb.1",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "aclk_266_gscl",
+ },
+ .sources = &clk_src_gscl_266,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+ }, {
+ .clk = {
+ .name = "sclk_g3d",
+ .devname = "mali-t604.0",
+ .enable = exynos5_clk_block_ctrl,
+ .ctrlbit = (1 << 1),
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_gscl_wrap",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_gscl_wrap",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam0",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam1",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_jpeg",
+ .parent = &exynos5_clk_mout_cpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+ &exynos5_clk_mout_apll,
+ &exynos5_clk_sclk_apll,
+ &exynos5_clk_mout_bpll,
+ &exynos5_clk_mout_bpll_user,
+ &exynos5_clk_mout_cpll,
+ &exynos5_clk_mout_epll,
+ &exynos5_clk_mout_mpll,
+ &exynos5_clk_mout_mpll_user,
+ &exynos5_clk_vpllsrc,
+ &exynos5_clk_sclk_vpll,
+ &exynos5_clk_mout_cpu,
+ &exynos5_clk_dout_armclk,
+ &exynos5_clk_dout_arm2clk,
+ &exynos5_clk_cdrex,
+ &exynos5_clk_aclk_400,
+ &exynos5_clk_aclk_333,
+ &exynos5_clk_aclk_266,
+ &exynos5_clk_aclk_200,
+ &exynos5_clk_aclk_166,
+ &exynos5_clk_aclk_66_pre,
+ &exynos5_clk_aclk_66,
+ &exynos5_clk_dout_mmc0,
+ &exynos5_clk_dout_mmc1,
+ &exynos5_clk_dout_mmc2,
+ &exynos5_clk_dout_mmc3,
+ &exynos5_clk_dout_mmc4,
+ &exynos5_clk_aclk_acp,
+ &exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+ &exynos5_clk_pdma0,
+ &exynos5_clk_pdma1,
+ &exynos5_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+ &exynos5_clk_sclk_uart0,
+ &exynos5_clk_sclk_uart1,
+ &exynos5_clk_sclk_uart2,
+ &exynos5_clk_sclk_uart3,
+ &exynos5_clk_sclk_mmc0,
+ &exynos5_clk_sclk_mmc1,
+ &exynos5_clk_sclk_mmc2,
+ &exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+ CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+ CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+ CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+ CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+ CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+ CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+ &exynos5_clk_sclk_hdmi27m,
+ &exynos5_clk_sclk_hdmiphy,
+ &clk_fout_bpll,
+ &clk_fout_cpll,
+ &exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 180000000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int tmp;
+ unsigned int epll_rate;
+ unsigned int locktime;
+ unsigned int lockcnt;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ if (clk->parent)
+ epll_rate = clk_get_rate(clk->parent);
+ else
+ epll_rate = clk_ext_xtal_mux.rate;
+
+ if (epll_rate != 24000000) {
+ pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+ return -EINVAL;
+ }
+
+ epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+ epll_con &= ~(0x1 << 27 | \
+ PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
+ PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+ PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+ if (epll_div[i][0] == rate) {
+ epll_con_k = epll_div[i][5] << 0;
+ epll_con |= epll_div[i][1] << 27;
+ epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+ epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+ epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(epll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ epll_rate /= 1000000;
+
+ /* 3000 max_cycls : specification data */
+ locktime = 3000 / epll_rate * epll_div[i][3];
+ lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+ __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+ __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+ __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+ do {
+ tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+ } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+ .get_rate = exynos5_epll_get_rate,
+ .set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+ .get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+ return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+ .suspend = exynos5_clock_suspend,
+ .resume = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+ struct clk *xtal_clk;
+ unsigned long apll;
+ unsigned long bpll;
+ unsigned long cpll;
+ unsigned long mpll;
+ unsigned long epll;
+ unsigned long vpll;
+ unsigned long vpllsrc;
+ unsigned long xtal;
+ unsigned long armclk;
+ unsigned long mout_cdrex;
+ unsigned long aclk_400;
+ unsigned long aclk_333;
+ unsigned long aclk_266;
+ unsigned long aclk_200;
+ unsigned long aclk_166;
+ unsigned long aclk_66;
+ unsigned int ptr;
+
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+ xtal_clk = clk_get(NULL, "xtal");
+ BUG_ON(IS_ERR(xtal_clk));
+
+ xtal = clk_get_rate(xtal_clk);
+
+ xtal_rate = xtal;
+
+ clk_put(xtal_clk);
+
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+ apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+ bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+ cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+ __raw_readl(EXYNOS5_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+ __raw_readl(EXYNOS5_VPLL_CON1));
+
+ clk_fout_apll.ops = &exynos5_fout_apll_ops;
+ clk_fout_bpll.rate = bpll;
+ clk_fout_cpll.rate = cpll;
+ clk_fout_mpll.rate = mpll;
+ clk_fout_epll.rate = epll;
+ clk_fout_vpll.rate = vpll;
+
+ printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+ "M=%ld, E=%ld V=%ld",
+ apll, bpll, cpll, mpll, epll, vpll);
+
+ armclk = clk_get_rate(&exynos5_clk_armclk);
+ mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+ aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+ aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+ aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+ aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+ aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+ aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+ printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+ "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+ "ACLK166=%ld, ACLK66=%ld\n",
+ armclk, mout_cdrex, aclk_400,
+ aclk_333, aclk_266, aclk_200,
+ aclk_166, aclk_66);
+
+
+ clk_fout_epll.ops = &exynos5_epll_ops;
+
+ if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+ printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+ clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+ clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+ clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+ clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+ clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+ s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+ int ptr;
+
+ s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+ s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+ s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+ s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+ s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+ s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+ s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+ s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+ s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+ s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+ clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+ register_syscore_ops(&exynos5_clock_syscore_ops);
+ s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 187287aa57a..00000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1564 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
- SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
- SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
- SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_CLKSRC_TOP0),
- SAVE_ITEM(S5P_CLKSRC_TOP1),
- SAVE_ITEM(S5P_CLKSRC_CAM),
- SAVE_ITEM(S5P_CLKSRC_TV),
- SAVE_ITEM(S5P_CLKSRC_MFC),
- SAVE_ITEM(S5P_CLKSRC_G3D),
- SAVE_ITEM(S5P_CLKSRC_LCD0),
- SAVE_ITEM(S5P_CLKSRC_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_FSYS),
- SAVE_ITEM(S5P_CLKSRC_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_CAM),
- SAVE_ITEM(S5P_CLKDIV_TV),
- SAVE_ITEM(S5P_CLKDIV_MFC),
- SAVE_ITEM(S5P_CLKDIV_G3D),
- SAVE_ITEM(S5P_CLKDIV_LCD0),
- SAVE_ITEM(S5P_CLKDIV_MAUDIO),
- SAVE_ITEM(S5P_CLKDIV_FSYS0),
- SAVE_ITEM(S5P_CLKDIV_FSYS1),
- SAVE_ITEM(S5P_CLKDIV_FSYS2),
- SAVE_ITEM(S5P_CLKDIV_FSYS3),
- SAVE_ITEM(S5P_CLKDIV_PERIL0),
- SAVE_ITEM(S5P_CLKDIV_PERIL1),
- SAVE_ITEM(S5P_CLKDIV_PERIL2),
- SAVE_ITEM(S5P_CLKDIV_PERIL3),
- SAVE_ITEM(S5P_CLKDIV_PERIL4),
- SAVE_ITEM(S5P_CLKDIV_PERIL5),
- SAVE_ITEM(S5P_CLKDIV_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
- SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
- SAVE_ITEM(S5P_CLKSRC_MASK_TV),
- SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
- SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
- SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
- SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
- SAVE_ITEM(S5P_CLKDIV2_RATIO),
- SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
- SAVE_ITEM(S5P_CLKGATE_IP_CAM),
- SAVE_ITEM(S5P_CLKGATE_IP_TV),
- SAVE_ITEM(S5P_CLKGATE_IP_MFC),
- SAVE_ITEM(S5P_CLKGATE_IP_G3D),
- SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
- SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
- SAVE_ITEM(S5P_CLKGATE_IP_GPS),
- SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
- SAVE_ITEM(S5P_CLKGATE_BLOCK),
- SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
- SAVE_ITEM(S5P_CLKSRC_DMC),
- SAVE_ITEM(S5P_CLKDIV_DMC0),
- SAVE_ITEM(S5P_CLKDIV_DMC1),
- SAVE_ITEM(S5P_CLKGATE_IP_DMC),
- SAVE_ITEM(S5P_CLKSRC_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU),
- SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
- SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
- SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-#endif
-
-struct clk clk_sclk_hdmi27m = {
- .name = "sclk_hdmi27m",
- .rate = 27000000,
-};
-
-struct clk clk_sclk_hdmiphy = {
- .name = "sclk_hdmiphy",
-};
-
-struct clk clk_sclk_usbphy0 = {
- .name = "sclk_usbphy0",
- .rate = 27000000,
-};
-
-struct clk clk_sclk_usbphy1 = {
- .name = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
- .name = "apb_pclk",
- .id = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk clk_mout_apll = {
- .clk = {
- .name = "mout_apll",
- },
- .sources = &clk_src_apll,
- .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_sclk_apll = {
- .clk = {
- .name = "sclk_apll",
- .parent = &clk_mout_apll.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-struct clksrc_clk clk_mout_epll = {
- .clk = {
- .name = "mout_epll",
- },
- .sources = &clk_src_epll,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
- .clk = {
- .name = "mout_mpll",
- },
- .sources = &clk_src_mpll,
-
- /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *clkset_moutcore_list[] = {
- [0] = &clk_mout_apll.clk,
- [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_moutcore = {
- .sources = clkset_moutcore_list,
- .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
-};
-
-static struct clksrc_clk clk_moutcore = {
- .clk = {
- .name = "moutcore",
- },
- .sources = &clkset_moutcore,
- .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_coreclk = {
- .clk = {
- .name = "core_clk",
- .parent = &clk_moutcore.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_armclk = {
- .clk = {
- .name = "armclk",
- .parent = &clk_coreclk.clk,
- },
-};
-
-static struct clksrc_clk clk_aclk_corem0 = {
- .clk = {
- .name = "aclk_corem0",
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
- .clk = {
- .name = "aclk_cores",
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
- .clk = {
- .name = "aclk_corem1",
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
- .clk = {
- .name = "periphclk",
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-struct clk *clkset_corebus_list[] = {
- [0] = &clk_mout_mpll.clk,
- [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_mout_corebus = {
- .sources = clkset_corebus_list,
- .nr_sources = ARRAY_SIZE(clkset_corebus_list),
-};
-
-static struct clksrc_clk clk_mout_corebus = {
- .clk = {
- .name = "mout_corebus",
- },
- .sources = &clkset_mout_corebus,
- .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_dmc = {
- .clk = {
- .name = "sclk_dmc",
- .parent = &clk_mout_corebus.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cored = {
- .clk = {
- .name = "aclk_cored",
- .parent = &clk_sclk_dmc.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
- .clk = {
- .name = "aclk_corep",
- .parent = &clk_aclk_cored.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
- .clk = {
- .name = "aclk_acp",
- .parent = &clk_mout_corebus.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
- .clk = {
- .name = "pclk_acp",
- .parent = &clk_aclk_acp.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *clkset_aclk_top_list[] = {
- [0] = &clk_mout_mpll.clk,
- [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_aclk = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
-static struct clksrc_clk clk_aclk_200 = {
- .clk = {
- .name = "aclk_200",
- },
- .sources = &clkset_aclk,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_100 = {
- .clk = {
- .name = "aclk_100",
- },
- .sources = &clkset_aclk,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_aclk_160 = {
- .clk = {
- .name = "aclk_160",
- },
- .sources = &clkset_aclk,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk clk_aclk_133 = {
- .clk = {
- .name = "aclk_133",
- },
- .sources = &clkset_aclk,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
- [0] = &clk_fin_vpll,
- [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
- .sources = clkset_vpllsrc_list,
- .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
- .clk = {
- .name = "vpll_src",
- .enable = exynos4_clksrc_mask_top_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_vpllsrc,
- .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
- [0] = &clk_vpllsrc.clk,
- [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
- .sources = clkset_sclk_vpll_list,
- .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-struct clksrc_clk clk_sclk_vpll = {
- .clk = {
- .name = "sclk_vpll",
- },
- .sources = &clkset_sclk_vpll,
- .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk init_clocks_off[] = {
- {
- .name = "timers",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1<<24),
- }, {
- .name = "csis",
- .devname = "s5p-mipi-csis.0",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "csis",
- .devname = "s5p-mipi-csis.1",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 5),
- }, {
- .name = "fimc",
- .devname = "exynos4-fimc.0",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "fimc",
- .devname = "exynos4-fimc.1",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 1),
- }, {
- .name = "fimc",
- .devname = "exynos4-fimc.2",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 2),
- }, {
- .name = "fimc",
- .devname = "exynos4-fimc.3",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 3),
- }, {
- .name = "fimd",
- .devname = "exynos4-fb.0",
- .enable = exynos4_clk_ip_lcd0_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 5),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 6),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.3",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 8),
- }, {
- .name = "dwmmc",
- .parent = &clk_aclk_133.clk,
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 9),
- }, {
- .name = "dac",
- .devname = "s5p-sdo",
- .enable = exynos4_clk_ip_tv_ctrl,
- .ctrlbit = (1 << 2),
- }, {
- .name = "mixer",
- .devname = "s5p-mixer",
- .enable = exynos4_clk_ip_tv_ctrl,
- .ctrlbit = (1 << 1),
- }, {
- .name = "vp",
- .devname = "s5p-mixer",
- .enable = exynos4_clk_ip_tv_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "hdmi",
- .devname = "exynos4-hdmi",
- .enable = exynos4_clk_ip_tv_ctrl,
- .ctrlbit = (1 << 3),
- }, {
- .name = "hdmiphy",
- .devname = "exynos4-hdmi",
- .enable = exynos4_clk_hdmiphy_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "dacphy",
- .devname = "s5p-sdo",
- .enable = exynos4_clk_dac_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "adc",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 15),
- }, {
- .name = "keypad",
- .enable = exynos4_clk_ip_perir_ctrl,
- .ctrlbit = (1 << 16),
- }, {
- .name = "rtc",
- .enable = exynos4_clk_ip_perir_ctrl,
- .ctrlbit = (1 << 15),
- }, {
- .name = "watchdog",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_perir_ctrl,
- .ctrlbit = (1 << 14),
- }, {
- .name = "usbhost",
- .enable = exynos4_clk_ip_fsys_ctrl ,
- .ctrlbit = (1 << 12),
- }, {
- .name = "otg",
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 13),
- }, {
- .name = "spi",
- .devname = "s3c64xx-spi.0",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 16),
- }, {
- .name = "spi",
- .devname = "s3c64xx-spi.1",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 17),
- }, {
- .name = "spi",
- .devname = "s3c64xx-spi.2",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 18),
- }, {
- .name = "iis",
- .devname = "samsung-i2s.0",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 19),
- }, {
- .name = "iis",
- .devname = "samsung-i2s.1",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 20),
- }, {
- .name = "iis",
- .devname = "samsung-i2s.2",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 21),
- }, {
- .name = "ac97",
- .devname = "samsung-ac97",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 27),
- }, {
- .name = "fimg2d",
- .enable = exynos4_clk_ip_image_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "mfc",
- .devname = "s5p-mfc",
- .enable = exynos4_clk_ip_mfc_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.0",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 6),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.1",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.2",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 8),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.3",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 9),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.4",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 10),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.5",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 11),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.6",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 12),
- }, {
- .name = "i2c",
- .devname = "s3c2440-i2c.7",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 13),
- }, {
- .name = "i2c",
- .devname = "s3c2440-hdmiphy-i2c",
- .parent = &clk_aclk_100.clk,
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 14),
- }, {
- .name = "SYSMMU_MDMA",
- .enable = exynos4_clk_ip_image_ctrl,
- .ctrlbit = (1 << 5),
- }, {
- .name = "SYSMMU_FIMC0",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "SYSMMU_FIMC1",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 8),
- }, {
- .name = "SYSMMU_FIMC2",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 9),
- }, {
- .name = "SYSMMU_FIMC3",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 10),
- }, {
- .name = "SYSMMU_JPEG",
- .enable = exynos4_clk_ip_cam_ctrl,
- .ctrlbit = (1 << 11),
- }, {
- .name = "SYSMMU_FIMD0",
- .enable = exynos4_clk_ip_lcd0_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "SYSMMU_FIMD1",
- .enable = exynos4_clk_ip_lcd1_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "SYSMMU_PCIe",
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 18),
- }, {
- .name = "SYSMMU_G2D",
- .enable = exynos4_clk_ip_image_ctrl,
- .ctrlbit = (1 << 3),
- }, {
- .name = "SYSMMU_ROTATOR",
- .enable = exynos4_clk_ip_image_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "SYSMMU_TV",
- .enable = exynos4_clk_ip_tv_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "SYSMMU_MFC_L",
- .enable = exynos4_clk_ip_mfc_ctrl,
- .ctrlbit = (1 << 1),
- }, {
- .name = "SYSMMU_MFC_R",
- .enable = exynos4_clk_ip_mfc_ctrl,
- .ctrlbit = (1 << 2),
- }
-};
-
-static struct clk init_clocks[] = {
- {
- .name = "uart",
- .devname = "s5pv210-uart.0",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 0),
- }, {
- .name = "uart",
- .devname = "s5pv210-uart.1",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 1),
- }, {
- .name = "uart",
- .devname = "s5pv210-uart.2",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 2),
- }, {
- .name = "uart",
- .devname = "s5pv210-uart.3",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 3),
- }, {
- .name = "uart",
- .devname = "s5pv210-uart.4",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 4),
- }, {
- .name = "uart",
- .devname = "s5pv210-uart.5",
- .enable = exynos4_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 5),
- }
-};
-
-static struct clk clk_pdma0 = {
- .name = "dma",
- .devname = "dma-pl330.0",
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 0),
-};
-
-static struct clk clk_pdma1 = {
- .name = "dma",
- .devname = "dma-pl330.1",
- .enable = exynos4_clk_ip_fsys_ctrl,
- .ctrlbit = (1 << 1),
-};
-
-struct clk *clkset_group_list[] = {
- [0] = &clk_ext_xtal_mux,
- [1] = &clk_xusbxti,
- [2] = &clk_sclk_hdmi27m,
- [3] = &clk_sclk_usbphy0,
- [4] = &clk_sclk_usbphy1,
- [5] = &clk_sclk_hdmiphy,
- [6] = &clk_mout_mpll.clk,
- [7] = &clk_mout_epll.clk,
- [8] = &clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources clkset_group = {
- .sources = clkset_group_list,
- .nr_sources = ARRAY_SIZE(clkset_group_list),
-};
-
-static struct clk *clkset_mout_g2d0_list[] = {
- [0] = &clk_mout_mpll.clk,
- [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d0 = {
- .sources = clkset_mout_g2d0_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-
-static struct clksrc_clk clk_mout_g2d0 = {
- .clk = {
- .name = "mout_g2d0",
- },
- .sources = &clkset_mout_g2d0,
- .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d1_list[] = {
- [0] = &clk_mout_epll.clk,
- [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d1 = {
- .sources = clkset_mout_g2d1_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-
-static struct clksrc_clk clk_mout_g2d1 = {
- .clk = {
- .name = "mout_g2d1",
- },
- .sources = &clkset_mout_g2d1,
- .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d_list[] = {
- [0] = &clk_mout_g2d0.clk,
- [1] = &clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d = {
- .sources = clkset_mout_g2d_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-
-static struct clk *clkset_mout_mfc0_list[] = {
- [0] = &clk_mout_mpll.clk,
- [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc0 = {
- .sources = clkset_mout_mfc0_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk clk_mout_mfc0 = {
- .clk = {
- .name = "mout_mfc0",
- },
- .sources = &clkset_mout_mfc0,
- .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc1_list[] = {
- [0] = &clk_mout_epll.clk,
- [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc1 = {
- .sources = clkset_mout_mfc1_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk clk_mout_mfc1 = {
- .clk = {
- .name = "mout_mfc1",
- },
- .sources = &clkset_mout_mfc1,
- .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc_list[] = {
- [0] = &clk_mout_mfc0.clk,
- [1] = &clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc = {
- .sources = clkset_mout_mfc_list,
- .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
- [0] = &clk_sclk_vpll.clk,
- [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
- .sources = clkset_sclk_dac_list,
- .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
- .clk = {
- .name = "sclk_dac",
- .enable = exynos4_clksrc_mask_tv_ctrl,
- .ctrlbit = (1 << 8),
- },
- .sources = &clkset_sclk_dac,
- .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
- .clk = {
- .name = "sclk_pixel",
- .parent = &clk_sclk_vpll.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
- [0] = &clk_sclk_pixel.clk,
- [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
- .sources = clkset_sclk_hdmi_list,
- .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
- .clk = {
- .name = "sclk_hdmi",
- .enable = exynos4_clksrc_mask_tv_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_sclk_hdmi,
- .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
- [0] = &clk_sclk_dac.clk,
- [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
- .sources = clkset_sclk_mixer_list,
- .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
- .clk = {
- .name = "sclk_mixer",
- .enable = exynos4_clksrc_mask_tv_ctrl,
- .ctrlbit = (1 << 4),
- },
- .sources = &clkset_sclk_mixer,
- .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
- &clk_sclk_dac,
- &clk_sclk_pixel,
- &clk_sclk_hdmi,
- &clk_sclk_mixer,
-};
-
-static struct clksrc_clk clk_dout_mmc0 = {
- .clk = {
- .name = "dout_mmc0",
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc1 = {
- .clk = {
- .name = "dout_mmc1",
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc2 = {
- .clk = {
- .name = "dout_mmc2",
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc3 = {
- .clk = {
- .name = "dout_mmc3",
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc4 = {
- .clk = {
- .name = "dout_mmc4",
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
- {
- .clk = {
- .name = "sclk_pwm",
- .enable = exynos4_clksrc_mask_peril0_ctrl,
- .ctrlbit = (1 << 24),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_csis",
- .devname = "s5p-mipi-csis.0",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 24),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_csis",
- .devname = "s5p-mipi-csis.1",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 28),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_cam0",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 16),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_cam1",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 20),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimc",
- .devname = "exynos4-fimc.0",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimc",
- .devname = "exynos4-fimc.1",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 4),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimc",
- .devname = "exynos4-fimc.2",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 8),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimc",
- .devname = "exynos4-fimc.3",
- .enable = exynos4_clksrc_mask_cam_ctrl,
- .ctrlbit = (1 << 12),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimd",
- .devname = "exynos4-fb.0",
- .enable = exynos4_clksrc_mask_lcd0_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_fimg2d",
- },
- .sources = &clkset_mout_g2d,
- .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mfc",
- .devname = "s5p-mfc",
- },
- .sources = &clkset_mout_mfc,
- .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
- .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_dwmmc",
- .parent = &clk_dout_mmc4.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 16),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
- }
-};
-
-static struct clksrc_clk clk_sclk_uart0 = {
- .clk = {
- .name = "uclk1",
- .devname = "exynos4210-uart.0",
- .enable = exynos4_clksrc_mask_peril0_ctrl,
- .ctrlbit = (1 << 0),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart1 = {
- .clk = {
- .name = "uclk1",
- .devname = "exynos4210-uart.1",
- .enable = exynos4_clksrc_mask_peril0_ctrl,
- .ctrlbit = (1 << 4),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart2 = {
- .clk = {
- .name = "uclk1",
- .devname = "exynos4210-uart.2",
- .enable = exynos4_clksrc_mask_peril0_ctrl,
- .ctrlbit = (1 << 8),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart3 = {
- .clk = {
- .name = "uclk1",
- .devname = "exynos4210-uart.3",
- .enable = exynos4_clksrc_mask_peril0_ctrl,
- .ctrlbit = (1 << 12),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_dout_mmc0.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 0),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_dout_mmc1.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 4),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_dout_mmc2.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 8),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc3 = {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.3",
- .parent = &clk_dout_mmc3.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 12),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .enable = exynos4_clksrc_mask_peril1_ctrl,
- .ctrlbit = (1 << 16),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .enable = exynos4_clksrc_mask_peril1_ctrl,
- .ctrlbit = (1 << 20),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi2 = {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
- .enable = exynos4_clksrc_mask_peril1_ctrl,
- .ctrlbit = (1 << 24),
- },
- .sources = &clkset_group,
- .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
- .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
- &clk_mout_apll,
- &clk_sclk_apll,
- &clk_mout_epll,
- &clk_mout_mpll,
- &clk_moutcore,
- &clk_coreclk,
- &clk_armclk,
- &clk_aclk_corem0,
- &clk_aclk_cores,
- &clk_aclk_corem1,
- &clk_periphclk,
- &clk_mout_corebus,
- &clk_sclk_dmc,
- &clk_aclk_cored,
- &clk_aclk_corep,
- &clk_aclk_acp,
- &clk_pclk_acp,
- &clk_vpllsrc,
- &clk_sclk_vpll,
- &clk_aclk_200,
- &clk_aclk_100,
- &clk_aclk_160,
- &clk_aclk_133,
- &clk_dout_mmc0,
- &clk_dout_mmc1,
- &clk_dout_mmc2,
- &clk_dout_mmc3,
- &clk_dout_mmc4,
- &clk_mout_mfc0,
- &clk_mout_mfc1,
-};
-
-static struct clk *clk_cdev[] = {
- &clk_pdma0,
- &clk_pdma1,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
- &clk_sclk_uart0,
- &clk_sclk_uart1,
- &clk_sclk_uart2,
- &clk_sclk_uart3,
- &clk_sclk_mmc0,
- &clk_sclk_mmc1,
- &clk_sclk_mmc2,
- &clk_sclk_mmc3,
- &clk_sclk_spi0,
- &clk_sclk_spi1,
- &clk_sclk_spi2,
-
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
- CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
- CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
- CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
- CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
- CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
- CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
- CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
- CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
- CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
- CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
- if (soc_is_exynos4210())
- return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
- pll_4508);
- else if (soc_is_exynos4212() || soc_is_exynos4412())
- return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
- else
- return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
- .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 vpll_div[][8] = {
- { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
- { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned int vpll_con0, vpll_con1 = 0;
- unsigned int i;
-
- /* Return if nothing changed */
- if (clk->rate == rate)
- return 0;
-
- vpll_con0 = __raw_readl(S5P_VPLL_CON0);
- vpll_con0 &= ~(0x1 << 27 | \
- PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
- PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
- PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
- vpll_con1 = __raw_readl(S5P_VPLL_CON1);
- vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
- PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
- PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
- for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
- if (vpll_div[i][0] == rate) {
- vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
- vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
- vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
- vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
- vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
- vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
- vpll_con0 |= vpll_div[i][7] << 27;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(vpll_div)) {
- printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
- __func__);
- return -EINVAL;
- }
-
- __raw_writel(vpll_con0, S5P_VPLL_CON0);
- __raw_writel(vpll_con1, S5P_VPLL_CON1);
-
- /* Wait for VPLL lock */
- while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
- continue;
-
- clk->rate = rate;
- return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
- .get_rate = exynos4_vpll_get_rate,
- .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
- struct clk *xtal_clk;
- unsigned long apll = 0;
- unsigned long mpll = 0;
- unsigned long epll = 0;
- unsigned long vpll = 0;
- unsigned long vpllsrc;
- unsigned long xtal;
- unsigned long armclk;
- unsigned long sclk_dmc;
- unsigned long aclk_200;
- unsigned long aclk_100;
- unsigned long aclk_160;
- unsigned long aclk_133;
- unsigned int ptr;
-
- printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
- xtal_clk = clk_get(NULL, "xtal");
- BUG_ON(IS_ERR(xtal_clk));
-
- xtal = clk_get_rate(xtal_clk);
-
- xtal_rate = xtal;
-
- clk_put(xtal_clk);
-
- printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
- if (soc_is_exynos4210()) {
- apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
- pll_4508);
- mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
- pll_4508);
- epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
- __raw_readl(S5P_EPLL_CON1), pll_4600);
-
- vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
- vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
- __raw_readl(S5P_VPLL_CON1), pll_4650c);
- } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
- apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
- mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
- epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
- __raw_readl(S5P_EPLL_CON1));
-
- vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
- vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
- __raw_readl(S5P_VPLL_CON1));
- } else {
- /* nothing */
- }
-
- clk_fout_apll.ops = &exynos4_fout_apll_ops;
- clk_fout_mpll.rate = mpll;
- clk_fout_epll.rate = epll;
- clk_fout_vpll.ops = &exynos4_vpll_ops;
- clk_fout_vpll.rate = vpll;
-
- printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
- apll, mpll, epll, vpll);
-
- armclk = clk_get_rate(&clk_armclk.clk);
- sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-
- aclk_200 = clk_get_rate(&clk_aclk_200.clk);
- aclk_100 = clk_get_rate(&clk_aclk_100.clk);
- aclk_160 = clk_get_rate(&clk_aclk_160.clk);
- aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-
- printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
- "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
- armclk, sclk_dmc, aclk_200,
- aclk_100, aclk_160, aclk_133);
-
- clk_f.rate = armclk;
- clk_h.rate = sclk_dmc;
- clk_p.rate = aclk_100;
-
- for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
- s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
- &clk_sclk_hdmi27m,
- &clk_sclk_hdmiphy,
- &clk_sclk_usbphy0,
- &clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
- s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
- return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
- s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4_clock_syscore_ops = {
- .suspend = exynos4_clock_suspend,
- .resume = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
- int ptr;
-
- s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
- for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
- s3c_register_clksrc(sysclks[ptr], 1);
-
- for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
- s3c_register_clksrc(sclk_tv[ptr], 1);
-
- for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
- s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
- s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
- s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
- s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
- for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
- s3c_disable_clocks(clk_cdev[ptr], 1);
-
- s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
- s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
- clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
- register_syscore_ops(&exynos4_clock_syscore_ops);
- s3c24xx_register_clock(&dummy_apb_pclk);
-
- s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index c59e1887100..5ccd6e80a60 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -26,10 +26,12 @@
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
+#include <asm/cacheflush.h>
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
#include <mach/regs-gpio.h>
+#include <mach/pmu.h>
#include <plat/cpu.h>
#include <plat/clock.h>
@@ -45,10 +47,20 @@
#include <plat/regs-serial.h>
#include "common.h"
+#define L2_AUX_VAL 0x7C470001
+#define L2_AUX_MASK 0xC200ffff
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
+
+static void exynos4_map_io(void);
+static void exynos5_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
static struct cpu_table cpu_ids[] __initdata = {
{
@@ -56,7 +68,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
- .init_uarts = exynos4_init_uarts,
+ .init_uarts = exynos_init_uarts,
.init = exynos_init,
.name = name_exynos4210,
}, {
@@ -64,7 +76,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
- .init_uarts = exynos4_init_uarts,
+ .init_uarts = exynos_init_uarts,
.init = exynos_init,
.name = name_exynos4212,
}, {
@@ -72,9 +84,17 @@ static struct cpu_table cpu_ids[] __initdata = {
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
- .init_uarts = exynos4_init_uarts,
+ .init_uarts = exynos_init_uarts,
.init = exynos_init,
.name = name_exynos4412,
+ }, {
+ .idcode = EXYNOS5250_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init_clocks = exynos5_init_clocks,
+ .init_uarts = exynos_init_uarts,
+ .init = exynos_init,
+ .name = name_exynos5250,
},
};
@@ -83,10 +103,14 @@ static struct cpu_table cpu_ids[] __initdata = {
static struct map_desc exynos_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CHIPID,
- .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+ .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
.length = SZ_4K,
.type = MT_DEVICE,
- }, {
+ },
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+ {
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
.length = SZ_64K,
@@ -136,11 +160,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
- },
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
- {
+ }, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
@@ -156,24 +176,14 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = (unsigned long)S5P_VA_GPIO1,
- .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = (unsigned long)S5P_VA_GPIO2,
- .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = (unsigned long)S5P_VA_GPIO3,
- .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
- .length = SZ_256,
- .type = MT_DEVICE,
- }, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
- .length = SZ_4K,
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_DMC1,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
+ .length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
@@ -201,19 +211,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
},
};
-static void exynos_idle(void)
-{
- if (!need_resched())
- cpu_do_idle();
-
- local_irq_enable();
-}
+static struct map_desc exynos5_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S3C_VA_SYS,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_TIMER,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_WATCHDOG,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_SROMC,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_SYSTIMER,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_SYSRAM,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_CMU,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
+ .length = 144 * SZ_1K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_PMU,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_UART,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
+ .length = SZ_512K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_CPU,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_DIST,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ },
+};
void exynos4_restart(char mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
}
+void exynos5_restart(char mode, const char *cmd)
+{
+ __raw_writel(0x1, EXYNOS_SWRESET);
+}
+
/*
* exynos_map_io
*
@@ -233,7 +304,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
{
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
@@ -255,6 +326,11 @@ void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
+ s3c_sdhci_setname(0, "exynos4-sdhci");
+ s3c_sdhci_setname(1, "exynos4-sdhci");
+ s3c_sdhci_setname(2, "exynos4-sdhci");
+ s3c_sdhci_setname(3, "exynos4-sdhci");
+
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@@ -264,7 +340,27 @@ void __init exynos4_map_io(void)
s5p_hdmi_setname("exynos4-hdmi");
}
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos5_map_io(void)
+{
+ iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+ s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
+ s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
+ s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
+ s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
+
+ s3c_sdhci_setname(0, "exynos4-sdhci");
+ s3c_sdhci_setname(1, "exynos4-sdhci");
+ s3c_sdhci_setname(2, "exynos4-sdhci");
+ s3c_sdhci_setname(3, "exynos4-sdhci");
+
+ /* The I2C bus controllers are directly compatible with s3c2440 */
+ s3c_i2c0_setname("s3c2440-i2c");
+ s3c_i2c1_setname("s3c2440-i2c");
+ s3c_i2c2_setname("s3c2440-i2c");
+}
+
+static void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -280,6 +376,17 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
+static void __init exynos5_init_clocks(int xtal)
+{
+ printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+ s3c24xx_register_baseclocks(xtal);
+ s5p_register_clocks(xtal);
+
+ exynos5_register_clocks();
+ exynos5_setup_clocks();
+}
+
#define COMBINER_ENABLE_SET 0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS 0xC
@@ -353,7 +460,14 @@ static struct irq_chip combiner_chip = {
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
- if (combiner_nr >= MAX_COMBINER_NR)
+ unsigned int max_nr;
+
+ if (soc_is_exynos5250())
+ max_nr = EXYNOS5_MAX_COMBINER_NR;
+ else
+ max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+ if (combiner_nr >= max_nr)
BUG();
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG();
@@ -364,8 +478,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int i;
+ unsigned int max_nr;
+
+ if (soc_is_exynos5250())
+ max_nr = EXYNOS5_MAX_COMBINER_NR;
+ else
+ max_nr = EXYNOS4_MAX_COMBINER_NR;
- if (combiner_nr >= MAX_COMBINER_NR)
+ if (combiner_nr >= max_nr)
BUG();
combiner_data[combiner_nr].base = base;
@@ -402,13 +522,13 @@ void __init exynos4_init_irq(void)
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
if (!of_have_populated_dt())
- gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+ gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
#ifdef CONFIG_OF
else
of_irq_init(exynos4_dt_irq_match);
#endif
- for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+ for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
@@ -423,60 +543,147 @@ void __init exynos4_init_irq(void)
s5p_init_irq(NULL, 0);
}
+void __init exynos5_init_irq(void)
+{
+ int irq;
+
+#ifdef CONFIG_OF
+ of_irq_init(exynos4_dt_irq_match);
+#endif
+
+ for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
+ combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+ COMBINER_IRQ(irq, 0));
+ combiner_cascade_irq(irq, IRQ_SPI(irq));
+ }
+
+ /*
+ * The parameters of s5p_init_irq() are for VIC init.
+ * Theses parameters should be NULL and 0 because EXYNOS4
+ * uses GIC instead of VIC.
+ */
+ s5p_init_irq(NULL, 0);
+}
+
struct bus_type exynos4_subsys = {
.name = "exynos4-core",
.dev_name = "exynos4-core",
};
+struct bus_type exynos5_subsys = {
+ .name = "exynos5-core",
+ .dev_name = "exynos5-core",
+};
+
static struct device exynos4_dev = {
.bus = &exynos4_subsys,
};
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+ .bus = &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
{
- return subsys_system_register(&exynos4_subsys, NULL);
+ if (soc_is_exynos5250())
+ return subsys_system_register(&exynos5_subsys, NULL);
+ else
+ return subsys_system_register(&exynos4_subsys, NULL);
}
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
- /* TAG, Data Latency Control: 2cycle */
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+ int ret;
- if (soc_is_exynos4210())
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
- else if (soc_is_exynos4212() || soc_is_exynos4412())
- __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+ if (soc_is_exynos5250())
+ return 0;
+
+ ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+ if (!ret) {
+ l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+ clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+ return 0;
+ }
+
+ if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
+ l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
+ /* TAG, Data Latency Control: 2 cycles */
+ l2x0_saved_regs.tag_latency = 0x110;
- /* L2X0 Prefetch Control */
- __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+ if (soc_is_exynos4212() || soc_is_exynos4412())
+ l2x0_saved_regs.data_latency = 0x120;
+ else
+ l2x0_saved_regs.data_latency = 0x110;
- /* L2X0 Power Control */
- __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
- S5P_VA_L2CC + L2X0_POWER_CTRL);
+ l2x0_saved_regs.prefetch_ctrl = 0x30000007;
+ l2x0_saved_regs.pwr_ctrl =
+ (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
- l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+ l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+
+ __raw_writel(l2x0_saved_regs.tag_latency,
+ S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+ __raw_writel(l2x0_saved_regs.data_latency,
+ S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+ /* L2X0 Prefetch Control */
+ __raw_writel(l2x0_saved_regs.prefetch_ctrl,
+ S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+ /* L2X0 Power Control */
+ __raw_writel(l2x0_saved_regs.pwr_ctrl,
+ S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+ clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+ clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
+ }
+ l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
return 0;
}
-
early_initcall(exynos4_l2x0_cache_init);
#endif
-int __init exynos_init(void)
+static int __init exynos5_l2_cache_init(void)
{
- printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+ unsigned int val;
+
+ if (!soc_is_exynos5250())
+ return 0;
+
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ "bic %0, %0, #(1 << 2)\n" /* cache disable */
+ "mcr p15, 0, %0, c1, c0, 0\n"
+ "mrc p15, 1, %0, c9, c0, 2\n"
+ : "=r"(val));
+
+ val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
+
+ asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ "orr %0, %0, #(1 << 2)\n" /* cache enable */
+ "mcr p15, 0, %0, c1, c0, 0\n"
+ : : "r"(val));
- /* set idle function */
- pm_idle = exynos_idle;
+ return 0;
+}
+early_initcall(exynos5_l2_cache_init);
+
+static int __init exynos_init(void)
+{
+ printk(KERN_INFO "EXYNOS: Initializing architecture\n");
- return device_register(&exynos4_dev);
+ if (soc_is_exynos5250())
+ return device_register(&exynos5_dev);
+ else
+ return device_register(&exynos4_dev);
}
/* uart registration process */
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
@@ -484,69 +691,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
tcfg->has_fracval = 1;
- s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+ if (soc_is_exynos5250())
+ s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+ else
+ s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
}
+static void __iomem *exynos_eint_base;
+
static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16];
-static unsigned int exynos4_get_irq_nr(unsigned int number)
+static inline int exynos4_irq_to_gpio(unsigned int irq)
{
- u32 ret = 0;
+ if (irq < IRQ_EINT(0))
+ return -EINVAL;
- switch (number) {
- case 0 ... 3:
- ret = (number + IRQ_EINT0);
- break;
- case 4 ... 7:
- ret = (number + (IRQ_EINT4 - 4));
- break;
- case 8 ... 15:
- ret = (number + (IRQ_EINT8 - 8));
- break;
- default:
- printk(KERN_ERR "number available : %d\n", number);
- }
+ irq -= IRQ_EINT(0);
+ if (irq < 8)
+ return EXYNOS4_GPX0(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS4_GPX1(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS4_GPX2(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS4_GPX3(irq);
- return ret;
+ return -EINVAL;
}
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
+static inline int exynos5_irq_to_gpio(unsigned int irq)
+{
+ if (irq < IRQ_EINT(0))
+ return -EINVAL;
+
+ irq -= IRQ_EINT(0);
+ if (irq < 8)
+ return EXYNOS5_GPX0(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS5_GPX1(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS5_GPX2(irq);
+
+ irq -= 8;
+ if (irq < 8)
+ return EXYNOS5_GPX3(irq);
+
+ return -EINVAL;
+}
+
+static unsigned int exynos4_eint0_15_src_int[16] = {
+ EXYNOS4_IRQ_EINT0,
+ EXYNOS4_IRQ_EINT1,
+ EXYNOS4_IRQ_EINT2,
+ EXYNOS4_IRQ_EINT3,
+ EXYNOS4_IRQ_EINT4,
+ EXYNOS4_IRQ_EINT5,
+ EXYNOS4_IRQ_EINT6,
+ EXYNOS4_IRQ_EINT7,
+ EXYNOS4_IRQ_EINT8,
+ EXYNOS4_IRQ_EINT9,
+ EXYNOS4_IRQ_EINT10,
+ EXYNOS4_IRQ_EINT11,
+ EXYNOS4_IRQ_EINT12,
+ EXYNOS4_IRQ_EINT13,
+ EXYNOS4_IRQ_EINT14,
+ EXYNOS4_IRQ_EINT15,
+};
+
+static unsigned int exynos5_eint0_15_src_int[16] = {
+ EXYNOS5_IRQ_EINT0,
+ EXYNOS5_IRQ_EINT1,
+ EXYNOS5_IRQ_EINT2,
+ EXYNOS5_IRQ_EINT3,
+ EXYNOS5_IRQ_EINT4,
+ EXYNOS5_IRQ_EINT5,
+ EXYNOS5_IRQ_EINT6,
+ EXYNOS5_IRQ_EINT7,
+ EXYNOS5_IRQ_EINT8,
+ EXYNOS5_IRQ_EINT9,
+ EXYNOS5_IRQ_EINT10,
+ EXYNOS5_IRQ_EINT11,
+ EXYNOS5_IRQ_EINT12,
+ EXYNOS5_IRQ_EINT13,
+ EXYNOS5_IRQ_EINT14,
+ EXYNOS5_IRQ_EINT15,
+};
+static inline void exynos_irq_eint_mask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
- mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
- mask |= eint_irq_to_bit(data->irq);
- __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+ mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+ mask |= EINT_OFFSET_BIT(data->irq);
+ __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
spin_unlock(&eint_lock);
}
-static void exynos4_irq_eint_unmask(struct irq_data *data)
+static void exynos_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
- mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
- mask &= ~(eint_irq_to_bit(data->irq));
- __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+ mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+ mask &= ~(EINT_OFFSET_BIT(data->irq));
+ __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
spin_unlock(&eint_lock);
}
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
+static inline void exynos_irq_eint_ack(struct irq_data *data)
{
- __raw_writel(eint_irq_to_bit(data->irq),
- S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+ __raw_writel(EINT_OFFSET_BIT(data->irq),
+ EINT_PEND(exynos_eint_base, data->irq));
}
-static void exynos4_irq_eint_maskack(struct irq_data *data)
+static void exynos_irq_eint_maskack(struct irq_data *data)
{
- exynos4_irq_eint_mask(data);
- exynos4_irq_eint_ack(data);
+ exynos_irq_eint_mask(data);
+ exynos_irq_eint_ack(data);
}
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(data->irq);
int shift;
@@ -583,39 +859,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
mask = 0x7 << shift;
spin_lock(&eint_lock);
- ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+ ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
ctrl &= ~mask;
ctrl |= newvalue << shift;
- __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+ __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
spin_unlock(&eint_lock);
- switch (offs) {
- case 0 ... 7:
- s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
- break;
- case 8 ... 15:
- s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
- break;
- case 16 ... 23:
- s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
- break;
- case 24 ... 31:
- s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
- break;
- default:
- printk(KERN_ERR "No such irq number %d", offs);
- }
+ if (soc_is_exynos5250())
+ s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
+ else
+ s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
return 0;
}
-static struct irq_chip exynos4_irq_eint = {
- .name = "exynos4-eint",
- .irq_mask = exynos4_irq_eint_mask,
- .irq_unmask = exynos4_irq_eint_unmask,
- .irq_mask_ack = exynos4_irq_eint_maskack,
- .irq_ack = exynos4_irq_eint_ack,
- .irq_set_type = exynos4_irq_eint_set_type,
+static struct irq_chip exynos_irq_eint = {
+ .name = "exynos-eint",
+ .irq_mask = exynos_irq_eint_mask,
+ .irq_unmask = exynos_irq_eint_unmask,
+ .irq_mask_ack = exynos_irq_eint_maskack,
+ .irq_ack = exynos_irq_eint_ack,
+ .irq_set_type = exynos_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
@@ -630,12 +894,12 @@ static struct irq_chip exynos4_irq_eint = {
*
* Each EINT pend/mask registers handle eight of them.
*/
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos_irq_demux_eint(unsigned int start)
{
unsigned int irq;
- u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
- u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+ u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
+ u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
status &= ~mask;
status &= 0xff;
@@ -647,16 +911,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
}
}
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
- exynos4_irq_demux_eint(IRQ_EINT(16));
- exynos4_irq_demux_eint(IRQ_EINT(24));
+ exynos_irq_demux_eint(IRQ_EINT(16));
+ exynos_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
}
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
@@ -673,27 +937,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-int __init exynos4_init_irq_eint(void)
+static int __init exynos_init_irq_eint(void)
{
int irq;
+ if (soc_is_exynos5250())
+ exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
+ else
+ exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
+
+ if (exynos_eint_base == NULL) {
+ pr_err("unable to ioremap for EINT base address\n");
+ return -ENOMEM;
+ }
+
for (irq = 0 ; irq <= 31 ; irq++) {
- irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+ irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
- irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+ irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
- irq_set_handler_data(exynos4_get_irq_nr(irq),
- &eint0_15_data[irq]);
- irq_set_chained_handler(exynos4_get_irq_nr(irq),
- exynos4_irq_eint0_15);
+ if (soc_is_exynos5250()) {
+ irq_set_handler_data(exynos5_eint0_15_src_int[irq],
+ &eint0_15_data[irq]);
+ irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
+ exynos_irq_eint0_15);
+ } else {
+ irq_set_handler_data(exynos4_eint0_15_src_int[irq],
+ &eint0_15_data[irq]);
+ irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
+ exynos_irq_eint0_15);
+ }
}
return 0;
}
-arch_initcall(exynos4_init_irq_eint);
+arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f39..677b5467df1 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,30 +12,44 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
+extern struct sys_timer exynos4_timer;
+
void exynos_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void);
+void exynos5_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
+#ifdef CONFIG_ARCH_EXYNOS4
void exynos4_register_clocks(void);
void exynos4_setup_clocks(void);
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+#endif
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
-#ifdef CONFIG_ARCH_EXYNOS
-extern int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define exynos4210_register_clocks()
+#endif
+
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
#else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
#endif
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4ebb382c597..33ab4e7558a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -11,25 +11,53 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/time.h>
#include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <asm/unified.h>
+#include <mach/regs-pmu.h>
+#include <mach/pmu.h>
+
+#include <plat/cpu.h>
+
+#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+#define S5P_CHECK_AFTR 0xFCBA0D10
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index);
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
-static struct cpuidle_state exynos4_cpuidle_set[] = {
+static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
[0] = {
.enter = exynos4_enter_idle,
.exit_latency = 1,
.target_residency = 100000,
.flags = CPUIDLE_FLAG_TIME_VALID,
- .name = "IDLE",
+ .name = "C0",
.desc = "ARM clock gating(WFI)",
},
+ [1] = {
+ .enter = exynos4_enter_lowpower,
+ .exit_latency = 300,
+ .target_residency = 100000,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "C1",
+ .desc = "ARM power down",
+ },
};
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
.owner = THIS_MODULE,
};
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos4_set_wakeupmask(void)
+{
+ __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+}
+
+static unsigned int g_pwr_ctrl, g_diag_reg;
+
+static void save_cpu_arch_register(void)
+{
+ /*read power control register*/
+ asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
+ /*read diagnostic register*/
+ asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+ return;
+}
+
+static void restore_cpu_arch_register(void)
+{
+ /*write power control register*/
+ asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
+ /*write diagnostic register*/
+ asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+ return;
+}
+
+static int idle_finisher(unsigned long flags)
+{
+ cpu_do_idle();
+ return 1;
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct timeval before, after;
+ int idle_time;
+ unsigned long tmp;
+
+ local_irq_disable();
+ do_gettimeofday(&before);
+
+ exynos4_set_wakeupmask();
+
+ /* Set value of power down register for aftr mode */
+ exynos4_sys_powerdown_conf(SYS_AFTR);
+
+ __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+ __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+ save_cpu_arch_register();
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ cpu_pm_enter();
+ cpu_suspend(0, idle_finisher);
+
+#ifdef CONFIG_SMP
+ scu_enable(S5P_VA_SCU);
+#endif
+ cpu_pm_exit();
+
+ restore_cpu_arch_register();
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ }
+
+ /* Clear wakeup state register */
+ __raw_writel(0x0, S5P_WAKEUP_STAT);
+
+ do_gettimeofday(&after);
+
+ local_irq_enable();
+ idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+ (after.tv_usec - before.tv_usec);
+
+ dev->last_residency = idle_time;
+ return index;
+}
+
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
- int index)
+ int index)
{
struct timeval before, after;
int idle_time;
@@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
return index;
}
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ int new_index = index;
+
+ /* This mode only can be entered when other core's are offline */
+ if (num_online_cpus() > 1)
+ new_index = drv->safe_state_index;
+
+ if (new_index == 0)
+ return exynos4_enter_idle(dev, drv, new_index);
+ else
+ return exynos4_enter_core0_aftr(dev, drv, new_index);
+}
+
static int __init exynos4_init_cpuidle(void)
{
int i, max_cpuidle_state, cpu_id;
@@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
sizeof(struct cpuidle_state));
}
+ drv->safe_state_index = 0;
cpuidle_register_driver(&exynos4_idle_driver);
for_each_cpu(cpu_id, cpu_online_mask) {
device = &per_cpu(exynos4_cpuidle_device, cpu_id);
device->cpu = cpu_id;
- device->state_count = drv->state_count;
+ if (cpu_id == 0)
+ device->state_count = (sizeof(exynos4_cpuidle_set) /
+ sizeof(struct cpuidle_state));
+ else
+ device->state_count = 1; /* Support IDLE only */
if (cpuidle_register_device(device)) {
printk(KERN_ERR "CPUidle register device failed\n,");
return -EIO;
}
}
+
return 0;
}
device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de8e1d..50ce5b0adcf 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_SATA,
- .end = IRQ_SATA,
+ .start = EXYNOS4_IRQ_SATA,
+ .end = EXYNOS4_IRQ_SATA,
.flags = IORESOURCE_IRQ,
},
};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e53b..7199e1ae79b 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
.flags = IORESOURCE_DMA,
},
[4] = {
- .start = IRQ_AC97,
- .end = IRQ_AC97,
+ .start = EXYNOS4_IRQ_AC97,
+ .end = EXYNOS4_IRQ_AC97,
.flags = IORESOURCE_IRQ,
},
};
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
index b025db4bf60..79035018fb7 100644
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
+#include <linux/ioport.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
}
static struct resource exynos4_dwmci_resource[] = {
- [0] = {
- .start = EXYNOS4_PA_DWMCI,
- .end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DWMCI,
- .end = IRQ_DWMCI,
- .flags = IORESOURCE_IRQ,
- }
+ [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
+ [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
};
static struct dw_mci_board exynos4_dwci_pdata = {
diff --git a/arch/arm/mach-exynos/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
deleted file mode 100644
index 3273f25d6a7..00000000000
--- a/arch/arm/mach-exynos/dev-pd.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-pd.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Power Domain support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-
-#include <mach/regs-pmu.h>
-
-#include <plat/pd.h>
-
-static int exynos4_pd_enable(struct device *dev)
-{
- struct samsung_pd_info *pdata = dev->platform_data;
- u32 timeout;
-
- __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
-
- /* Wait max 1ms */
- timeout = 10;
- while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
- != S5P_INT_LOCAL_PWR_EN) {
- if (timeout == 0) {
- printk(KERN_ERR "Power domain %s enable failed.\n",
- dev_name(dev));
- return -ETIMEDOUT;
- }
- timeout--;
- udelay(100);
- }
-
- return 0;
-}
-
-static int exynos4_pd_disable(struct device *dev)
-{
- struct samsung_pd_info *pdata = dev->platform_data;
- u32 timeout;
-
- __raw_writel(0, pdata->base);
-
- /* Wait max 1ms */
- timeout = 10;
- while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
- if (timeout == 0) {
- printk(KERN_ERR "Power domain %s disable failed.\n",
- dev_name(dev));
- return -ETIMEDOUT;
- }
- timeout--;
- udelay(100);
- }
-
- return 0;
-}
-
-struct platform_device exynos4_device_pd[] = {
- {
- .name = "samsung-pd",
- .id = 0,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_MFC_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 1,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_G3D_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 2,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_LCD0_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 3,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_LCD1_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 4,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_TV_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 5,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_CAM_CONF,
- },
- },
- }, {
- .name = "samsung-pd",
- .id = 6,
- .dev = {
- .platform_data = &(struct samsung_pd_info) {
- .enable = exynos4_pd_enable,
- .disable = exynos4_pd_disable,
- .base = S5P_PMU_GPS_CONF,
- },
- },
- },
-};
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 00000000000..2e85c022fd1
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr) \
+static struct resource exynos##_series##_uart##_nr##_resource[] = { \
+ [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
+ [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+ [0] = {
+ .resources = exynos4_uart0_resource,
+ .nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
+ },
+ [1] = {
+ .resources = exynos4_uart1_resource,
+ .nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
+ },
+ [2] = {
+ .resources = exynos4_uart2_resource,
+ .nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
+ },
+ [3] = {
+ .resources = exynos4_uart3_resource,
+ .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
+ },
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+ [0] = {
+ .resources = exynos5_uart0_resource,
+ .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
+ },
+ [1] = {
+ .resources = exynos5_uart1_resource,
+ .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
+ },
+ [2] = {
+ .resources = exynos5_uart2_resource,
+ .nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
+ },
+ [3] = {
+ .resources = exynos5_uart3_resource,
+ .nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
+ },
+};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index b10fcd270f0..69aaa450320 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -29,14 +29,13 @@
#include <asm/irq.h>
#include <plat/devs.h>
#include <plat/irqs.h>
+#include <plat/cpu.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/dma.h>
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-u8 pdma0_peri[] = {
+static u8 exynos4210_pdma0_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM2_RX,
@@ -69,28 +68,47 @@ u8 pdma0_peri[] = {
DMACH_AC97_PCMOUT,
};
-struct dma_pl330_platdata exynos4_pdma0_pdata = {
- .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
- .peri_id = pdma0_peri,
+static u8 exynos4212_pdma0_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM2_RX,
+ DMACH_PCM2_TX,
+ DMACH_MIPI_HSI0,
+ DMACH_MIPI_HSI1,
+ DMACH_SPI0_RX,
+ DMACH_SPI0_TX,
+ DMACH_SPI2_RX,
+ DMACH_SPI2_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S2_RX,
+ DMACH_I2S2_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART2_RX,
+ DMACH_UART2_TX,
+ DMACH_UART4_RX,
+ DMACH_UART4_TX,
+ DMACH_SLIMBUS0_RX,
+ DMACH_SLIMBUS0_TX,
+ DMACH_SLIMBUS2_RX,
+ DMACH_SLIMBUS2_TX,
+ DMACH_SLIMBUS4_RX,
+ DMACH_SLIMBUS4_TX,
+ DMACH_AC97_MICIN,
+ DMACH_AC97_PCMIN,
+ DMACH_AC97_PCMOUT,
+ DMACH_MIPI_HSI4,
+ DMACH_MIPI_HSI5,
};
-struct amba_device exynos4_device_pdma0 = {
- .dev = {
- .init_name = "dma-pl330.0",
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &exynos4_pdma0_pdata,
- },
- .res = {
- .start = EXYNOS4_PA_PDMA0,
- .end = EXYNOS4_PA_PDMA0 + SZ_4K,
- .flags = IORESOURCE_MEM,
- },
- .irq = {IRQ_PDMA0, NO_IRQ},
- .periphid = 0x00041330,
-};
+struct dma_pl330_platdata exynos4_pdma0_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
+ EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
-u8 pdma1_peri[] = {
+static u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
@@ -118,39 +136,94 @@ u8 pdma1_peri[] = {
DMACH_SLIMBUS5_TX,
};
-struct dma_pl330_platdata exynos4_pdma1_pdata = {
- .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
- .peri_id = pdma1_peri,
+static u8 exynos4212_pdma1_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM1_RX,
+ DMACH_PCM1_TX,
+ DMACH_MIPI_HSI2,
+ DMACH_MIPI_HSI3,
+ DMACH_SPI1_RX,
+ DMACH_SPI1_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S1_RX,
+ DMACH_I2S1_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART1_RX,
+ DMACH_UART1_TX,
+ DMACH_UART3_RX,
+ DMACH_UART3_TX,
+ DMACH_SLIMBUS1_RX,
+ DMACH_SLIMBUS1_TX,
+ DMACH_SLIMBUS3_RX,
+ DMACH_SLIMBUS3_TX,
+ DMACH_SLIMBUS5_RX,
+ DMACH_SLIMBUS5_TX,
+ DMACH_SLIMBUS0AUX_RX,
+ DMACH_SLIMBUS0AUX_TX,
+ DMACH_SPDIF,
+ DMACH_MIPI_HSI6,
+ DMACH_MIPI_HSI7,
};
-struct amba_device exynos4_device_pdma1 = {
- .dev = {
- .init_name = "dma-pl330.1",
- .dma_mask = &dma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &exynos4_pdma1_pdata,
- },
- .res = {
- .start = EXYNOS4_PA_PDMA1,
- .end = EXYNOS4_PA_PDMA1 + SZ_4K,
- .flags = IORESOURCE_MEM,
- },
- .irq = {IRQ_PDMA1, NO_IRQ},
- .periphid = 0x00041330,
+static struct dma_pl330_platdata exynos4_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
+ EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+
+static u8 mdma_peri[] = {
+ DMACH_MTOM_0,
+ DMACH_MTOM_1,
+ DMACH_MTOM_2,
+ DMACH_MTOM_3,
+ DMACH_MTOM_4,
+ DMACH_MTOM_5,
+ DMACH_MTOM_6,
+ DMACH_MTOM_7,
+};
+
+static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+ .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+ .peri_id = mdma_peri,
};
+static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
+ EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
+
static int __init exynos4_dma_init(void)
{
if (of_have_populated_dt())
return 0;
+ if (soc_is_exynos4210()) {
+ exynos4_pdma0_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4210_pdma0_peri);
+ exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+ exynos4_pdma1_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4210_pdma1_peri);
+ exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ exynos4_pdma0_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4212_pdma0_peri);
+ exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+ exynos4_pdma1_pdata.nr_valid_peri =
+ ARRAY_SIZE(exynos4212_pdma1_peri);
+ exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+ }
+
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
- amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+ amba_device_register(&exynos4_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
- amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+ amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+
+ dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
+ amba_device_register(&exynos4_mdma1_device, &iomem_resource);
return 0;
}
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index dd1ad55524c..9c17a0a4385 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 3df27f2d503..7517c3f417a 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -32,3 +32,5 @@ struct exynos_dvfs_info {
};
extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a..e0c86ea475e 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,12 @@
*/
.macro addruart, rp, rv, tmp
- ldr \rp, = S3C_PA_UART
- ldr \rv, = S3C_VA_UART
+ mrc p15, 0, \tmp, c0, c0, 0
+ and \tmp, \tmp, #0xf0
+ teq \tmp, #0xf0 @@ A15
+ ldreq \rp, =EXYNOS5_PA_UART
+ movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
+ ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
deleted file mode 100644
index 3ba4f547534..00000000000
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/entry-macro.S
- *
- * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for EXYNOS4 platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
- .macro disable_fiq
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf5525..00000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 80523ca9bb4..d7498afe036 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * EXYNOS4 - GPIO lib support
+ * EXYNOS - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -13,9 +12,13 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
-/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
+/* Macro for EXYNOS GPIO numbering */
+
+#define EXYNOS_GPIO_NEXT(__gpio) \
+ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+/* EXYNOS4 GPIO bank sizes */
-/* GPIO bank sizes */
#define EXYNOS4_GPIO_A0_NR (8)
#define EXYNOS4_GPIO_A1_NR (6)
#define EXYNOS4_GPIO_B_NR (8)
@@ -54,52 +57,50 @@
#define EXYNOS4_GPIO_Y6_NR (8)
#define EXYNOS4_GPIO_Z_NR (7)
-/* GPIO bank numbers */
-
-#define EXYNOS4_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+/* EXYNOS4 GPIO bank numbers */
-enum s5p_gpio_number {
+enum exynos4_gpio_number {
EXYNOS4_GPIO_A0_START = 0,
- EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
- EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
- EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
- EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
- EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
- EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
- EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
- EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
- EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
- EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
- EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
- EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
- EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
- EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
- EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
- EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
- EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
- EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
- EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
- EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
- EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
- EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
- EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
- EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
- EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
- EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
- EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
- EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
- EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
- EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
- EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
- EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
- EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
- EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
- EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
+ EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
+ EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
+ EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
+ EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
+ EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
+ EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+ EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+ EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
+ EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
+ EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
+ EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
+ EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
+ EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
+ EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
+ EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
+ EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
+ EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
+ EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
+ EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
+ EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
+ EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
+ EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
+ EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
+ EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
+ EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
+ EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
+ EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
+ EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
+ EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
+ EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
+ EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
+ EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
+ EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
+ EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
+ EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
+ EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
};
/* EXYNOS4 GPIO number definitions */
+
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
@@ -139,11 +140,147 @@ enum s5p_gpio_number {
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
/* the end of the EXYNOS4 specific gpios */
+
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-#define S3C_GPIO_END EXYNOS4_GPIO_END
-/* define the number of gpios we need to the one after the GPZ() range */
-#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
- CONFIG_SAMSUNG_GPIO_EXTRA + 1)
+/* EXYNOS5 GPIO bank sizes */
+
+#define EXYNOS5_GPIO_A0_NR (8)
+#define EXYNOS5_GPIO_A1_NR (6)
+#define EXYNOS5_GPIO_A2_NR (8)
+#define EXYNOS5_GPIO_B0_NR (5)
+#define EXYNOS5_GPIO_B1_NR (5)
+#define EXYNOS5_GPIO_B2_NR (4)
+#define EXYNOS5_GPIO_B3_NR (4)
+#define EXYNOS5_GPIO_C0_NR (7)
+#define EXYNOS5_GPIO_C1_NR (7)
+#define EXYNOS5_GPIO_C2_NR (7)
+#define EXYNOS5_GPIO_C3_NR (7)
+#define EXYNOS5_GPIO_D0_NR (8)
+#define EXYNOS5_GPIO_D1_NR (8)
+#define EXYNOS5_GPIO_Y0_NR (6)
+#define EXYNOS5_GPIO_Y1_NR (4)
+#define EXYNOS5_GPIO_Y2_NR (6)
+#define EXYNOS5_GPIO_Y3_NR (8)
+#define EXYNOS5_GPIO_Y4_NR (8)
+#define EXYNOS5_GPIO_Y5_NR (8)
+#define EXYNOS5_GPIO_Y6_NR (8)
+#define EXYNOS5_GPIO_X0_NR (8)
+#define EXYNOS5_GPIO_X1_NR (8)
+#define EXYNOS5_GPIO_X2_NR (8)
+#define EXYNOS5_GPIO_X3_NR (8)
+#define EXYNOS5_GPIO_E0_NR (8)
+#define EXYNOS5_GPIO_E1_NR (2)
+#define EXYNOS5_GPIO_F0_NR (4)
+#define EXYNOS5_GPIO_F1_NR (4)
+#define EXYNOS5_GPIO_G0_NR (8)
+#define EXYNOS5_GPIO_G1_NR (8)
+#define EXYNOS5_GPIO_G2_NR (2)
+#define EXYNOS5_GPIO_H0_NR (4)
+#define EXYNOS5_GPIO_H1_NR (8)
+#define EXYNOS5_GPIO_V0_NR (8)
+#define EXYNOS5_GPIO_V1_NR (8)
+#define EXYNOS5_GPIO_V2_NR (8)
+#define EXYNOS5_GPIO_V3_NR (8)
+#define EXYNOS5_GPIO_V4_NR (2)
+#define EXYNOS5_GPIO_Z_NR (7)
+
+/* EXYNOS5 GPIO bank numbers */
+
+enum exynos5_gpio_number {
+ EXYNOS5_GPIO_A0_START = 0,
+ EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
+ EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
+ EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
+ EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
+ EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
+ EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
+ EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
+ EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
+ EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
+ EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
+ EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+ EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
+ EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
+ EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
+ EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
+ EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
+ EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
+ EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
+ EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
+ EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
+ EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
+ EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
+ EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
+ EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
+ EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
+ EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
+ EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
+ EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
+ EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
+ EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
+ EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
+ EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
+ EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
+ EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
+ EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
+ EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
+ EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
+ EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
+};
+
+/* EXYNOS5 GPIO number definitions */
+
+#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
+#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
+#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
+#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
+#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
+#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
+#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
+#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
+#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
+#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
+#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
+#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
+#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
+#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
+#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
+#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
+#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
+#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
+#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
+#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
+#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
+#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
+#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
+#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
+#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
+#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
+#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
+#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
+#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
+#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
+#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
+#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
+#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
+#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
+#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
+#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
+#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
+#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
+
+/* the end of the EXYNOS5 specific gpios */
+
+#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
+
+/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
+
+#define S3C_GPIO_END (EXYNOS5_GPIO_END)
+
+/* define the number of gpios */
+
+#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
deleted file mode 100644
index d5478d24753..00000000000
--- a/arch/arm/mach-exynos/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/io.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6442/include/mach/io.h
- *
- * Default IO routines for EXYNOS4
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H __FILE__
-
-/* No current ISA/PCI bus support. */
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce04789..591e78521a9 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -17,158 +16,452 @@
/* PPI: Private Peripheral Interrupt */
-#define IRQ_PPI(x) (x+16)
-
-#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
+#define IRQ_PPI(x) (x + 16)
/* SPI: Shared Peripheral Interrupt */
-#define IRQ_SPI(x) (x+32)
-
-#define IRQ_EINT0 IRQ_SPI(16)
-#define IRQ_EINT1 IRQ_SPI(17)
-#define IRQ_EINT2 IRQ_SPI(18)
-#define IRQ_EINT3 IRQ_SPI(19)
-#define IRQ_EINT4 IRQ_SPI(20)
-#define IRQ_EINT5 IRQ_SPI(21)
-#define IRQ_EINT6 IRQ_SPI(22)
-#define IRQ_EINT7 IRQ_SPI(23)
-#define IRQ_EINT8 IRQ_SPI(24)
-#define IRQ_EINT9 IRQ_SPI(25)
-#define IRQ_EINT10 IRQ_SPI(26)
-#define IRQ_EINT11 IRQ_SPI(27)
-#define IRQ_EINT12 IRQ_SPI(28)
-#define IRQ_EINT13 IRQ_SPI(29)
-#define IRQ_EINT14 IRQ_SPI(30)
-#define IRQ_EINT15 IRQ_SPI(31)
-#define IRQ_EINT16_31 IRQ_SPI(32)
-
-#define IRQ_PDMA0 IRQ_SPI(35)
-#define IRQ_PDMA1 IRQ_SPI(36)
-#define IRQ_TIMER0_VIC IRQ_SPI(37)
-#define IRQ_TIMER1_VIC IRQ_SPI(38)
-#define IRQ_TIMER2_VIC IRQ_SPI(39)
-#define IRQ_TIMER3_VIC IRQ_SPI(40)
-#define IRQ_TIMER4_VIC IRQ_SPI(41)
-#define IRQ_MCT_L0 IRQ_SPI(42)
-#define IRQ_WDT IRQ_SPI(43)
-#define IRQ_RTC_ALARM IRQ_SPI(44)
-#define IRQ_RTC_TIC IRQ_SPI(45)
-#define IRQ_GPIO_XB IRQ_SPI(46)
-#define IRQ_GPIO_XA IRQ_SPI(47)
-#define IRQ_MCT_L1 IRQ_SPI(48)
-
-#define IRQ_UART0 IRQ_SPI(52)
-#define IRQ_UART1 IRQ_SPI(53)
-#define IRQ_UART2 IRQ_SPI(54)
-#define IRQ_UART3 IRQ_SPI(55)
-#define IRQ_UART4 IRQ_SPI(56)
-#define IRQ_MCT_G0 IRQ_SPI(57)
-#define IRQ_IIC IRQ_SPI(58)
-#define IRQ_IIC1 IRQ_SPI(59)
-#define IRQ_IIC2 IRQ_SPI(60)
-#define IRQ_IIC3 IRQ_SPI(61)
-#define IRQ_IIC4 IRQ_SPI(62)
-#define IRQ_IIC5 IRQ_SPI(63)
-#define IRQ_IIC6 IRQ_SPI(64)
-#define IRQ_IIC7 IRQ_SPI(65)
-#define IRQ_SPI0 IRQ_SPI(66)
-#define IRQ_SPI1 IRQ_SPI(67)
-#define IRQ_SPI2 IRQ_SPI(68)
-
-#define IRQ_USB_HOST IRQ_SPI(70)
-#define IRQ_USB_HSOTG IRQ_SPI(71)
-#define IRQ_MODEM_IF IRQ_SPI(72)
-#define IRQ_HSMMC0 IRQ_SPI(73)
-#define IRQ_HSMMC1 IRQ_SPI(74)
-#define IRQ_HSMMC2 IRQ_SPI(75)
-#define IRQ_HSMMC3 IRQ_SPI(76)
-#define IRQ_DWMCI IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0 IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1 IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI IRQ_SPI(82)
-#define IRQ_ROTATOR IRQ_SPI(83)
-#define IRQ_FIMC0 IRQ_SPI(84)
-#define IRQ_FIMC1 IRQ_SPI(85)
-#define IRQ_FIMC2 IRQ_SPI(86)
-#define IRQ_FIMC3 IRQ_SPI(87)
-#define IRQ_JPEG IRQ_SPI(88)
-#define IRQ_2D IRQ_SPI(89)
-#define IRQ_PCIE IRQ_SPI(90)
-
-#define IRQ_MIXER IRQ_SPI(91)
-#define IRQ_HDMI IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
-#define IRQ_MFC IRQ_SPI(94)
-#define IRQ_SDO IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS IRQ_SPI(96)
-#define IRQ_I2S0 IRQ_SPI(97)
-#define IRQ_I2S1 IRQ_SPI(98)
-#define IRQ_I2S2 IRQ_SPI(99)
-#define IRQ_AC97 IRQ_SPI(100)
-
-#define IRQ_SPDIF IRQ_SPI(104)
-#define IRQ_ADC0 IRQ_SPI(105)
-#define IRQ_PEN0 IRQ_SPI(106)
-#define IRQ_ADC1 IRQ_SPI(107)
-#define IRQ_PEN1 IRQ_SPI(108)
-#define IRQ_KEYPAD IRQ_SPI(109)
-#define IRQ_PMU IRQ_SPI(110)
-#define IRQ_GPS IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
-#define IRQ_SLIMBUS IRQ_SPI(113)
-
-#define IRQ_TSI IRQ_SPI(115)
-#define IRQ_SATA IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER 8
-#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR 16
-
-#define IRQ_ADC IRQ_ADC0
-#define IRQ_TC IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS 16
-#define IRQ_GPIO2_NR_GROUPS 9
-#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
+#define IRQ_SPI(x) (x + 32)
+
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER 8
+#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
+#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
+#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
+
+#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR 16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC EXYNOS4_IRQ_IIC
+#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
+#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
+#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
+#define IRQ_JPEG EXYNOS4_IRQ_JPEG
+#define IRQ_2D EXYNOS4_IRQ_2D
+
+#define IRQ_MIXER EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC EXYNOS4_IRQ_MFC
+#define IRQ_SDO EXYNOS4_IRQ_SDO
+
+#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
+
+#define IRQ_ADC EXYNOS4_IRQ_ADC0
+#define IRQ_TC EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
+
+#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
+#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
+#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
+#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
+#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
+#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
+#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
+#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
+#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
+#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
+#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
+#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
+#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
+#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
+#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
+#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
+#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
+#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
+#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
+#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
+#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
+#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
+#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
+#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
+#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
+#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
+#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
+#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
+#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
+#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
+#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
+#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
+#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
+#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
+#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
+#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
+#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
+#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
+#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
+#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
+#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
+#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
+#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
+#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
+#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
+#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
+#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
+#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
+#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
+#define EXYNOS5_IRQ_2D IRQ_SPI(91)
+#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
+#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
+#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
+#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
+#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
+#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
+#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
+#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
+#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
+#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
+#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
+#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
+#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
+#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
+#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
+
+#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
+#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
+#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
+#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
+#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
+#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
+#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
+#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
+#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
+
+#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
+#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
+#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
+#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
+#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
+
+#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
+#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
+
+#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
+
+#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
+#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
+#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
+
+#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
+#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
+#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
+#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
+#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
+
+#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
+
+#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
+#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
+
+#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
+#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
+
+#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
+#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
+
+#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
+#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
+
+#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
+#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
+
+#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
+#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
+
+#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
+#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
+
+#define EXYNOS5_MAX_COMBINER_NR 32
+
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
+#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
+#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
+#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
+
+#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
+ EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
+
+#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
+#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
+#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
/* Set the default NR_IRQS */
-#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
+#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22a2bb..6e6d11ff352 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,12 +25,17 @@
#define EXYNOS4_PA_SYSRAM0 0x02025000
#define EXYNOS4_PA_SYSRAM1 0x02020000
+#define EXYNOS5_PA_SYSRAM 0x02020000
#define EXYNOS4_PA_FIMC0 0x11800000
#define EXYNOS4_PA_FIMC1 0x11810000
#define EXYNOS4_PA_FIMC2 0x11820000
#define EXYNOS4_PA_FIMC3 0x11830000
+#define EXYNOS4_PA_JPEG 0x11840000
+
+#define EXYNOS4_PA_G2D 0x12800000
+
#define EXYNOS4_PA_I2S0 0x03830000
#define EXYNOS4_PA_I2S1 0xE3100000
#define EXYNOS4_PA_I2S2 0xE2A00000
@@ -44,32 +49,50 @@
#define EXYNOS4_PA_ONENAND 0x0C000000
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
-#define EXYNOS4_PA_CHIPID 0x10000000
+#define EXYNOS_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000
+#define EXYNOS5_PA_SYSCON 0x10050100
+
#define EXYNOS4_PA_PMU 0x10020000
+#define EXYNOS5_PA_PMU 0x10040000
+
#define EXYNOS4_PA_CMU 0x10030000
+#define EXYNOS5_PA_CMU 0x10010000
#define EXYNOS4_PA_SYSTIMER 0x10050000
+#define EXYNOS5_PA_SYSTIMER 0x101C0000
+
#define EXYNOS4_PA_WATCHDOG 0x10060000
+#define EXYNOS5_PA_WATCHDOG 0x101D0000
+
#define EXYNOS4_PA_RTC 0x10070000
#define EXYNOS4_PA_KEYPAD 0x100A0000
#define EXYNOS4_PA_DMC0 0x10400000
+#define EXYNOS4_PA_DMC1 0x10410000
#define EXYNOS4_PA_COMBINER 0x10440000
+#define EXYNOS5_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
+#define EXYNOS5_PA_GIC_CPU 0x10480000
+#define EXYNOS5_PA_GIC_DIST 0x10490000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_L2CC 0x10502000
-#define EXYNOS4_PA_MDMA 0x10810000
+#define EXYNOS4_PA_MDMA0 0x10810000
+#define EXYNOS4_PA_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
+#define EXYNOS5_PA_MDMA0 0x10800000
+#define EXYNOS5_PA_MDMA1 0x11C10000
+#define EXYNOS5_PA_PDMA0 0x121A0000
+#define EXYNOS5_PA_PDMA1 0x121B0000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
@@ -91,10 +114,13 @@
#define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000
-
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
#define EXYNOS4_PA_GPIO3 0x03860000
+#define EXYNOS5_PA_GPIO1 0x11400000
+#define EXYNOS5_PA_GPIO2 0x13400000
+#define EXYNOS5_PA_GPIO3 0x10D10000
+#define EXYNOS5_PA_GPIO4 0x03860000
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
@@ -109,6 +135,7 @@
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
#define EXYNOS4_PA_SROMC 0x12570000
+#define EXYNOS5_PA_SROMC 0x12250000
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_OHCI 0x12590000
@@ -116,6 +143,7 @@
#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
+#define EXYNOS5_PA_UART 0x12C00000
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
@@ -124,6 +152,7 @@
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000
@@ -133,8 +162,10 @@
#define EXYNOS4_PA_SPDIF 0x139B0000
#define EXYNOS4_PA_TIMER 0x139D0000
+#define EXYNOS5_PA_TIMER 0x12DD0000
#define EXYNOS4_PA_SDRAM 0x40000000
+#define EXYNOS5_PA_SDRAM 0x40000000
/* Compatibiltiy Defines */
@@ -152,7 +183,6 @@
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART EXYNOS4_PA_UART
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
@@ -162,6 +192,8 @@
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
+#define S5P_PA_JPEG EXYNOS4_PA_JPEG
+#define S5P_PA_G2D EXYNOS4_PA_G2D
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
@@ -181,15 +213,18 @@
/* Compatibility UART */
-#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0 0x13800000
+#define EXYNOS4_PA_UART1 0x13810000
+#define EXYNOS4_PA_UART2 0x13820000
+#define EXYNOS4_PA_UART3 0x13830000
+#define EXYNOS4_SZ_UART SZ_256
-#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0 S5P_PA_UART(0)
-#define S5P_PA_UART1 S5P_PA_UART(1)
-#define S5P_PA_UART2 S5P_PA_UART(2)
-#define S5P_PA_UART3 S5P_PA_UART(3)
-#define S5P_PA_UART4 S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0 0x12C00000
+#define EXYNOS5_PA_UART1 0x12C10000
+#define EXYNOS5_PA_UART2 0x12C20000
+#define EXYNOS5_PA_UART3 0x12C30000
+#define EXYNOS5_SZ_UART SZ_256
-#define S5P_SZ_UART SZ_256
+#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index 632dd563013..e76b7faba66 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -22,11 +22,13 @@ enum sys_powerdown {
NUM_SYS_POWERDOWN,
};
+extern unsigned long l2x0_regs_phys;
struct exynos4_pmu_conf {
void __iomem *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern void s3c_cpu_resume(void);
#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe9482..d9578a58ae7 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,315 @@
#include <plat/cpu.h>
#include <mach/map.h>
-#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
-
-#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
-
-#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
-
-#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
-
-#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
-#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
-#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
-#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
-
-#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
-
-#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
-
-#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
-
-#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
-
-#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
- S5P_CLKREG(0x0C930) : \
- S5P_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
- S5P_CLKREG(0x0C960) : \
- S5P_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
-#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
-#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
-
-#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
-#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
-#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
-#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
-
-#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
- S5P_CLKREG(0x14004) : \
- S5P_CLKREG(0x10008))
-#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
- S5P_CLKREG(0x14108) : \
- S5P_CLKREG(0x10108))
-#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
- S5P_CLKREG(0x1410C) : \
- S5P_CLKREG(0x1010C))
-
-#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
-#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
-
-#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
-#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
-#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
-
-#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
-#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
-
-#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
-
-#define S5P_APLLCON0_ENABLE_SHIFT (31)
-#define S5P_APLLCON0_LOCKED_SHIFT (29)
-#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
-
-#define S5P_EPLLCON0_ENABLE_SHIFT (31)
-#define S5P_EPLLCON0_LOCKED_SHIFT (29)
-
-#define S5P_VPLLCON0_ENABLE_SHIFT (31)
-#define S5P_VPLLCON0_LOCKED_SHIFT (29)
-
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
-#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
-#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
-#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
-#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
-
-#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
-#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
-#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
-#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
-#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
-#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
-#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
-#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
-#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
-#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
-#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
-#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
-#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
-
-#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
-#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
-#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
+
+#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
+
+#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
+
+#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
+#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
+
+#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
+#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
+
+#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
+
+#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
+
+#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
+#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
+
+#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
+
+#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
+#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
+ EXYNOS_CLKREG(0x0C930) : \
+ EXYNOS_CLKREG(0x04930))
+#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
+#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
+#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
+#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
+ EXYNOS_CLKREG(0x0C960) : \
+ EXYNOS_CLKREG(0x08960))
+#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
+#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
+
+#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
+#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
+#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
+#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
+#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
+
+#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
+#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
+
+#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
+#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
+ EXYNOS_CLKREG(0x14004) : \
+ EXYNOS_CLKREG(0x10008))
+#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
+#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
+#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
+ EXYNOS_CLKREG(0x14108) : \
+ EXYNOS_CLKREG(0x10108))
+#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
+ EXYNOS_CLKREG(0x1410C) : \
+ EXYNOS_CLKREG(0x1010C))
+
+#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
+#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
+
+#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
+#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
+#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
+
+#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
+#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
+
+#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
+
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
+#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
+
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
+
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
+
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+
+#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
+#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
+
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
/* Only for EXYNOS4210 */
-#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
+#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
+
+/* Only for EXYNOS4212 */
+
+#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
+
+#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
+
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
+
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
+#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
+#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
+#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
+#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
+
+#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
-#define S5P_EPLL_CON S5P_EPLL_CON0
+#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a..e4b5b60dcb8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
#include <mach/map.h>
#include <mach/irqs.h>
+#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
+#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
+#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
+#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
+#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
+
+#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
+
+/* compatibility for plat-s5p/irq-pm.c */
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
@@ -28,15 +37,4 @@
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
-#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
-
#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fe..4c53f38b5a9 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
#define S5P_SWRESET S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
deleted file mode 100644
index 0063a6de3dc..00000000000
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/system.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
- /* nothing here yet */
-}
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9ac..2979995d5a6 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,35 @@
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H __FILE__
+#include <asm/mach-types.h>
+
#include <mach/map.h>
+
+volatile u8 *uart_base;
+
#include <plat/uncompress.h>
+static unsigned int __raw_readl(unsigned int ptr)
+{
+ return *((volatile unsigned int *)ptr);
+}
+
static void arch_detect_cpu(void)
{
- /* we do not need to do any cpu detection here at the moment. */
+ u32 chip_id = __raw_readl(EXYNOS_PA_CHIPID);
+
+ /*
+ * product_id is bits 31:12
+ * bits 23:20 describe the exynosX family
+ *
+ */
+ chip_id >>= 20;
+ chip_id &= 0xf;
+
+ if (chip_id == 0x5)
+ uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+ else
+ uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
/*
* For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e6b02fdf1b0..8245f1c761d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -37,13 +37,13 @@
* data from the device tree.
*/
static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
"exynos4210-uart.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
"exynos4210-uart.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
"exynos4210-uart.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
"exynos4-sdhci.0", NULL),
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 00000000000..4711c8920e3
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
+/*
+ * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+ "exynos4210-uart.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+ "exynos4210-uart.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+ "exynos4210-uart.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+ "exynos4210-uart.3", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ {},
+};
+
+static void __init exynos5250_dt_map_io(void)
+{
+ exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos5250_dt_machine_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5250_auxdata_lookup, NULL);
+}
+
+static char const *exynos5250_dt_compat[] __initdata = {
+ "samsung,exynos5250",
+ NULL
+};
+
+DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ .init_irq = exynos5_init_irq,
+ .map_io = exynos5250_dt_map_io,
+ .handle_irq = gic_handle_irq,
+ .init_machine = exynos5250_dt_machine_init,
+ .timer = &exynos4_timer,
+ .dt_compat = exynos5250_dt_compat,
+ .restart = exynos5_restart,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 435261f83f4..ed90aef404c 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -28,6 +28,7 @@
#include <video/platform_lcd.h>
#include <media/m5mols.h>
+#include <media/s5k6aa.h>
#include <media/s5p_fimc.h>
#include <media/v4l2-mediabus.h>
@@ -75,6 +76,7 @@ enum fixed_regulator_id {
FIXED_REG_ID_MAX8903,
FIXED_REG_ID_CAM_A28V,
FIXED_REG_ID_CAM_12V,
+ FIXED_REG_ID_CAM_VT_15V,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -109,13 +111,14 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_DISABLE | MMC_CAP_ERASE),
+ MMC_CAP_ERASE),
+ .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply emmc_supplies[] = {
- REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+ REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
REGULATOR_SUPPLY("vmmc", "dw_mmc"),
};
@@ -148,8 +151,7 @@ static struct platform_device emmc_fixed_voltage = {
static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_DISABLE,
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
@@ -306,49 +308,7 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
};
/* TSP */
-static u8 mxt_init_vals[] = {
- /* MXT_GEN_COMMAND(6) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* MXT_GEN_POWER(7) */
- 0x20, 0xff, 0x32,
- /* MXT_GEN_ACQUIRE(8) */
- 0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
- /* MXT_TOUCH_MULTI(9) */
- 0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00,
- /* MXT_TOUCH_KEYARRAY(15) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x00,
- /* MXT_SPT_GPIOPWM(19) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* MXT_PROCI_GRIPFACE(20) */
- 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
- 0x0f, 0x0a,
- /* MXT_PROCG_NOISE(22) */
- 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
- 0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
- /* MXT_TOUCH_PROXIMITY(23) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00,
- /* MXT_PROCI_ONETOUCH(24) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* MXT_SPT_SELFTEST(25) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- /* MXT_PROCI_TWOTOUCH(27) */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* MXT_SPT_CTECONFIG(28) */
- 0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
-};
-
static struct mxt_platform_data mxt_platform_data = {
- .config = mxt_init_vals,
- .config_length = ARRAY_SIZE(mxt_init_vals),
-
.x_line = 18,
.y_line = 11,
.x_size = 1024,
@@ -399,6 +359,9 @@ static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
};
+static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
+ REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
+};
static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
};
@@ -413,7 +376,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
};
static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
- REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+ REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
};
static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
@@ -431,7 +394,7 @@ static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
- REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+ REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
};
static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
@@ -546,6 +509,8 @@ static struct regulator_init_data __initdata max8997_ldo6_data = {
.enabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
+ .consumer_supplies = nuri_max8997_ldo6_consumer,
};
static struct regulator_init_data __initdata max8997_ldo7_data = {
@@ -565,7 +530,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = {
static struct regulator_init_data __initdata max8997_ldo8_data = {
.constraints = {
- .name = "VUSB/VDAC_3.3V_C210",
+ .name = "VUSB+VDAC_3.3V_C210",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
@@ -742,7 +707,7 @@ static struct regulator_init_data __initdata max8997_buck2_data = {
.constraints = {
.name = "VINT_1.1V_C210",
.min_uV = 900000,
- .max_uV = 1100000,
+ .max_uV = 1200000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.state_mem = {
@@ -957,7 +922,6 @@ static struct max8997_platform_data __initdata nuri_max8997_pdata = {
.regulators = nuri_max8997_regulators,
.buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
- .buck2_gpiodvs = true,
.buck1_voltage[0] = 1350000, /* 1.35V */
.buck1_voltage[1] = 1300000, /* 1.3V */
@@ -1116,7 +1080,30 @@ static void __init nuri_ehci_init(void)
}
/* CAMERA */
+static struct regulator_consumer_supply cam_vt_cam15_supply =
+ REGULATOR_SUPPLY("vdd_core", "6-003c");
+
+static struct regulator_init_data cam_vt_cam15_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cam_vt_cam15_supply,
+};
+
+static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
+ .supply_name = "VT_CAM_1.5V",
+ .microvolts = 1500000,
+ .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
+ .enable_high = 1,
+ .init_data = &cam_vt_cam15_reg_init_data,
+};
+
+static struct platform_device cam_vt_cam15_fixed_rdev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
+ .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
+};
+
static struct regulator_consumer_supply cam_vdda_supply[] = {
+ REGULATOR_SUPPLY("vdda", "6-003c"),
REGULATOR_SUPPLY("a_sensor", "0-001f"),
};
@@ -1173,6 +1160,21 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
+#define GPIO_CAM_VT_NSTBY EXYNOS4_GPL2(0)
+#define GPIO_CAM_VT_NRST EXYNOS4_GPL2(1)
+
+static struct s5k6aa_platform_data s5k6aa_pldata = {
+ .mclk_frequency = 24000000UL,
+ .gpio_reset = { GPIO_CAM_VT_NRST, 0 },
+ .gpio_stby = { GPIO_CAM_VT_NSTBY, 0 },
+ .bus_type = V4L2_MBUS_PARALLEL,
+ .horiz_flip = 1,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+ I2C_BOARD_INFO("S5K6AA", 0x3c),
+ .platform_data = &s5k6aa_pldata,
+};
static struct m5mols_platform_data m5mols_platdata = {
.gpio_reset = GPIO_CAM_MEGA_RST,
@@ -1185,6 +1187,13 @@ static struct i2c_board_info m5mols_board_info = {
static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
{
+ .flags = V4L2_MBUS_PCLK_SAMPLE_RISING |
+ V4L2_MBUS_VSYNC_ACTIVE_LOW,
+ .bus_type = FIMC_ITU_601,
+ .board_info = &s5k6aa_board_info,
+ .clk_frequency = 24000000UL,
+ .i2c_bus_num = 6,
+ }, {
.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
V4L2_MBUS_VSYNC_ACTIVE_LOW,
.bus_type = FIMC_MIPI_CSI2,
@@ -1200,11 +1209,13 @@ static struct s5p_platform_fimc fimc_md_platdata = {
};
static struct gpio nuri_camera_gpios[] = {
+ { GPIO_CAM_VT_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
+ { GPIO_CAM_VT_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
{ GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
{ GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
};
-static void nuri_camera_init(void)
+static void __init nuri_camera_init(void)
{
s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
&s5p_device_mipi_csis0);
@@ -1224,6 +1235,8 @@ static void nuri_camera_init(void)
pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
/* Free GPIOs controlled directly by the sensor drivers. */
+ gpio_free(GPIO_CAM_VT_NRST);
+ gpio_free(GPIO_CAM_VT_NSTBY);
gpio_free(GPIO_CAM_MEGA_RST);
if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
@@ -1234,15 +1247,27 @@ static void nuri_camera_init(void)
s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
}
+static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
+ .frequency = 400000U,
+ .sda_delay = 200,
+ .bus_num = 6,
+};
+
static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
.frequency = 400000U,
.sda_delay = 200,
};
+/* DEVFREQ controlling memory/bus */
+static struct platform_device exynos4_bus_devfreq = {
+ .name = "exynos4210-busfreq",
+};
+
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
&s3c_device_i2c0,
+ &s3c_device_i2c6,
&emmc_fixed_voltage,
&s5p_device_mipi_csis0,
&s5p_device_fimc0,
@@ -1259,13 +1284,12 @@ static struct platform_device *nuri_devices[] __initdata = {
&s3c_device_i2c3,
&i2c9_gpio,
&s3c_device_adc,
+ &s5p_device_g2d,
+ &s5p_device_jpeg,
&s3c_device_rtc,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
- &exynos4_device_pd[PD_MFC],
- &exynos4_device_pd[PD_LCD0],
- &exynos4_device_pd[PD_CAM],
&s5p_device_fimc_md,
/* NURI Devices */
@@ -1274,12 +1298,15 @@ static struct platform_device *nuri_devices[] __initdata = {
&nuri_backlight_device,
&max8903_fixed_reg_dev,
&nuri_max8903_device,
+ &cam_vt_cam15_fixed_rdev,
&cam_vdda_fixed_rdev,
&cam_8m_12v_fixed_rdev,
+ &exynos4_bus_devfreq,
};
static void __init nuri_map_io(void)
{
+ clk_xusbxti.rate = 24000000;
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
@@ -1305,24 +1332,16 @@ static void __init nuri_machine_init(void)
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
+ s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
s5p_fimd0_set_platdata(&nuri_fb_pdata);
nuri_camera_init();
nuri_ehci_init();
- clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
- s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
- s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
- s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 0679b8ad2d1..878d4c99142 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -20,6 +20,7 @@
#include <linux/regulator/machine.h>
#include <linux/mfd/max8997.h>
#include <linux/lcd.h>
+#include <linux/rfkill-gpio.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -235,6 +236,7 @@ static struct regulator_init_data __initdata max8997_ldo9_data = {
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
+ .always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
@@ -278,6 +280,7 @@ static struct regulator_init_data __initdata max8997_ldo14_data = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
+ .always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
@@ -293,6 +296,7 @@ static struct regulator_init_data __initdata max8997_ldo17_data = {
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
+ .always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
@@ -412,7 +416,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
{ MAX8997_BUCK7, &max8997_buck7_data },
};
-struct max8997_platform_data __initdata origen_max8997_pdata = {
+static struct max8997_platform_data __initdata origen_max8997_pdata = {
.num_regulators = ARRAY_SIZE(origen_max8997_regulators),
.regulators = origen_max8997_regulators,
@@ -602,6 +606,23 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
+/* Bluetooth rfkill gpio platform data */
+struct rfkill_gpio_platform_data origen_bt_pdata = {
+ .reset_gpio = EXYNOS4_GPX2(2),
+ .shutdown_gpio = -1,
+ .type = RFKILL_TYPE_BLUETOOTH,
+ .name = "origen-bt",
+};
+
+/* Bluetooth Platform device */
+static struct platform_device origen_device_bluetooth = {
+ .name = "rfkill_gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &origen_bt_pdata,
+ },
+};
+
static struct platform_device *origen_devices[] __initdata = {
&s3c_device_hsmmc2,
&s3c_device_hsmmc0,
@@ -613,23 +634,20 @@ static struct platform_device *origen_devices[] __initdata = {
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
+ &s5p_device_fimc_md,
&s5p_device_fimd0,
+ &s5p_device_g2d,
&s5p_device_hdmi,
&s5p_device_i2c_hdmiphy,
+ &s5p_device_jpeg,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&s5p_device_mixer,
&exynos4_device_ohci,
- &exynos4_device_pd[PD_LCD0],
- &exynos4_device_pd[PD_TV],
- &exynos4_device_pd[PD_G3D],
- &exynos4_device_pd[PD_LCD1],
- &exynos4_device_pd[PD_CAM],
- &exynos4_device_pd[PD_GPS],
- &exynos4_device_pd[PD_MFC],
&origen_device_gpiokeys,
&origen_lcd_hv070wsa,
+ &origen_device_bluetooth,
};
/* LCD Backlight data */
@@ -643,6 +661,16 @@ static struct platform_pwm_backlight_data origen_bl_data = {
.pwm_period_ns = 1000,
};
+static void __init origen_bt_setup(void)
+{
+ gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
+ /* 4 UART Pins configuration */
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
+ /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
+ s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
+ s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
+}
+
static void s5p_tv_setup(void)
{
/* Direct HPD to HDMI chip */
@@ -695,14 +723,9 @@ static void __init origen_machine_init(void)
platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
- s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
- s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
- s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
-
- s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
-
samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+
+ origen_bt_setup();
}
MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index b2c5557f50e..83b91fa777c 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -270,6 +270,9 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
+ &s5p_device_fimc_md,
+ &s5p_device_g2d,
+ &s5p_device_jpeg,
&exynos4_device_ac97,
&exynos4_device_i2s0,
&exynos4_device_ohci,
@@ -277,13 +280,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
- &exynos4_device_pd[PD_MFC],
- &exynos4_device_pd[PD_G3D],
- &exynos4_device_pd[PD_LCD0],
- &exynos4_device_pd[PD_LCD1],
- &exynos4_device_pd[PD_CAM],
- &exynos4_device_pd[PD_TV],
- &exynos4_device_pd[PD_GPS],
&exynos4_device_spdif,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
@@ -336,10 +332,6 @@ static void s5p_tv_setup(void)
WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-
- /* setup dependencies between TV devices */
- s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
- s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
}
static void __init smdkv310_map_io(void)
@@ -379,7 +371,6 @@ static void __init smdkv310_machine_init(void)
clk_xusbxti.rate = 24000000;
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
- s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 38939956c34..a34036eb8ba 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -29,6 +29,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
+#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
@@ -39,6 +40,7 @@
#include <plat/pd.h>
#include <plat/regs-fb-v4.h>
#include <plat/fimc-core.h>
+#include <plat/s5p-time.h>
#include <plat/camport.h>
#include <plat/mipi_csis.h>
@@ -47,6 +49,7 @@
#include <media/v4l2-mediabus.h>
#include <media/s5p_fimc.h>
#include <media/m5mols.h>
+#include <media/s5k6aa.h>
#include "common.h"
@@ -123,8 +126,10 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
static struct regulator_consumer_supply lp3974_buck2_consumer =
REGULATOR_SUPPLY("vddg3d", NULL);
-static struct regulator_consumer_supply lp3974_buck3_consumer =
- REGULATOR_SUPPLY("vdet", "s5p-sdo");
+static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
+ REGULATOR_SUPPLY("vdet", "s5p-sdo"),
+ REGULATOR_SUPPLY("vdd_reg", "0-003c"),
+};
static struct regulator_init_data lp3974_buck1_data = {
.constraints = {
@@ -169,8 +174,8 @@ static struct regulator_init_data lp3974_buck3_data = {
.enabled = 1,
},
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &lp3974_buck3_consumer,
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
+ .consumer_supplies = lp3974_buck3_consumer,
};
static struct regulator_init_data lp3974_buck4_data = {
@@ -303,6 +308,9 @@ static struct regulator_init_data lp3974_ldo8_data = {
.consumer_supplies = lp3974_ldo8_consumer,
};
+static struct regulator_consumer_supply lp3974_ldo9_consumer =
+ REGULATOR_SUPPLY("vddio", "0-003c");
+
static struct regulator_init_data lp3974_ldo9_data = {
.constraints = {
.name = "VCC_2.8V",
@@ -314,6 +322,8 @@ static struct regulator_init_data lp3974_ldo9_data = {
.enabled = 1,
},
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &lp3974_ldo9_consumer,
};
static struct regulator_init_data lp3974_ldo10_data = {
@@ -412,6 +422,7 @@ static struct regulator_init_data lp3974_ldo15_data = {
};
static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+ REGULATOR_SUPPLY("vdda", "0-003c"),
REGULATOR_SUPPLY("a_sensor", "0-001f"),
};
@@ -736,14 +747,14 @@ static struct platform_device universal_gpio_keys = {
static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_DISABLE),
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply mmc0_supplies[] = {
- REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+ REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
};
static struct regulator_init_data mmc0_fixed_voltage_init_data = {
@@ -775,8 +786,7 @@ static struct platform_device mmc0_fixed_voltage = {
static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_DISABLE,
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
@@ -787,8 +797,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
- MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_DISABLE,
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
};
@@ -819,6 +828,8 @@ static struct s3c_fb_pd_win universal_fb_win0 = {
},
.max_bpp = 32,
.default_bpp = 16,
+ .virtual_x = 480,
+ .virtual_y = 2 * 800,
};
static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
@@ -830,6 +841,28 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
+static struct regulator_consumer_supply cam_vt_dio_supply =
+ REGULATOR_SUPPLY("vdd_core", "0-003c");
+
+static struct regulator_init_data cam_vt_dio_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cam_vt_dio_supply,
+};
+
+static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
+ .supply_name = "CAM_VT_D_IO",
+ .microvolts = 2800000,
+ .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
+ .enable_high = 1,
+ .init_data = &cam_vt_dio_reg_init_data,
+};
+
+static struct platform_device cam_vt_dio_fixed_reg_dev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
+ .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
+};
+
static struct regulator_consumer_supply cam_i_core_supply =
REGULATOR_SUPPLY("core", "0-001f");
@@ -885,6 +918,28 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
+#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7)
+#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6)
+
+static int s5k6aa_set_power(int on)
+{
+ gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+ return 0;
+}
+
+static struct s5k6aa_platform_data s5k6aa_platdata = {
+ .mclk_frequency = 21600000UL,
+ .gpio_reset = { GPIO_CAM_VGA_NRST, 0 },
+ .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 },
+ .bus_type = V4L2_MBUS_PARALLEL,
+ .horiz_flip = 1,
+ .set_power = s5k6aa_set_power,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+ I2C_BOARD_INFO("S5K6AA", 0x3C),
+ .platform_data = &s5k6aa_platdata,
+};
static int m5mols_set_power(struct device *dev, int on)
{
@@ -909,6 +964,14 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
.mux_id = 0,
.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
V4L2_MBUS_VSYNC_ACTIVE_LOW,
+ .bus_type = FIMC_ITU_601,
+ .board_info = &s5k6aa_board_info,
+ .i2c_bus_num = 0,
+ .clk_frequency = 24000000UL,
+ }, {
+ .mux_id = 0,
+ .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+ V4L2_MBUS_VSYNC_ACTIVE_LOW,
.bus_type = FIMC_MIPI_CSI2,
.board_info = &m5mols_board_info,
.i2c_bus_num = 0,
@@ -927,9 +990,11 @@ static struct gpio universal_camera_gpios[] = {
{ GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
{ GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
{ GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+ { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
+ { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
};
-static void universal_camera_init(void)
+static void __init universal_camera_init(void)
{
s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
&s5p_device_mipi_csis0);
@@ -950,6 +1015,8 @@ static void universal_camera_init(void)
/* Free GPIOs controlled directly by the sensor drivers. */
gpio_free(GPIO_CAM_MEGA_nRST);
gpio_free(GPIO_CAM_8M_ISP_INT);
+ gpio_free(GPIO_CAM_VGA_NRST);
+ gpio_free(GPIO_CAM_VGA_NSTBY);
if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
pr_err("Camera port A setup failed\n");
@@ -962,6 +1029,7 @@ static struct platform_device *universal_devices[] __initdata = {
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
+ &s5p_device_g2d,
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
@@ -971,7 +1039,6 @@ static struct platform_device *universal_devices[] __initdata = {
&s3c_device_i2c5,
&s5p_device_i2c_hdmiphy,
&hdmi_fixed_voltage,
- &exynos4_device_pd[PD_TV],
&s5p_device_hdmi,
&s5p_device_sdo,
&s5p_device_mixer,
@@ -981,12 +1048,11 @@ static struct platform_device *universal_devices[] __initdata = {
&universal_gpio_keys,
&s5p_device_onenand,
&s5p_device_fimd0,
+ &s5p_device_jpeg,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
- &exynos4_device_pd[PD_MFC],
- &exynos4_device_pd[PD_LCD0],
- &exynos4_device_pd[PD_CAM],
+ &cam_vt_dio_fixed_reg_dev,
&cam_i_core_fixed_reg_dev,
&cam_s_if_fixed_reg_dev,
&s5p_device_fimc_md,
@@ -994,21 +1060,19 @@ static struct platform_device *universal_devices[] __initdata = {
static void __init universal_map_io(void)
{
+ clk_xusbxti.rate = 24000000;
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+ s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
}
-void s5p_tv_setup(void)
+static void s5p_tv_setup(void)
{
/* direct HPD to HDMI chip */
gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-
- /* setup dependencies between TV devices */
- s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
- s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
}
static void __init universal_reserve(void)
@@ -1042,15 +1106,6 @@ static void __init universal_machine_init(void)
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-
- s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
- s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
-
- s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
- s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@@ -1060,7 +1115,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io,
.handle_irq = gic_handle_irq,
.init_machine = universal_machine_init,
- .timer = &exynos4_timer,
+ .timer = &s5p_timer,
.reserve = &universal_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527d091..897d9a9cf22 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -21,6 +21,7 @@
#include <linux/percpu.h>
#include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
#include <plat/cpu.h>
@@ -29,12 +30,13 @@
#include <mach/regs-mct.h>
#include <asm/mach/time.h>
+#define TICK_BASE_CNT 1
+
enum {
MCT_INT_SPI,
MCT_INT_PPI
};
-static unsigned long clk_cnt_per_tick;
static unsigned long clk_rate;
static unsigned int mct_int_type;
@@ -205,11 +207,14 @@ static int exynos4_comp_set_next_event(unsigned long cycles,
static void exynos4_comp_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
+ unsigned long cycles_per_jiffy;
exynos4_mct_comp0_stop();
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+ cycles_per_jiffy =
+ (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+ exynos4_mct_comp0_start(mode, cycles_per_jiffy);
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -248,9 +253,7 @@ static struct irqaction mct_comp_event_irq = {
static void exynos4_clockevent_init(void)
{
- clk_cnt_per_tick = clk_rate / 2 / HZ;
-
- clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+ clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
mct_comp_device.max_delta_ns =
clockevent_delta2ns(0xffffffff, &mct_comp_device);
mct_comp_device.min_delta_ns =
@@ -258,7 +261,10 @@ static void exynos4_clockevent_init(void)
mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(&mct_comp_device);
- setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+ if (soc_is_exynos5250())
+ setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
+ else
+ setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
@@ -314,12 +320,15 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+ unsigned long cycles_per_jiffy;
exynos4_mct_tick_stop(mevt);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+ cycles_per_jiffy =
+ (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+ exynos4_mct_tick_start(cycles_per_jiffy, mevt);
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -375,7 +384,7 @@ static struct irqaction mct_tick1_event_irq = {
.handler = exynos4_mct_tick_isr,
};
-static void exynos4_mct_tick_init(struct clock_event_device *evt)
+static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
@@ -393,7 +402,7 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
evt->rating = 450;
- clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+ clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
evt->max_delta_ns =
clockevent_delta2ns(0x7fffffff, evt);
evt->min_delta_ns =
@@ -401,33 +410,27 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
clockevents_register_device(evt);
- exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
+ exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
mct_tick0_event_irq.dev_id = mevt;
- evt->irq = IRQ_MCT_L0;
- setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+ evt->irq = EXYNOS4_IRQ_MCT_L0;
+ setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = mevt;
- evt->irq = IRQ_MCT_L1;
- setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
- irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+ evt->irq = EXYNOS4_IRQ_MCT_L1;
+ setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
+ irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
}
} else {
- enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
+ enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
}
-}
-
-/* Setup the local clock events for a CPU */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
- exynos4_mct_tick_init(evt);
return 0;
}
-void local_timer_stop(struct clock_event_device *evt)
+static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
unsigned int cpu = smp_processor_id();
evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
@@ -437,8 +440,13 @@ void local_timer_stop(struct clock_event_device *evt)
else
remove_irq(evt->irq, &mct_tick1_event_irq);
else
- disable_percpu_irq(IRQ_MCT_LOCALTIMER);
+ disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
}
+
+static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
+ .setup = exynos4_local_timer_setup,
+ .stop = exynos4_local_timer_stop,
+};
#endif /* CONFIG_LOCAL_TIMERS */
static void __init exynos4_timer_resources(void)
@@ -452,12 +460,14 @@ static void __init exynos4_timer_resources(void)
if (mct_int_type == MCT_INT_PPI) {
int err;
- err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+ err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n",
- IRQ_MCT_LOCALTIMER, err);
+ EXYNOS_IRQ_MCT_LOCALTIMER, err);
}
+
+ local_timer_register(&exynos4_mct_tick_ops);
#endif /* CONFIG_LOCAL_TIMERS */
}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a1eb6..36c3984aaa4 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
- ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+ if (soc_is_exynos5250())
+ ncores = 2;
+ else
+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
/* sanity check */
if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
-
- scu_enable(scu_base_addr());
+ if (!soc_is_exynos5250())
+ scu_enable(scu_base_addr());
/*
* Write the address of secondary startup into the
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e1901305177..428cfeb5772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
- { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
- { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
- { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
- { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
- { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
- { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
- { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
- { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
- { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
+ { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
+ { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
+ { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
+ { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
static struct sleep_save exynos4210_set_clksrc[] = {
- { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
+ { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
};
static struct sleep_save exynos4_epll_save[] = {
- SAVE_ITEM(S5P_EPLL_CON0),
- SAVE_ITEM(S5P_EPLL_CON1),
+ SAVE_ITEM(EXYNOS4_EPLL_CON0),
+ SAVE_ITEM(EXYNOS4_EPLL_CON1),
};
static struct sleep_save exynos4_vpll_save[] = {
- SAVE_ITEM(S5P_VPLL_CON0),
- SAVE_ITEM(S5P_VPLL_CON1),
+ SAVE_ITEM(EXYNOS4_VPLL_CON0),
+ SAVE_ITEM(EXYNOS4_VPLL_CON1),
};
static struct sleep_save exynos4_core_save[] = {
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_SROM_BC3),
};
-static struct sleep_save exynos4_l2cc_save[] = {
- SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void)
u32 tmp;
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
- s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
@@ -239,7 +231,7 @@ static void exynos4_restore_pll(void)
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, S5P_EPLL_LOCK);
+ __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +249,7 @@ static void exynos4_restore_pll(void)
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, S5P_VPLL_LOCK);
+ __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +260,14 @@ static void exynos4_restore_pll(void)
do {
if (epll_wait) {
- pll_con = __raw_readl(S5P_EPLL_CON0);
- if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+ pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+ if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
- pll_con = __raw_readl(S5P_VPLL_CON0);
- if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+ pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+ if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
} while (epll_wait || vpll_wait);
@@ -388,13 +380,6 @@ static void exynos4_pm_resume(void)
scu_enable(S5P_VA_SCU);
#endif
-#ifdef CONFIG_CACHE_L2X0
- s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
- outer_inv_all();
- /* enable L2X0*/
- writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
-#endif
-
early_wakeup:
return;
}
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
new file mode 100644
index 00000000000..13b306808b4
--- /dev/null
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -0,0 +1,201 @@
+/*
+ * Exynos Generic power domain support.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Implementation of Exynos specific power domain control which is used in
+ * conjunction with runtime-pm. Support for both device-tree and non-device-tree
+ * based power domain support is included.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/pm_domain.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+
+#include <mach/regs-pmu.h>
+#include <plat/devs.h>
+
+/*
+ * Exynos specific wrapper around the generic power domain
+ */
+struct exynos_pm_domain {
+ void __iomem *base;
+ char const *name;
+ bool is_off;
+ struct generic_pm_domain pd;
+};
+
+static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
+{
+ struct exynos_pm_domain *pd;
+ void __iomem *base;
+ u32 timeout, pwr;
+ char *op;
+
+ pd = container_of(domain, struct exynos_pm_domain, pd);
+ base = pd->base;
+
+ pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
+ __raw_writel(pwr, base);
+
+ /* Wait max 1ms */
+ timeout = 10;
+
+ while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
+ if (!timeout) {
+ op = (power_on) ? "enable" : "disable";
+ pr_err("Power domain %s %s failed\n", domain->name, op);
+ return -ETIMEDOUT;
+ }
+ timeout--;
+ cpu_relax();
+ usleep_range(80, 100);
+ }
+ return 0;
+}
+
+static int exynos_pd_power_on(struct generic_pm_domain *domain)
+{
+ return exynos_pd_power(domain, true);
+}
+
+static int exynos_pd_power_off(struct generic_pm_domain *domain)
+{
+ return exynos_pd_power(domain, false);
+}
+
+#define EXYNOS_GPD(PD, BASE, NAME) \
+static struct exynos_pm_domain PD = { \
+ .base = (void __iomem *)BASE, \
+ .name = NAME, \
+ .pd = { \
+ .power_off = exynos_pd_power_off, \
+ .power_on = exynos_pd_power_on, \
+ }, \
+}
+
+#ifdef CONFIG_OF
+static __init int exynos_pm_dt_parse_domains(void)
+{
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
+ struct exynos_pm_domain *pd;
+
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd) {
+ pr_err("%s: failed to allocate memory for domain\n",
+ __func__);
+ return -ENOMEM;
+ }
+
+ if (of_get_property(np, "samsung,exynos4210-pd-off", NULL))
+ pd->is_off = true;
+ pd->name = np->name;
+ pd->base = of_iomap(np, 0);
+ pd->pd.power_off = exynos_pd_power_off;
+ pd->pd.power_on = exynos_pd_power_on;
+ pd->pd.of_node = np;
+ pm_genpd_init(&pd->pd, NULL, false);
+ }
+ return 0;
+}
+#else
+static __init int exynos_pm_dt_parse_domains(void)
+{
+ return 0;
+}
+#endif /* CONFIG_OF */
+
+static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
+ struct exynos_pm_domain *pd)
+{
+ if (pdev->dev.bus) {
+ if (pm_genpd_add_device(&pd->pd, &pdev->dev))
+ pr_info("%s: error in adding %s device to %s power"
+ "domain\n", __func__, dev_name(&pdev->dev),
+ pd->name);
+ }
+}
+
+EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
+EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
+EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
+EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
+EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
+EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
+EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
+
+static struct exynos_pm_domain *exynos4_pm_domains[] = {
+ &exynos4_pd_mfc,
+ &exynos4_pd_g3d,
+ &exynos4_pd_lcd0,
+ &exynos4_pd_lcd1,
+ &exynos4_pd_tv,
+ &exynos4_pd_cam,
+ &exynos4_pd_gps,
+};
+
+static __init int exynos4_pm_init_power_domain(void)
+{
+ int idx;
+
+ if (of_have_populated_dt())
+ return exynos_pm_dt_parse_domains();
+
+ for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++)
+ pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL,
+ exynos4_pm_domains[idx]->is_off);
+
+#ifdef CONFIG_S5P_DEV_FIMD0
+ exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
+#endif
+#ifdef CONFIG_S5P_DEV_TV
+ exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
+ exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
+#endif
+#ifdef CONFIG_S5P_DEV_MFC
+ exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
+#endif
+#ifdef CONFIG_S5P_DEV_FIMC0
+ exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_FIMC1
+ exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_FIMC2
+ exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_FIMC3
+ exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_CSIS0
+ exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_CSIS1
+ exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
+#endif
+#ifdef CONFIG_S5P_DEV_G2D
+ exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
+#endif
+#ifdef CONFIG_S5P_DEV_JPEG
+ exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
+#endif
+ return 0;
+}
+arch_initcall(exynos4_pm_init_power_domain);
+
+static __init int exynos_pm_late_initcall(void)
+{
+ pm_genpd_poweroff_unused();
+ return 0;
+}
+late_initcall(exynos_pm_late_initcall);
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd17c38..b90d94c17f7 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
/*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
#include <linux/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
+ if (soc_is_exynos5250())
+ /* will be implemented with gpio function */
+ return;
+
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}