summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-davinci/include
diff options
context:
space:
mode:
authorAnton Arapov <anton@redhat.com>2012-04-16 10:05:28 +0200
committerAnton Arapov <anton@redhat.com>2012-04-16 10:05:28 +0200
commitb4b6116a13633898cf868f2f103c96a90c4c20f8 (patch)
tree93d1b7e2cfcdf473d8d4ff3ad141fa864f8491f6 /arch/arm/mach-davinci/include
parentedd4be777c953e5faafc80d091d3084b4343f5d3 (diff)
downloadkernel-uprobes-b4b6116a13633898cf868f2f103c96a90c4c20f8.tar.gz
kernel-uprobes-b4b6116a13633898cf868f2f103c96a90c4c20f8.tar.xz
kernel-uprobes-b4b6116a13633898cf868f2f103c96a90c4c20f8.zip
fedora kernel: d9aad82f3319f3cfd1aebc01234254ef0c37ad84v3.3.2-1
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/arm/mach-davinci/include')
-rw-r--r--arch/arm/mach-davinci/include/mach/aemif.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/asp.h137
-rw-r--r--arch/arm/mach-davinci/include/mach/cdce949.h19
-rw-r--r--arch/arm/mach-davinci/include/mach/clock.h21
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h92
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h56
-rw-r--r--arch/arm/mach-davinci/include/mach/cpufreq.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/cpuidle.h18
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h94
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h133
-rw-r--r--arch/arm/mach-davinci/include/mach/ddr2.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S85
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h32
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h52
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h47
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h41
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h262
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S48
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio-davinci.h91
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h88
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h41
-rw-r--r--arch/arm/mach-davinci/include/mach/i2c.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h24
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h506
-rw-r--r--arch/arm/mach-davinci/include/mach/keyscan.h42
-rw-r--r--arch/arm/mach-davinci/include/mach/mmc.h39
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h1217
-rw-r--r--arch/arm/mach-davinci/include/mach/nand.h90
-rw-r--r--arch/arm/mach-davinci/include/mach/pm.h54
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h260
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h58
-rw-r--r--arch/arm/mach-davinci/include/mach/spi.h89
-rw-r--r--arch/arm/mach-davinci/include/mach/sram.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h21
-rw-r--r--arch/arm/mach-davinci/include/mach/time.h35
-rw-r--r--arch/arm/mach-davinci/include/mach/timex.h22
-rw-r--r--arch/arm/mach-davinci/include/mach/tnetv107x.h61
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h106
-rw-r--r--arch/arm/mach-davinci/include/mach/usb.h59
39 files changed, 4159 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h
new file mode 100644
index 00000000000..05b29344309
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/aemif.h
@@ -0,0 +1,36 @@
+/*
+ * TI DaVinci AEMIF support
+ *
+ * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_AEMIF_H
+#define _MACH_DAVINCI_AEMIF_H
+
+#define NRCSR_OFFSET 0x00
+#define AWCCR_OFFSET 0x04
+#define A1CR_OFFSET 0x10
+
+#define ACR_ASIZE_MASK 0x3
+#define ACR_EW_MASK BIT(30)
+#define ACR_SS_MASK BIT(31)
+
+/* All timings in nanoseconds */
+struct davinci_aemif_timing {
+ u8 wsetup;
+ u8 wstrobe;
+ u8 whold;
+
+ u8 rsetup;
+ u8 rstrobe;
+ u8 rhold;
+
+ u8 ta;
+};
+
+int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+ void __iomem *base, unsigned cs);
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
new file mode 100644
index 00000000000..9aa240909a2
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -0,0 +1,137 @@
+/*
+ * <mach/asp.h> - DaVinci Audio Serial Port support
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE 0x01E02000
+#define DAVINCI_ASP1_BASE 0x01E04000
+
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE 0x01D02000
+
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
+
+/* Bases of da850/da830 McASP0 register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX 2
+#define DAVINCI_DMA_ASP0_RX 3
+#define DAVINCI_DMA_ASP1_TX 8
+#define DAVINCI_DMA_ASP1_RX 9
+
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
+
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
+
+struct snd_platform_data {
+ u32 tx_dma_offset;
+ u32 rx_dma_offset;
+ enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
+ enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
+ unsigned int codec_fmt;
+ /*
+ * Allowing this is more efficient and eliminates left and right swaps
+ * caused by underruns, but will swap the left and right channels
+ * when compared to previous behavior.
+ */
+ unsigned enable_channel_combine:1;
+ unsigned sram_size_playback;
+ unsigned sram_size_capture;
+
+ /*
+ * If McBSP peripheral gets the clock from an external pin,
+ * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+ * and MCBSP_CLKS.
+ * Depending on different hardware connections it is possible
+ * to use this setting to change the behaviour of McBSP
+ * driver. The dm365_clk_input_pin enum is available for dm365
+ */
+ int clk_input_pin;
+
+ /*
+ * This flag works when both clock and FS are outputs for the cpu
+ * and makes clock more accurate (FS is not symmetrical and the
+ * clock is very fast.
+ * The clock becoming faster is named
+ * i2s continuous serial clock (I2S_SCK) and it is an externally
+ * visible bit clock.
+ *
+ * first line : WordSelect
+ * second line : ContinuousSerialClock
+ * third line: SerialData
+ *
+ * SYMMETRICAL APPROACH:
+ * _______________________ LEFT
+ * _| RIGHT |______________________|
+ * _ _ _ _ _ _ _ _
+ * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+ * _ _ _ _ _ _ _ _
+ * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+ * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
+ *
+ * ACCURATE CLOCK APPROACH:
+ * ______________ LEFT
+ * _| RIGHT |_______________________________|
+ * _ _ _ _ _ _ _ _ _
+ * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+ * _ _ _ _ dummy cycles
+ * _/ \_ ... _/ \_/ \_ ... _/ \__________________
+ * \_/ \_/ \_/ \_/
+ *
+ */
+ bool i2s_accurate_sck;
+
+ /* McASP specific fields */
+ int tdm_slots;
+ u8 op_mode;
+ u8 num_serializer;
+ u8 *serial_dir;
+ u8 version;
+ u8 txnumevt;
+ u8 rxnumevt;
+};
+
+enum {
+ MCASP_VERSION_1 = 0, /* DM646x */
+ MCASP_VERSION_2, /* DA8xx/OMAPL1x */
+};
+
+enum dm365_clk_input_pin {
+ MCBSP_CLKR = 0, /* DM365 */
+ MCBSP_CLKS,
+};
+
+#define INACTIVE_MODE 0
+#define TX_MODE 1
+#define RX_MODE 2
+
+#define DAVINCI_MCASP_IIS_MODE 0
+#define DAVINCI_MCASP_DIT_MODE 1
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/include/mach/cdce949.h b/arch/arm/mach-davinci/include/mach/cdce949.h
new file mode 100644
index 00000000000..c73331fae34
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cdce949.h
@@ -0,0 +1,19 @@
+/*
+ * TI CDCE949 off-chip clock synthesizer support
+ *
+ * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_CDCE949_H
+#define _MACH_DAVINCI_CDCE949_H
+
+#include <linux/clk.h>
+
+#include <mach/clock.h>
+
+int cdce_set_rate(struct clk *clk, unsigned long rate);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
new file mode 100644
index 00000000000..a3b04021987
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-davinci/include/mach/clock.h
+ *
+ * Clock control driver for DaVinci - header file
+ *
+ * Authors: Vladimir Barinov <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
+#define __ASM_ARCH_DAVINCI_CLOCK_H
+
+struct clk;
+
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
new file mode 100644
index 00000000000..5cd39a4e0c9
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -0,0 +1,92 @@
+/*
+ * Header for code common to all DaVinci machines.
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
+#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+struct sys_timer;
+
+extern struct sys_timer davinci_timer;
+
+extern void davinci_irq_init(void);
+extern void __iomem *davinci_intc_base;
+extern int davinci_intc_type;
+
+struct davinci_timer_instance {
+ u32 base;
+ u32 bottom_irq;
+ u32 top_irq;
+ unsigned long cmp_off;
+ unsigned int cmp_irq;
+};
+
+struct davinci_timer_info {
+ struct davinci_timer_instance *timers;
+ unsigned int clockevent_id;
+ unsigned int clocksource_id;
+};
+
+struct davinci_gpio_controller;
+
+/*
+ * SoC info passed into common davinci modules.
+ *
+ * Base addresses in this structure should be physical and not virtual.
+ * Modules that take such base addresses, should internally ioremap() them to
+ * use.
+ */
+struct davinci_soc_info {
+ struct map_desc *io_desc;
+ unsigned long io_desc_num;
+ u32 cpu_id;
+ u32 jtag_id;
+ u32 jtag_id_reg;
+ struct davinci_id *ids;
+ unsigned long ids_num;
+ struct clk_lookup *cpu_clks;
+ u32 *psc_bases;
+ unsigned long psc_bases_num;
+ u32 pinmux_base;
+ const struct mux_config *pinmux_pins;
+ unsigned long pinmux_pins_num;
+ u32 intc_base;
+ int intc_type;
+ u8 *intc_irq_prios;
+ unsigned long intc_irq_num;
+ u32 *intc_host_map;
+ struct davinci_timer_info *timer_info;
+ int gpio_type;
+ u32 gpio_base;
+ unsigned gpio_num;
+ unsigned gpio_irq;
+ unsigned gpio_unbanked;
+ struct davinci_gpio_controller *gpio_ctlrs;
+ int gpio_ctlrs_num;
+ struct platform_device *serial_dev;
+ struct emac_platform_data *emac_pdata;
+ dma_addr_t sram_dma;
+ unsigned sram_len;
+};
+
+extern struct davinci_soc_info davinci_soc_info;
+
+extern void davinci_common_init(struct davinci_soc_info *soc_info);
+extern void davinci_init_ide(void);
+void davinci_restart(char mode, const char *cmd);
+
+/* standard place to map on-chip SRAMs; they *may* support DMA */
+#define SRAM_VIRT 0xfffe0000
+#define SRAM_SIZE SZ_128K
+
+#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
new file mode 100644
index 00000000000..4e8190eed67
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -0,0 +1,56 @@
+/*
+ * TI Common Platform Interrupt Controller (cp_intc) definitions
+ *
+ * Author: Steve Chen <schen@mvista.com>
+ * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef __ASM_HARDWARE_CP_INTC_H
+#define __ASM_HARDWARE_CP_INTC_H
+
+#define CP_INTC_REV 0x00
+#define CP_INTC_CTRL 0x04
+#define CP_INTC_HOST_CTRL 0x0C
+#define CP_INTC_GLOBAL_ENABLE 0x10
+#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
+#define CP_INTC_SYS_STAT_IDX_SET 0x20
+#define CP_INTC_SYS_STAT_IDX_CLR 0x24
+#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
+#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
+#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
+#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
+#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
+#define CP_INTC_PACING_PRESCALE 0x40
+#define CP_INTC_VECTOR_BASE 0x50
+#define CP_INTC_VECTOR_SIZE 0x54
+#define CP_INTC_VECTOR_NULL 0x58
+#define CP_INTC_PRIO_IDX 0x80
+#define CP_INTC_PRIO_VECTOR 0x84
+#define CP_INTC_SECURE_ENABLE 0x90
+#define CP_INTC_SECURE_PRIO_IDX 0x94
+#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
+#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
+#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
+#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
+#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
+#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
+#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
+#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
+#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
+#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
+#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
+#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
+#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
+#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
+#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
+#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
+#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
+#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
+#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
+
+void __init cp_intc_init(void);
+
+#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cpufreq.h b/arch/arm/mach-davinci/include/mach/cpufreq.h
new file mode 100644
index 00000000000..3c089cfb6cd
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpufreq.h
@@ -0,0 +1,26 @@
+/*
+ * TI DaVinci CPUFreq platform support.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _MACH_DAVINCI_CPUFREQ_H
+#define _MACH_DAVINCI_CPUFREQ_H
+
+#include <linux/cpufreq.h>
+
+struct davinci_cpufreq_config {
+ struct cpufreq_frequency_table *freq_table;
+ int (*set_voltage) (unsigned int index);
+ int (*init) (void);
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h
new file mode 100644
index 00000000000..74f088b0edf
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpuidle.h
@@ -0,0 +1,18 @@
+/*
+ * TI DaVinci cpuidle platform support
+ *
+ * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_CPUIDLE_H
+#define _MACH_DAVINCI_CPUIDLE_H
+
+struct davinci_cpuidle_config {
+ u32 ddr2_pdown;
+ void __iomem *ddr2_ctlr_base;
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
new file mode 100644
index 00000000000..957fb87e832
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -0,0 +1,94 @@
+/*
+ * DaVinci CPU type detection
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Defines the cpu_is_*() macros for runtime detection of DaVinci
+ * device type. In addition, if support for a given device is not
+ * compiled in to the kernel, the macros return 0 so that
+ * resulting code can be optimized out.
+ *
+ * 2009 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _ASM_ARCH_CPU_H
+#define _ASM_ARCH_CPU_H
+
+#include <mach/common.h>
+
+struct davinci_id {
+ u8 variant; /* JTAG ID bits 31:28 */
+ u16 part_no; /* JTAG ID bits 27:12 */
+ u16 manufacturer; /* JTAG ID bits 11:1 */
+ u32 cpu_id;
+ char *name;
+};
+
+/* Can use lower 16 bits of cpu id for a variant when required */
+#define DAVINCI_CPU_ID_DM6446 0x64460000
+#define DAVINCI_CPU_ID_DM6467 0x64670000
+#define DAVINCI_CPU_ID_DM355 0x03550000
+#define DAVINCI_CPU_ID_DM365 0x03650000
+#define DAVINCI_CPU_ID_DA830 0x08300000
+#define DAVINCI_CPU_ID_DA850 0x08500000
+#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
+
+#define IS_DAVINCI_CPU(type, id) \
+static inline int is_davinci_ ##type(void) \
+{ \
+ return (davinci_soc_info.cpu_id == (id)); \
+}
+
+IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
+IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
+IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
+IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
+IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
+IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
+IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
+
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
+#define cpu_is_davinci_dm644x() is_davinci_dm644x()
+#else
+#define cpu_is_davinci_dm644x() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
+#define cpu_is_davinci_dm646x() is_davinci_dm646x()
+#else
+#define cpu_is_davinci_dm646x() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DM355
+#define cpu_is_davinci_dm355() is_davinci_dm355()
+#else
+#define cpu_is_davinci_dm355() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DM365
+#define cpu_is_davinci_dm365() is_davinci_dm365()
+#else
+#define cpu_is_davinci_dm365() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DA830
+#define cpu_is_davinci_da830() is_davinci_da830()
+#else
+#define cpu_is_davinci_da830() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+#define cpu_is_davinci_da850() is_davinci_da850()
+#else
+#define cpu_is_davinci_da850() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
+#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
+#else
+#define cpu_is_davinci_tnetv107x() 0
+#endif
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
new file mode 100644
index 00000000000..ee3461d7ec1
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -0,0 +1,133 @@
+/*
+ * Chip specific defines for DA8XX/OMAP L1XX SoC
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
+#define __ASM_ARCH_DAVINCI_DA8XX_H
+
+#include <video/da8xx-fb.h>
+
+#include <linux/platform_device.h>
+#include <linux/davinci_emac.h>
+#include <linux/spi/spi.h>
+
+#include <mach/serial.h>
+#include <mach/edma.h>
+#include <mach/i2c.h>
+#include <mach/asp.h>
+#include <mach/mmc.h>
+#include <mach/usb.h>
+#include <mach/pm.h>
+#include <mach/spi.h>
+
+extern void __iomem *da8xx_syscfg0_base;
+extern void __iomem *da8xx_syscfg1_base;
+
+/*
+ * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
+ * (than the regular 300Mhz variant), the board code should set this up
+ * with the supported speed before calling da850_register_cpufreq().
+ */
+extern unsigned int da850_max_speed;
+
+/*
+ * The cp_intc interrupt controller for the da8xx isn't in the same
+ * chunk of physical memory space as the other registers (like it is
+ * on the davincis) so it needs to be mapped separately. It will be
+ * mapped early on when the I/O space is mapped and we'll put it just
+ * before the I/O space in the processor's virtual memory space.
+ */
+#define DA8XX_CP_INTC_BASE 0xfffee000
+#define DA8XX_CP_INTC_SIZE SZ_8K
+#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
+
+#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
+#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
+#define DA8XX_JTAG_ID_REG 0x18
+#define DA8XX_CFGCHIP0_REG 0x17c
+#define DA8XX_CFGCHIP2_REG 0x184
+#define DA8XX_CFGCHIP3_REG 0x188
+
+#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
+#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
+#define DA8XX_DEEPSLEEP_REG 0x8
+#define DA8XX_PWRDN_REG 0x18
+
+#define DA8XX_PSC0_BASE 0x01c10000
+#define DA8XX_PLL0_BASE 0x01c11000
+#define DA8XX_TIMER64P0_BASE 0x01c20000
+#define DA8XX_TIMER64P1_BASE 0x01c21000
+#define DA8XX_GPIO_BASE 0x01e26000
+#define DA8XX_PSC1_BASE 0x01e27000
+#define DA8XX_AEMIF_CS2_BASE 0x60000000
+#define DA8XX_AEMIF_CS3_BASE 0x62000000
+#define DA8XX_AEMIF_CTL_BASE 0x68000000
+#define DA8XX_ARM_RAM_BASE 0xffff0000
+
+void __init da830_init(void);
+void __init da850_init(void);
+
+int da830_register_edma(struct edma_rsv_info *rsv);
+int da850_register_edma(struct edma_rsv_info *rsv[2]);
+int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
+int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
+int da8xx_register_watchdog(void);
+int da8xx_register_usb20(unsigned mA, unsigned potpgt);
+int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
+int da8xx_register_emac(void);
+int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
+int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
+int da850_register_mmcsd1(struct davinci_mmc_config *config);
+void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
+int da8xx_register_rtc(void);
+int da850_register_cpufreq(char *async_clk);
+int da8xx_register_cpuidle(void);
+void __iomem * __init da8xx_get_mem_ctlr(void);
+int da850_register_pm(struct platform_device *pdev);
+int __init da850_register_sata(unsigned long refclkpn);
+void da8xx_restart(char mode, const char *cmd);
+
+extern struct platform_device da8xx_serial_device;
+extern struct emac_platform_data da8xx_emac_pdata;
+extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
+extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
+extern struct davinci_spi_platform_data da8xx_spi_pdata[];
+
+extern struct platform_device da8xx_wdt_device;
+
+extern const short da830_emif25_pins[];
+extern const short da830_spi0_pins[];
+extern const short da830_spi1_pins[];
+extern const short da830_mmc_sd_pins[];
+extern const short da830_uart0_pins[];
+extern const short da830_uart1_pins[];
+extern const short da830_uart2_pins[];
+extern const short da830_usb20_pins[];
+extern const short da830_usb11_pins[];
+extern const short da830_uhpi_pins[];
+extern const short da830_cpgmac_pins[];
+extern const short da830_emif3c_pins[];
+extern const short da830_mcasp0_pins[];
+extern const short da830_mcasp1_pins[];
+extern const short da830_mcasp2_pins[];
+extern const short da830_i2c0_pins[];
+extern const short da830_i2c1_pins[];
+extern const short da830_lcdcntl_pins[];
+extern const short da830_pwm_pins[];
+extern const short da830_ecap0_pins[];
+extern const short da830_ecap1_pins[];
+extern const short da830_ecap2_pins[];
+extern const short da830_eqep0_pins[];
+extern const short da830_eqep1_pins[];
+
+extern const short da850_i2c0_pins[];
+extern const short da850_i2c1_pins[];
+extern const short da850_lcdcntl_pins[];
+
+#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/ddr2.h b/arch/arm/mach-davinci/include/mach/ddr2.h
new file mode 100644
index 00000000000..c19e047d0e6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/ddr2.h
@@ -0,0 +1,4 @@
+#define DDR2_SDRCR_OFFSET 0xc
+#define DDR2_SRPD_BIT (1 << 23)
+#define DDR2_MCLKSTOPEN_BIT (1 << 30)
+#define DDR2_LPMODEN_BIT (1 << 31)
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
new file mode 100644
index 00000000000..cf94552d527
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -0,0 +1,85 @@
+/*
+ * Debugging macro for DaVinci
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/* Modifications
+ * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart
+ * macros, based on debug-8250.S file
+ * but using 32-bit accesses required for
+ * some davinci devices.
+ */
+
+#include <linux/serial_reg.h>
+
+#include <mach/serial.h>
+
+#define UART_SHIFT 2
+
+ .pushsection .data
+davinci_uart_phys: .word 0
+davinci_uart_virt: .word 0
+ .popsection
+
+ .macro addruart, rp, rv, tmp
+
+ /* Use davinci_uart_phys/virt if already configured */
+10: adr \rp, 99f @ get effective addr of 99f
+ ldr \rv, [\rp] @ get absolute addr of 99f
+ sub \rv, \rv, \rp @ offset between the two
+ ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
+ sub \tmp, \rp, \rv @ make it effective
+ ldr \rp, [\tmp, #0] @ davinci_uart_phys
+ ldr \rv, [\tmp, #4] @ davinci_uart_virt
+ cmp \rp, #0 @ is port configured?
+ cmpne \rv, #0
+ bne 100f @ already configured
+
+ /* Check the debug UART address set in uncompress.h */
+ and \rp, pc, #0xff000000
+ ldr \rv, =DAVINCI_UART_INFO_OFS
+ add \rp, \rp, \rv
+
+ /* Copy uart phys address from decompressor uart info */
+ ldr \rv, [\rp, #0]
+ str \rv, [\tmp, #0]
+
+ /* Copy uart virt address from decompressor uart info */
+ ldr \rv, [\rp, #4]
+ str \rv, [\tmp, #4]
+
+ b 10b
+
+ .align
+99: .word .
+ .word davinci_uart_phys
+ .ltorg
+
+100:
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_TX << UART_SHIFT]
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1002b
+ .endm
+
+ .macro waituart,rd,rx
+#ifdef FLOW_CONTROL
+1001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT]
+ tst \rd, #UART_MSR_CTS
+ beq 1001b
+#endif
+ .endm
+
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
new file mode 100644
index 00000000000..36dff4a0ce3
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -0,0 +1,32 @@
+/*
+ * Chip specific defines for DM355 SoC
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DM355_H
+#define __ASM_ARCH_DM355_H
+
+#include <mach/hardware.h>
+#include <mach/asp.h>
+#include <media/davinci/vpfe_capture.h>
+
+#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
+#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+
+#define ASP1_TX_EVT_EN 1
+#define ASP1_RX_EVT_EN 2
+
+struct spi_board_info;
+
+void __init dm355_init(void);
+void dm355_init_spi0(unsigned chipselect_mask,
+ struct spi_board_info *info, unsigned len);
+void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_set_vpfe_config(struct vpfe_config *cfg);
+
+#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
new file mode 100644
index 00000000000..2563bf4e93a
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DM365_H
+#define __ASM_ARCH_DM665_H
+
+#include <linux/platform_device.h>
+#include <linux/davinci_emac.h>
+#include <mach/hardware.h>
+#include <mach/asp.h>
+#include <mach/keyscan.h>
+#include <media/davinci/vpfe_capture.h>
+
+#define DM365_EMAC_BASE (0x01D07000)
+#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
+#define DM365_EMAC_CNTRL_OFFSET (0x0000)
+#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
+#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
+#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
+
+/* Base of key scan register bank */
+#define DM365_KEYSCAN_BASE (0x01C69400)
+
+#define DM365_RTC_BASE (0x01C69000)
+
+#define DAVINCI_DM365_VC_BASE (0x01D0C000)
+#define DAVINCI_DMA_VC_TX 2
+#define DAVINCI_DMA_VC_RX 3
+
+#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+
+void __init dm365_init(void);
+void __init dm365_init_asp(struct snd_platform_data *pdata);
+void __init dm365_init_vc(struct snd_platform_data *pdata);
+void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void __init dm365_init_rtc(void);
+void dm365_init_spi0(unsigned chipselect_mask,
+ struct spi_board_info *info, unsigned len);
+
+void dm365_set_vpfe_config(struct vpfe_config *cfg);
+#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 00000000000..5a1b26d4e68
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,47 @@
+/*
+ * This file contains the processor specific definitions
+ * of the TI DM644x.
+ *
+ * Copyright (C) 2008 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_DM644X_H
+#define __ASM_ARCH_DM644X_H
+
+#include <linux/davinci_emac.h>
+#include <mach/hardware.h>
+#include <mach/asp.h>
+#include <media/davinci/vpfe_capture.h>
+
+#define DM644X_EMAC_BASE (0x01C80000)
+#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
+#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
+#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
+#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
+#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
+
+#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
+#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
+#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
+
+void __init dm644x_init(void);
+void __init dm644x_init_asp(struct snd_platform_data *pdata);
+void dm644x_set_vpfe_config(struct vpfe_config *cfg);
+
+#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
new file mode 100644
index 00000000000..a8ee6c9f0bb
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -0,0 +1,41 @@
+/*
+ * Chip specific defines for DM646x SoC
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DM646X_H
+#define __ASM_ARCH_DM646X_H
+
+#include <mach/hardware.h>
+#include <mach/asp.h>
+#include <linux/i2c.h>
+#include <linux/videodev2.h>
+#include <linux/davinci_emac.h>
+#include <media/davinci/vpif_types.h>
+
+#define DM646X_EMAC_BASE (0x01C80000)
+#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
+#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
+#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
+#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
+#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
+
+#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
+#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+
+void __init dm646x_init(void);
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+
+void dm646x_video_init(void);
+
+void dm646x_setup_vpif(struct vpif_display_config *,
+ struct vpif_capture_config *);
+
+#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
new file mode 100644
index 00000000000..20c77f29bf0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -0,0 +1,262 @@
+/*
+ * TI DAVINCI dma definitions
+ *
+ * Copyright (C) 2006-2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ * Channel Triggers transfers, usually from a hardware event but
+ * also manually or by "chaining" from DMA completions.
+ * Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ * "set"), source and destination addresses, a link to a
+ * next PaRAM slot (if any), options for the transfer, and
+ * instructions for updating those addresses. There are
+ * more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers. An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers. When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining). The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * DaVinci hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface. (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+ unsigned int opt;
+ unsigned int src;
+ unsigned int a_b_cnt;
+ unsigned int dst;
+ unsigned int src_dst_bidx;
+ unsigned int link_bcntrld;
+ unsigned int src_dst_cidx;
+ unsigned int ccnt;
+};
+
+#define CCINT0_INTERRUPT 16
+#define CCERRINT_INTERRUPT 17
+#define TCERRINT0_INTERRUPT 18
+#define TCERRINT1_INTERRUPT 19
+
+/* fields in edmacc_param.opt */
+#define SAM BIT(0)
+#define DAM BIT(1)
+#define SYNCDIM BIT(2)
+#define STATIC BIT(3)
+#define EDMA_FWID (0x07 << 8)
+#define TCCMODE BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN BIT(20)
+#define ITCINTEN BIT(21)
+#define TCCHEN BIT(22)
+#define ITCCHEN BIT(23)
+
+#define TRWORD (0x7<<2)
+#define PAENTRY (0x1ff<<5)
+
+/* Drivers should avoid using these symbolic names for dm644x
+ * channels, and use platform_device IORESOURCE_DMA resources
+ * instead. (Other DaVinci chips have different peripherals
+ * and thus have different DMA channel mappings.)
+ */
+#define DAVINCI_DMA_MCBSP_TX 2
+#define DAVINCI_DMA_MCBSP_RX 3
+#define DAVINCI_DMA_VPSS_HIST 4
+#define DAVINCI_DMA_VPSS_H3A 5
+#define DAVINCI_DMA_VPSS_PRVU 6
+#define DAVINCI_DMA_VPSS_RSZ 7
+#define DAVINCI_DMA_IMCOP_IMXINT 8
+#define DAVINCI_DMA_IMCOP_VLCDINT 9
+#define DAVINCI_DMA_IMCO_PASQINT 10
+#define DAVINCI_DMA_IMCOP_DSQINT 11
+#define DAVINCI_DMA_SPI_SPIX 16
+#define DAVINCI_DMA_SPI_SPIR 17
+#define DAVINCI_DMA_UART0_URXEVT0 18
+#define DAVINCI_DMA_UART0_UTXEVT0 19
+#define DAVINCI_DMA_UART1_URXEVT1 20
+#define DAVINCI_DMA_UART1_UTXEVT1 21
+#define DAVINCI_DMA_UART2_URXEVT2 22
+#define DAVINCI_DMA_UART2_UTXEVT2 23
+#define DAVINCI_DMA_MEMSTK_MSEVT 24
+#define DAVINCI_DMA_MMCRXEVT 26
+#define DAVINCI_DMA_MMCTXEVT 27
+#define DAVINCI_DMA_I2C_ICREVT 28
+#define DAVINCI_DMA_I2C_ICXEVT 29
+#define DAVINCI_DMA_GPIO_GPINT0 32
+#define DAVINCI_DMA_GPIO_GPINT1 33
+#define DAVINCI_DMA_GPIO_GPINT2 34
+#define DAVINCI_DMA_GPIO_GPINT3 35
+#define DAVINCI_DMA_GPIO_GPINT4 36
+#define DAVINCI_DMA_GPIO_GPINT5 37
+#define DAVINCI_DMA_GPIO_GPINT6 38
+#define DAVINCI_DMA_GPIO_GPINT7 39
+#define DAVINCI_DMA_GPIO_GPBNKINT0 40
+#define DAVINCI_DMA_GPIO_GPBNKINT1 41
+#define DAVINCI_DMA_GPIO_GPBNKINT2 42
+#define DAVINCI_DMA_GPIO_GPBNKINT3 43
+#define DAVINCI_DMA_GPIO_GPBNKINT4 44
+#define DAVINCI_DMA_TIMER0_TINT0 48
+#define DAVINCI_DMA_TIMER1_TINT1 49
+#define DAVINCI_DMA_TIMER2_TINT2 50
+#define DAVINCI_DMA_TIMER3_TINT3 51
+#define DAVINCI_DMA_PWM0 52
+#define DAVINCI_DMA_PWM1 53
+#define DAVINCI_DMA_PWM2 54
+
+/* DA830 specific EDMA3 information */
+#define EDMA_DA830_NUM_DMACH 32
+#define EDMA_DA830_NUM_TCC 32
+#define EDMA_DA830_NUM_PARAMENTRY 128
+#define EDMA_DA830_NUM_EVQUE 2
+#define EDMA_DA830_NUM_TC 2
+#define EDMA_DA830_CHMAP_EXIST 0
+#define EDMA_DA830_NUM_REGIONS 4
+#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
+#define DA830_DMACH2EVENT_MAP1 0x00000000u
+#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC1_ERROR 3
+#define DMA_TC2_ERROR 4
+
+enum address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum dma_event_q {
+ EVENTQ_0 = 0,
+ EVENTQ_1 = 1,
+ EVENTQ_2 = 2,
+ EVENTQ_3 = 3,
+ EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i) ((i) >> 16)
+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
+
+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_CC 2
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(unsigned ctlr, int slot);
+void edma_free_slot(unsigned slot);
+
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+struct edma_rsv_info {
+
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+};
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+ /* how many dma resources of each type */
+ unsigned n_channel;
+ unsigned n_region;
+ unsigned n_slot;
+ unsigned n_tc;
+ unsigned n_cc;
+ enum dma_event_q default_queue;
+
+ /* Resource reservation for other cores */
+ struct edma_rsv_info *rsv;
+
+ const s8 (*queue_tc_mapping)[2];
+ const s8 (*queue_priority_mapping)[2];
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
new file mode 100644
index 00000000000..e14c0dc0e12
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -0,0 +1,48 @@
+/*
+ * Low-level IRQ helper macros for TI DaVinci-based platforms
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <mach/io.h>
+#include <mach/irqs.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =davinci_intc_base
+ ldr \base, [\base]
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
+ ldr \tmp, =davinci_intc_type
+ ldr \tmp, [\tmp]
+ cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
+ beq 1001f
+#endif
+#if defined(CONFIG_AINTC)
+ ldr \tmp, [\base, #0x14]
+ movs \tmp, \tmp, lsr #2
+ sub \irqnr, \tmp, #1
+ b 1002f
+#endif
+#if defined(CONFIG_CP_INTC)
+1001: ldr \irqnr, [\base, #0x80] /* get irq number */
+ and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
+ mov \tmp, \irqnr, lsr #3
+ and \tmp, \tmp, #0xfc
+ add \tmp, \tmp, #0x280 /* get the register offset */
+ ldr \irqstat, [\base, \tmp] /* get the intc status */
+ cmp \irqstat, #0x0
+#endif
+1002:
+ .endm
diff --git a/arch/arm/mach-davinci/include/mach/gpio-davinci.h b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
new file mode 100644
index 00000000000..1fdd1fd3544
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/gpio-davinci.h
@@ -0,0 +1,91 @@
+/*
+ * TI DaVinci GPIO Support
+ *
+ * Copyright (c) 2006 David Brownell
+ * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DAVINCI_DAVINCI_GPIO_H
+#define __DAVINCI_DAVINCI_GPIO_H
+
+#include <linux/io.h>
+#include <linux/spinlock.h>
+
+#include <asm-generic/gpio.h>
+
+#include <mach/irqs.h>
+#include <mach/common.h>
+
+#define DAVINCI_GPIO_BASE 0x01C67000
+
+enum davinci_gpio_type {
+ GPIO_TYPE_DAVINCI = 0,
+ GPIO_TYPE_TNETV107X,
+};
+
+/*
+ * basic gpio routines
+ *
+ * board-specific init should be done by arch/.../.../board-XXX.c (maybe
+ * initializing banks together) rather than boot loaders; kexec() won't
+ * go through boot loaders.
+ *
+ * the gpio clock will be turned on when gpios are used, and you may also
+ * need to pay attention to PINMUX registers to be sure those pins are
+ * used as gpios, not with other peripherals.
+ *
+ * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
+ * and maybe for later updates, code may write GPIO(N). These may be
+ * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
+ * may not support all the GPIOs in that range.
+ *
+ * GPIOs can also be on external chips, numbered after the ones built-in
+ * to the DaVinci chip. For now, they won't be usable as IRQ sources.
+ */
+#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
+
+struct davinci_gpio_controller {
+ struct gpio_chip chip;
+ int irq_base;
+ spinlock_t lock;
+ void __iomem *regs;
+ void __iomem *set_data;
+ void __iomem *clr_data;
+ void __iomem *in_data;
+};
+
+/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
+ * with constant parameters; or in outlined code they execute at runtime.
+ *
+ * You'd access the controller directly when reading or writing more than
+ * one gpio value at a time, and to support wired logic where the value
+ * being driven by the cpu need not match the value read back.
+ *
+ * These are NOT part of the cross-platform GPIO interface
+ */
+static inline struct davinci_gpio_controller *
+__gpio_to_controller(unsigned gpio)
+{
+ struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
+ int index = gpio / 32;
+
+ if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
+ return NULL;
+
+ return ctlrs + index;
+}
+
+static inline u32 __gpio_mask(unsigned gpio)
+{
+ return 1 << (gpio % 32);
+}
+
+#endif /* __DAVINCI_DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
new file mode 100644
index 00000000000..960e9de47e1
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -0,0 +1,88 @@
+/*
+ * TI DaVinci GPIO Support
+ *
+ * Copyright (c) 2006 David Brownell
+ * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DAVINCI_GPIO_H
+#define __DAVINCI_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#define __ARM_GPIOLIB_COMPLEX
+
+/* The inline versions use the static inlines in the driver header */
+#include "gpio-davinci.h"
+
+/*
+ * The get/set/clear functions will inline when called with constant
+ * parameters referencing built-in GPIOs, for low-overhead bitbanging.
+ *
+ * gpio_set_value() will inline only on traditional Davinci style controllers
+ * with distinct set/clear registers.
+ *
+ * Otherwise, calls with variable parameters or referencing external
+ * GPIOs (e.g. on GPIO expander chips) use outlined functions.
+ */
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
+ struct davinci_gpio_controller *ctlr;
+ u32 mask;
+
+ ctlr = __gpio_to_controller(gpio);
+
+ if (ctlr->set_data != ctlr->clr_data) {
+ mask = __gpio_mask(gpio);
+ if (value)
+ __raw_writel(mask, ctlr->set_data);
+ else
+ __raw_writel(mask, ctlr->clr_data);
+ return;
+ }
+ }
+
+ __gpio_set_value(gpio, value);
+}
+
+/* Returns zero or nonzero; works for gpios configured as inputs OR
+ * as outputs, at least for built-in GPIOs.
+ *
+ * NOTE: for built-in GPIOs, changes in reported values are synchronized
+ * to the GPIO clock. This is easily seen after calling gpio_set_value()
+ * and then immediately gpio_get_value(), where the gpio_get_value() will
+ * return the old value until the GPIO clock ticks and the new value gets
+ * latched.
+ */
+static inline int gpio_get_value(unsigned gpio)
+{
+ struct davinci_gpio_controller *ctlr;
+
+ if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
+ return __gpio_get_value(gpio);
+
+ ctlr = __gpio_to_controller(gpio);
+ return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+ if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
+ return 0;
+ else
+ return __gpio_cansleep(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ /* don't support the reverse mapping */
+ return -ENOSYS;
+}
+
+#endif /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
new file mode 100644
index 00000000000..414e0b93e74
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -0,0 +1,41 @@
+/*
+ * Hardware definitions common to all DaVinci family processors
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Before you add anything to ths file:
+ *
+ * This header is for defines common to ALL DaVinci family chips.
+ * Anything that is chip specific should go in <chipname>.h,
+ * and the chip/board init code should then explicitly include
+ * <chipname>.h
+ */
+#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
+
+/*
+ * I/O mapping
+ */
+#define IO_PHYS 0x01c00000UL
+#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
+#define IO_SIZE 0x00400000
+#define IO_VIRT (IO_PHYS + IO_OFFSET)
+#define io_v2p(va) ((va) - IO_OFFSET)
+#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
+#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) x
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
new file mode 100644
index 00000000000..2312d197dfb
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
@@ -0,0 +1,26 @@
+/*
+ * DaVinci I2C controller platform_device info
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+*/
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+/* All frequencies are expressed in kHz */
+struct davinci_i2c_platform_data {
+ unsigned int bus_freq; /* standard bus frequency (kHz) */
+ unsigned int bus_delay; /* post-transaction delay (usec) */
+ unsigned int sda_pin; /* GPIO pin ID to use for SDA */
+ unsigned int scl_pin; /* GPIO pin ID to use for SCL */
+};
+
+/* for board setup code */
+void davinci_init_i2c(struct davinci_i2c_platform_data *);
+
+#endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
new file mode 100644
index 00000000000..b2267d1e1a7
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -0,0 +1,24 @@
+/*
+ * DaVinci IO address definitions
+ *
+ * Copied from include/asm/arm/arch-omap/io.h
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+#define __mem_isa(a) (a)
+
+#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
new file mode 100644
index 00000000000..ec76c7775c2
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -0,0 +1,506 @@
+/*
+ * DaVinci interrupt controller definitions
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/* Base address */
+#define DAVINCI_ARM_INTC_BASE 0x01C48000
+
+#define DAVINCI_INTC_TYPE_AINTC 0
+#define DAVINCI_INTC_TYPE_CP_INTC 1
+
+/* Interrupt lines */
+#define IRQ_VDINT0 0
+#define IRQ_VDINT1 1
+#define IRQ_VDINT2 2
+#define IRQ_HISTINT 3
+#define IRQ_H3AINT 4
+#define IRQ_PRVUINT 5
+#define IRQ_RSZINT 6
+#define IRQ_VFOCINT 7
+#define IRQ_VENCINT 8
+#define IRQ_ASQINT 9
+#define IRQ_IMXINT 10
+#define IRQ_VLCDINT 11
+#define IRQ_USBINT 12
+#define IRQ_EMACINT 13
+
+#define IRQ_CCINT0 16
+#define IRQ_CCERRINT 17
+#define IRQ_TCERRINT0 18
+#define IRQ_TCERRINT 19
+#define IRQ_PSCIN 20
+
+#define IRQ_IDE 22
+#define IRQ_HPIINT 23
+#define IRQ_MBXINT 24
+#define IRQ_MBRINT 25
+#define IRQ_MMCINT 26
+#define IRQ_SDIOINT 27
+#define IRQ_MSINT 28
+#define IRQ_DDRINT 29
+#define IRQ_AEMIFINT 30
+#define IRQ_VLQINT 31
+#define IRQ_TINT0_TINT12 32
+#define IRQ_TINT0_TINT34 33
+#define IRQ_TINT1_TINT12 34
+#define IRQ_TINT1_TINT34 35
+#define IRQ_PWMINT0 36
+#define IRQ_PWMINT1 37
+#define IRQ_PWMINT2 38
+#define IRQ_I2C 39
+#define IRQ_UARTINT0 40
+#define IRQ_UARTINT1 41
+#define IRQ_UARTINT2 42
+#define IRQ_SPINT0 43
+#define IRQ_SPINT1 44
+
+#define IRQ_DSP2ARM0 46
+#define IRQ_DSP2ARM1 47
+#define IRQ_GPIO0 48
+#define IRQ_GPIO1 49
+#define IRQ_GPIO2 50
+#define IRQ_GPIO3 51
+#define IRQ_GPIO4 52
+#define IRQ_GPIO5 53
+#define IRQ_GPIO6 54
+#define IRQ_GPIO7 55
+#define IRQ_GPIOBNK0 56
+#define IRQ_GPIOBNK1 57
+#define IRQ_GPIOBNK2 58
+#define IRQ_GPIOBNK3 59
+#define IRQ_GPIOBNK4 60
+#define IRQ_COMMTX 61
+#define IRQ_COMMRX 62
+#define IRQ_EMUINT 63
+
+#define DAVINCI_N_AINTC_IRQ 64
+
+#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
+
+/* DaVinci DM6467-specific Interrupts */
+#define IRQ_DM646X_VP_VERTINT0 0
+#define IRQ_DM646X_VP_VERTINT1 1
+#define IRQ_DM646X_VP_VERTINT2 2
+#define IRQ_DM646X_VP_VERTINT3 3
+#define IRQ_DM646X_VP_ERRINT 4
+#define IRQ_DM646X_RESERVED_1 5
+#define IRQ_DM646X_RESERVED_2 6
+#define IRQ_DM646X_WDINT 7
+#define IRQ_DM646X_CRGENINT0 8
+#define IRQ_DM646X_CRGENINT1 9
+#define IRQ_DM646X_TSIFINT0 10
+#define IRQ_DM646X_TSIFINT1 11
+#define IRQ_DM646X_VDCEINT 12
+#define IRQ_DM646X_USBINT 13
+#define IRQ_DM646X_USBDMAINT 14
+#define IRQ_DM646X_PCIINT 15
+#define IRQ_DM646X_TCERRINT2 20
+#define IRQ_DM646X_TCERRINT3 21
+#define IRQ_DM646X_IDE 22
+#define IRQ_DM646X_HPIINT 23
+#define IRQ_DM646X_EMACRXTHINT 24
+#define IRQ_DM646X_EMACRXINT 25
+#define IRQ_DM646X_EMACTXINT 26
+#define IRQ_DM646X_EMACMISCINT 27
+#define IRQ_DM646X_MCASP0TXINT 28
+#define IRQ_DM646X_MCASP0RXINT 29
+#define IRQ_DM646X_RESERVED_3 31
+#define IRQ_DM646X_MCASP1TXINT 32
+#define IRQ_DM646X_VLQINT 38
+#define IRQ_DM646X_UARTINT2 42
+#define IRQ_DM646X_SPINT0 43
+#define IRQ_DM646X_SPINT1 44
+#define IRQ_DM646X_DSP2ARMINT 45
+#define IRQ_DM646X_RESERVED_4 46
+#define IRQ_DM646X_PSCINT 47
+#define IRQ_DM646X_GPIO0 48
+#define IRQ_DM646X_GPIO1 49
+#define IRQ_DM646X_GPIO2 50
+#define IRQ_DM646X_GPIO3 51
+#define IRQ_DM646X_GPIO4 52
+#define IRQ_DM646X_GPIO5 53
+#define IRQ_DM646X_GPIO6 54
+#define IRQ_DM646X_GPIO7 55
+#define IRQ_DM646X_GPIOBNK0 56
+#define IRQ_DM646X_GPIOBNK1 57
+#define IRQ_DM646X_GPIOBNK2 58
+#define IRQ_DM646X_DDRINT 59
+#define IRQ_DM646X_AEMIFINT 60
+
+/* DaVinci DM355-specific Interrupts */
+#define IRQ_DM355_CCDC_VDINT0 0
+#define IRQ_DM355_CCDC_VDINT1 1
+#define IRQ_DM355_CCDC_VDINT2 2
+#define IRQ_DM355_IPIPE_HST 3
+#define IRQ_DM355_H3AINT 4
+#define IRQ_DM355_IPIPE_SDR 5
+#define IRQ_DM355_IPIPEIFINT 6
+#define IRQ_DM355_OSDINT 7
+#define IRQ_DM355_VENCINT 8
+#define IRQ_DM355_IMCOPINT 11
+#define IRQ_DM355_RTOINT 13
+#define IRQ_DM355_TINT4 13
+#define IRQ_DM355_TINT2_TINT12 13
+#define IRQ_DM355_UARTINT2 14
+#define IRQ_DM355_TINT5 14
+#define IRQ_DM355_TINT2_TINT34 14
+#define IRQ_DM355_TINT6 15
+#define IRQ_DM355_TINT3_TINT12 15
+#define IRQ_DM355_SPINT1_0 17
+#define IRQ_DM355_SPINT1_1 18
+#define IRQ_DM355_SPINT2_0 19
+#define IRQ_DM355_SPINT2_1 21
+#define IRQ_DM355_TINT7 22
+#define IRQ_DM355_TINT3_TINT34 22
+#define IRQ_DM355_SDIOINT0 23
+#define IRQ_DM355_MMCINT0 26
+#define IRQ_DM355_MSINT 26
+#define IRQ_DM355_MMCINT1 27
+#define IRQ_DM355_PWMINT3 28
+#define IRQ_DM355_SDIOINT1 31
+#define IRQ_DM355_SPINT0_0 42
+#define IRQ_DM355_SPINT0_1 43
+#define IRQ_DM355_GPIO0 44
+#define IRQ_DM355_GPIO1 45
+#define IRQ_DM355_GPIO2 46
+#define IRQ_DM355_GPIO3 47
+#define IRQ_DM355_GPIO4 48
+#define IRQ_DM355_GPIO5 49
+#define IRQ_DM355_GPIO6 50
+#define IRQ_DM355_GPIO7 51
+#define IRQ_DM355_GPIO8 52
+#define IRQ_DM355_GPIO9 53
+#define IRQ_DM355_GPIOBNK0 54
+#define IRQ_DM355_GPIOBNK1 55
+#define IRQ_DM355_GPIOBNK2 56
+#define IRQ_DM355_GPIOBNK3 57
+#define IRQ_DM355_GPIOBNK4 58
+#define IRQ_DM355_GPIOBNK5 59
+#define IRQ_DM355_GPIOBNK6 60
+
+/* DaVinci DM365-specific Interrupts */
+#define IRQ_DM365_INSFINT 7
+#define IRQ_DM365_IMXINT1 8
+#define IRQ_DM365_IMXINT0 10
+#define IRQ_DM365_KLD_ARMINT 10
+#define IRQ_DM365_IMCOPINT 11
+#define IRQ_DM365_RTOINT 13
+#define IRQ_DM365_TINT5 14
+#define IRQ_DM365_TINT6 15
+#define IRQ_DM365_SPINT2_1 21
+#define IRQ_DM365_TINT7 22
+#define IRQ_DM365_SDIOINT0 23
+#define IRQ_DM365_MMCINT1 27
+#define IRQ_DM365_PWMINT3 28
+#define IRQ_DM365_RTCINT 29
+#define IRQ_DM365_SDIOINT1 31
+#define IRQ_DM365_SPIINT0_0 42
+#define IRQ_DM365_SPIINT3_0 43
+#define IRQ_DM365_GPIO0 44
+#define IRQ_DM365_GPIO1 45
+#define IRQ_DM365_GPIO2 46
+#define IRQ_DM365_GPIO3 47
+#define IRQ_DM365_GPIO4 48
+#define IRQ_DM365_GPIO5 49
+#define IRQ_DM365_GPIO6 50
+#define IRQ_DM365_GPIO7 51
+#define IRQ_DM365_EMAC_RXTHRESH 52
+#define IRQ_DM365_EMAC_RXPULSE 53
+#define IRQ_DM365_EMAC_TXPULSE 54
+#define IRQ_DM365_EMAC_MISCPULSE 55
+#define IRQ_DM365_GPIO12 56
+#define IRQ_DM365_GPIO13 57
+#define IRQ_DM365_GPIO14 58
+#define IRQ_DM365_GPIO15 59
+#define IRQ_DM365_ADCINT 59
+#define IRQ_DM365_KEYINT 60
+#define IRQ_DM365_TCERRINT2 61
+#define IRQ_DM365_TCERRINT3 62
+#define IRQ_DM365_EMUINT 63
+
+/* DA8XX interrupts */
+#define IRQ_DA8XX_COMMTX 0
+#define IRQ_DA8XX_COMMRX 1
+#define IRQ_DA8XX_NINT 2
+#define IRQ_DA8XX_EVTOUT0 3
+#define IRQ_DA8XX_EVTOUT1 4
+#define IRQ_DA8XX_EVTOUT2 5
+#define IRQ_DA8XX_EVTOUT3 6
+#define IRQ_DA8XX_EVTOUT4 7
+#define IRQ_DA8XX_EVTOUT5 8
+#define IRQ_DA8XX_EVTOUT6 9
+#define IRQ_DA8XX_EVTOUT7 10
+#define IRQ_DA8XX_CCINT0 11
+#define IRQ_DA8XX_CCERRINT 12
+#define IRQ_DA8XX_TCERRINT0 13
+#define IRQ_DA8XX_AEMIFINT 14
+#define IRQ_DA8XX_I2CINT0 15
+#define IRQ_DA8XX_MMCSDINT0 16
+#define IRQ_DA8XX_MMCSDINT1 17
+#define IRQ_DA8XX_ALLINT0 18
+#define IRQ_DA8XX_RTC 19
+#define IRQ_DA8XX_SPINT0 20
+#define IRQ_DA8XX_TINT12_0 21
+#define IRQ_DA8XX_TINT34_0 22
+#define IRQ_DA8XX_TINT12_1 23
+#define IRQ_DA8XX_TINT34_1 24
+#define IRQ_DA8XX_UARTINT0 25
+#define IRQ_DA8XX_KEYMGRINT 26
+#define IRQ_DA8XX_SECINT 26
+#define IRQ_DA8XX_SECKEYERR 26
+#define IRQ_DA8XX_CHIPINT0 28
+#define IRQ_DA8XX_CHIPINT1 29
+#define IRQ_DA8XX_CHIPINT2 30
+#define IRQ_DA8XX_CHIPINT3 31
+#define IRQ_DA8XX_TCERRINT1 32
+#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33
+#define IRQ_DA8XX_C0_RX_PULSE 34
+#define IRQ_DA8XX_C0_TX_PULSE 35
+#define IRQ_DA8XX_C0_MISC_PULSE 36
+#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37
+#define IRQ_DA8XX_C1_RX_PULSE 38
+#define IRQ_DA8XX_C1_TX_PULSE 39
+#define IRQ_DA8XX_C1_MISC_PULSE 40
+#define IRQ_DA8XX_MEMERR 41
+#define IRQ_DA8XX_GPIO0 42
+#define IRQ_DA8XX_GPIO1 43
+#define IRQ_DA8XX_GPIO2 44
+#define IRQ_DA8XX_GPIO3 45
+#define IRQ_DA8XX_GPIO4 46
+#define IRQ_DA8XX_GPIO5 47
+#define IRQ_DA8XX_GPIO6 48
+#define IRQ_DA8XX_GPIO7 49
+#define IRQ_DA8XX_GPIO8 50
+#define IRQ_DA8XX_I2CINT1 51
+#define IRQ_DA8XX_LCDINT 52
+#define IRQ_DA8XX_UARTINT1 53
+#define IRQ_DA8XX_MCASPINT 54
+#define IRQ_DA8XX_ALLINT1 55
+#define IRQ_DA8XX_SPINT1 56
+#define IRQ_DA8XX_UHPI_INT1 57
+#define IRQ_DA8XX_USB_INT 58
+#define IRQ_DA8XX_IRQN 59
+#define IRQ_DA8XX_RWAKEUP 60
+#define IRQ_DA8XX_UARTINT2 61
+#define IRQ_DA8XX_DFTSSINT 62
+#define IRQ_DA8XX_EHRPWM0 63
+#define IRQ_DA8XX_EHRPWM0TZ 64
+#define IRQ_DA8XX_EHRPWM1 65
+#define IRQ_DA8XX_EHRPWM1TZ 66
+#define IRQ_DA8XX_ECAP0 69
+#define IRQ_DA8XX_ECAP1 70
+#define IRQ_DA8XX_ECAP2 71
+#define IRQ_DA8XX_ARMCLKSTOPREQ 90
+
+/* DA830 specific interrupts */
+#define IRQ_DA830_MPUERR 27
+#define IRQ_DA830_IOPUERR 27
+#define IRQ_DA830_BOOTCFGERR 27
+#define IRQ_DA830_EHRPWM2 67
+#define IRQ_DA830_EHRPWM2TZ 68
+#define IRQ_DA830_EQEP0 72
+#define IRQ_DA830_EQEP1 73
+#define IRQ_DA830_T12CMPINT0_0 74
+#define IRQ_DA830_T12CMPINT1_0 75
+#define IRQ_DA830_T12CMPINT2_0 76
+#define IRQ_DA830_T12CMPINT3_0 77
+#define IRQ_DA830_T12CMPINT4_0 78
+#define IRQ_DA830_T12CMPINT5_0 79
+#define IRQ_DA830_T12CMPINT6_0 80
+#define IRQ_DA830_T12CMPINT7_0 81
+#define IRQ_DA830_T12CMPINT0_1 82
+#define IRQ_DA830_T12CMPINT1_1 83
+#define IRQ_DA830_T12CMPINT2_1 84
+#define IRQ_DA830_T12CMPINT3_1 85
+#define IRQ_DA830_T12CMPINT4_1 86
+#define IRQ_DA830_T12CMPINT5_1 87
+#define IRQ_DA830_T12CMPINT6_1 88
+#define IRQ_DA830_T12CMPINT7_1 89
+
+#define DA830_N_CP_INTC_IRQ 96
+
+/* DA850 speicific interrupts */
+#define IRQ_DA850_MPUADDRERR0 27
+#define IRQ_DA850_MPUPROTERR0 27
+#define IRQ_DA850_IOPUADDRERR0 27
+#define IRQ_DA850_IOPUPROTERR0 27
+#define IRQ_DA850_IOPUADDRERR1 27
+#define IRQ_DA850_IOPUPROTERR1 27
+#define IRQ_DA850_IOPUADDRERR2 27
+#define IRQ_DA850_IOPUPROTERR2 27
+#define IRQ_DA850_BOOTCFG_ADDR_ERR 27
+#define IRQ_DA850_BOOTCFG_PROT_ERR 27
+#define IRQ_DA850_MPUADDRERR1 27
+#define IRQ_DA850_MPUPROTERR1 27
+#define IRQ_DA850_IOPUADDRERR3 27
+#define IRQ_DA850_IOPUPROTERR3 27
+#define IRQ_DA850_IOPUADDRERR4 27
+#define IRQ_DA850_IOPUPROTERR4 27
+#define IRQ_DA850_IOPUADDRERR5 27
+#define IRQ_DA850_IOPUPROTERR5 27
+#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27
+#define IRQ_DA850_SATAINT 67
+#define IRQ_DA850_TINT12_2 68
+#define IRQ_DA850_TINT34_2 68
+#define IRQ_DA850_TINTALL_2 68
+#define IRQ_DA850_MMCSDINT0_1 72
+#define IRQ_DA850_MMCSDINT1_1 73
+#define IRQ_DA850_T12CMPINT0_2 74
+#define IRQ_DA850_T12CMPINT1_2 75
+#define IRQ_DA850_T12CMPINT2_2 76
+#define IRQ_DA850_T12CMPINT3_2 77
+#define IRQ_DA850_T12CMPINT4_2 78
+#define IRQ_DA850_T12CMPINT5_2 79
+#define IRQ_DA850_T12CMPINT6_2 80
+#define IRQ_DA850_T12CMPINT7_2 81
+#define IRQ_DA850_T12CMPINT0_3 82
+#define IRQ_DA850_T12CMPINT1_3 83
+#define IRQ_DA850_T12CMPINT2_3 84
+#define IRQ_DA850_T12CMPINT3_3 85
+#define IRQ_DA850_T12CMPINT4_3 86
+#define IRQ_DA850_T12CMPINT5_3 87
+#define IRQ_DA850_T12CMPINT6_3 88
+#define IRQ_DA850_T12CMPINT7_3 89
+#define IRQ_DA850_RPIINT 91
+#define IRQ_DA850_VPIFINT 92
+#define IRQ_DA850_CCINT1 93
+#define IRQ_DA850_CCERRINT1 94
+#define IRQ_DA850_TCERRINT2 95
+#define IRQ_DA850_TINT12_3 96
+#define IRQ_DA850_TINT34_3 96
+#define IRQ_DA850_TINTALL_3 96
+#define IRQ_DA850_MCBSP0RINT 97
+#define IRQ_DA850_MCBSP0XINT 98
+#define IRQ_DA850_MCBSP1RINT 99
+#define IRQ_DA850_MCBSP1XINT 100
+
+#define DA850_N_CP_INTC_IRQ 101
+
+
+/* TNETV107X specific interrupts */
+#define IRQ_TNETV107X_TDM1_TXDMA 0
+#define IRQ_TNETV107X_EXT_INT_0 1
+#define IRQ_TNETV107X_EXT_INT_1 2
+#define IRQ_TNETV107X_GPIO_INT12 3
+#define IRQ_TNETV107X_GPIO_INT13 4
+#define IRQ_TNETV107X_TIMER_0_TINT12 5
+#define IRQ_TNETV107X_TIMER_1_TINT12 6
+#define IRQ_TNETV107X_UART0 7
+#define IRQ_TNETV107X_TDM1_RXDMA 8
+#define IRQ_TNETV107X_MCDMA_INT0 9
+#define IRQ_TNETV107X_MCDMA_INT1 10
+#define IRQ_TNETV107X_TPCC 11
+#define IRQ_TNETV107X_TPCC_INT0 12
+#define IRQ_TNETV107X_TPCC_INT1 13
+#define IRQ_TNETV107X_TPCC_INT2 14
+#define IRQ_TNETV107X_TPCC_INT3 15
+#define IRQ_TNETV107X_TPTC0 16
+#define IRQ_TNETV107X_TPTC1 17
+#define IRQ_TNETV107X_TIMER_0_TINT34 18
+#define IRQ_TNETV107X_ETHSS 19
+#define IRQ_TNETV107X_TIMER_1_TINT34 20
+#define IRQ_TNETV107X_DSP2ARM_INT0 21
+#define IRQ_TNETV107X_DSP2ARM_INT1 22
+#define IRQ_TNETV107X_ARM_NPMUIRQ 23
+#define IRQ_TNETV107X_USB1 24
+#define IRQ_TNETV107X_VLYNQ 25
+#define IRQ_TNETV107X_UART0_DMATX 26
+#define IRQ_TNETV107X_UART0_DMARX 27
+#define IRQ_TNETV107X_TDM1_TXMCSP 28
+#define IRQ_TNETV107X_SSP 29
+#define IRQ_TNETV107X_MCDMA_INT2 30
+#define IRQ_TNETV107X_MCDMA_INT3 31
+#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
+#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
+#define IRQ_TNETV107X_USB0 34
+#define IRQ_TNETV107X_USB_CDMA 35
+#define IRQ_TNETV107X_LCD 36
+#define IRQ_TNETV107X_KEYPAD 37
+#define IRQ_TNETV107X_KEYPAD_FREE 38
+#define IRQ_TNETV107X_RNG 39
+#define IRQ_TNETV107X_PKA 40
+#define IRQ_TNETV107X_TDM0_TXDMA 41
+#define IRQ_TNETV107X_TDM0_RXDMA 42
+#define IRQ_TNETV107X_TDM0_TXMCSP 43
+#define IRQ_TNETV107X_TDM0_RXMCSP 44
+#define IRQ_TNETV107X_TDM1_RXMCSP 45
+#define IRQ_TNETV107X_SDIO1 46
+#define IRQ_TNETV107X_SDIO0 47
+#define IRQ_TNETV107X_TSC 48
+#define IRQ_TNETV107X_TS 49
+#define IRQ_TNETV107X_UART1 50
+#define IRQ_TNETV107X_MBX_LITE 51
+#define IRQ_TNETV107X_GPIO_INT00 52
+#define IRQ_TNETV107X_GPIO_INT01 53
+#define IRQ_TNETV107X_GPIO_INT02 54
+#define IRQ_TNETV107X_GPIO_INT03 55
+#define IRQ_TNETV107X_UART2 56
+#define IRQ_TNETV107X_UART2_DMATX 57
+#define IRQ_TNETV107X_UART2_DMARX 58
+#define IRQ_TNETV107X_IMCOP_IMX 59
+#define IRQ_TNETV107X_IMCOP_VLCD 60
+#define IRQ_TNETV107X_AES 61
+#define IRQ_TNETV107X_DES 62
+#define IRQ_TNETV107X_SHAMD5 63
+#define IRQ_TNETV107X_TPCC_ERR 68
+#define IRQ_TNETV107X_TPCC_PROT 69
+#define IRQ_TNETV107X_TPTC0_ERR 70
+#define IRQ_TNETV107X_TPTC1_ERR 71
+#define IRQ_TNETV107X_UART0_ERR 72
+#define IRQ_TNETV107X_UART1_ERR 73
+#define IRQ_TNETV107X_AEMIF_ERR 74
+#define IRQ_TNETV107X_DDR_ERR 75
+#define IRQ_TNETV107X_WDTARM_INT0 76
+#define IRQ_TNETV107X_MCDMA_ERR 77
+#define IRQ_TNETV107X_GPIO_ERR 78
+#define IRQ_TNETV107X_MPU_ADDR 79
+#define IRQ_TNETV107X_MPU_PROT 80
+#define IRQ_TNETV107X_IOPU_ADDR 81
+#define IRQ_TNETV107X_IOPU_PROT 82
+#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
+#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
+#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
+#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
+#define IRQ_TNETV107X_PLL_UNLOCK 87
+#define IRQ_TNETV107X_WDTDSP_INT0 88
+#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
+#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
+#define IRQ_TNETV107X_PBIST_CPU 91
+#define IRQ_TNETV107X_WDTARM 92
+#define IRQ_TNETV107X_PSC 93
+#define IRQ_TNETV107X_MMC0 94
+#define IRQ_TNETV107X_MMC1 95
+
+#define TNETV107X_N_CP_INTC_IRQ 96
+
+/* da850 currently has the most gpio pins (144) */
+#define DAVINCI_N_GPIO 144
+/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
+#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/arch/arm/mach-davinci/include/mach/keyscan.h
new file mode 100644
index 00000000000..7a560e05bda
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/keyscan.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2009 Texas Instruments, Inc
+ *
+ * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef DAVINCI_KEYSCAN_H
+#define DAVINCI_KEYSCAN_H
+
+#include <linux/io.h>
+
+enum davinci_matrix_types {
+ DAVINCI_KEYSCAN_MATRIX_4X4,
+ DAVINCI_KEYSCAN_MATRIX_5X3,
+};
+
+struct davinci_ks_platform_data {
+ int (*device_enable)(struct device *dev);
+ unsigned short *keymap;
+ u32 keymapsize;
+ u8 rep:1;
+ u8 strobe;
+ u8 interval;
+ u8 matrix_type;
+};
+
+#endif
+
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
new file mode 100644
index 00000000000..5ba6b22ce33
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/mmc.h
@@ -0,0 +1,39 @@
+/*
+ * Board-specific MMC configuration
+ */
+
+#ifndef _DAVINCI_MMC_H
+#define _DAVINCI_MMC_H
+
+#include <linux/types.h>
+#include <linux/mmc/host.h>
+
+struct davinci_mmc_config {
+ /* get_cd()/get_wp() may sleep */
+ int (*get_cd)(int module);
+ int (*get_ro)(int module);
+
+ void (*set_power)(int module, bool on);
+
+ /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
+ u8 wires;
+
+ u32 max_freq;
+
+ /* any additional host capabilities: OR'd in to mmc->f_caps */
+ u32 caps;
+
+ /* Version of the MMC/SD controller */
+ u8 version;
+
+ /* Number of sg segments */
+ u8 nr_sg;
+};
+void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
+
+enum {
+ MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
+ MMC_CTLR_VERSION_2, /* DA830 */
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
new file mode 100644
index 00000000000..a7e92fca32e
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -0,0 +1,1217 @@
+/*
+ * Table of the DAVINCI register configurations for the PINMUX combinations
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * Based on linux/include/asm-arm/arch-omap/mux.h:
+ * Copyright (C) 2003 - 2005 Nokia Corporation
+ *
+ * Written by Tony Lindgren
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2008 Texas Instruments.
+ */
+
+#ifndef __INC_MACH_MUX_H
+#define __INC_MACH_MUX_H
+
+struct mux_config {
+ const char *name;
+ const char *mux_reg_name;
+ const unsigned char mux_reg;
+ const unsigned char mask_offset;
+ const unsigned char mask;
+ const unsigned char mode;
+ bool debug;
+};
+
+enum davinci_dm644x_index {
+ /* ATA and HDDIR functions */
+ DM644X_HDIREN,
+ DM644X_ATAEN,
+ DM644X_ATAEN_DISABLE,
+
+ /* HPI functions */
+ DM644X_HPIEN_DISABLE,
+
+ /* AEAW functions */
+ DM644X_AEAW,
+ DM644X_AEAW0,
+ DM644X_AEAW1,
+ DM644X_AEAW2,
+ DM644X_AEAW3,
+ DM644X_AEAW4,
+
+ /* Memory Stick */
+ DM644X_MSTK,
+
+ /* I2C */
+ DM644X_I2C,
+
+ /* ASP function */
+ DM644X_MCBSP,
+
+ /* UART1 */
+ DM644X_UART1,
+
+ /* UART2 */
+ DM644X_UART2,
+
+ /* PWM0 */
+ DM644X_PWM0,
+
+ /* PWM1 */
+ DM644X_PWM1,
+
+ /* PWM2 */
+ DM644X_PWM2,
+
+ /* VLYNQ function */
+ DM644X_VLYNQEN,
+ DM644X_VLSCREN,
+ DM644X_VLYNQWD,
+
+ /* EMAC and MDIO function */
+ DM644X_EMACEN,
+
+ /* GPIO3V[0:16] pins */
+ DM644X_GPIO3V,
+
+ /* GPIO pins */
+ DM644X_GPIO0,
+ DM644X_GPIO3,
+ DM644X_GPIO43_44,
+ DM644X_GPIO46_47,
+
+ /* VPBE */
+ DM644X_RGB666,
+
+ /* LCD */
+ DM644X_LOEEN,
+ DM644X_LFLDEN,
+};
+
+enum davinci_dm646x_index {
+ /* ATA function */
+ DM646X_ATAEN,
+
+ /* AUDIO Clock */
+ DM646X_AUDCK1,
+ DM646X_AUDCK0,
+
+ /* CRGEN Control */
+ DM646X_CRGMUX,
+
+ /* VPIF Control */
+ DM646X_STSOMUX_DISABLE,
+ DM646X_STSIMUX_DISABLE,
+ DM646X_PTSOMUX_DISABLE,
+ DM646X_PTSIMUX_DISABLE,
+
+ /* TSIF Control */
+ DM646X_STSOMUX,
+ DM646X_STSIMUX,
+ DM646X_PTSOMUX_PARALLEL,
+ DM646X_PTSIMUX_PARALLEL,
+ DM646X_PTSOMUX_SERIAL,
+ DM646X_PTSIMUX_SERIAL,
+};
+
+enum davinci_dm355_index {
+ /* MMC/SD 0 */
+ DM355_MMCSD0,
+
+ /* MMC/SD 1 */
+ DM355_SD1_CLK,
+ DM355_SD1_CMD,
+ DM355_SD1_DATA3,
+ DM355_SD1_DATA2,
+ DM355_SD1_DATA1,
+ DM355_SD1_DATA0,
+
+ /* I2C */
+ DM355_I2C_SDA,
+ DM355_I2C_SCL,
+
+ /* ASP0 function */
+ DM355_MCBSP0_BDX,
+ DM355_MCBSP0_X,
+ DM355_MCBSP0_BFSX,
+ DM355_MCBSP0_BDR,
+ DM355_MCBSP0_R,
+ DM355_MCBSP0_BFSR,
+
+ /* SPI0 */
+ DM355_SPI0_SDI,
+ DM355_SPI0_SDENA0,
+ DM355_SPI0_SDENA1,
+
+ /* IRQ muxing */
+ DM355_INT_EDMA_CC,
+ DM355_INT_EDMA_TC0_ERR,
+ DM355_INT_EDMA_TC1_ERR,
+
+ /* EDMA event muxing */
+ DM355_EVT8_ASP1_TX,
+ DM355_EVT9_ASP1_RX,
+ DM355_EVT26_MMC0_RX,
+
+ /* Video Out */
+ DM355_VOUT_FIELD,
+ DM355_VOUT_FIELD_G70,
+ DM355_VOUT_HVSYNC,
+ DM355_VOUT_COUTL_EN,
+ DM355_VOUT_COUTH_EN,
+
+ /* Video In Pin Mux */
+ DM355_VIN_PCLK,
+ DM355_VIN_CAM_WEN,
+ DM355_VIN_CAM_VD,
+ DM355_VIN_CAM_HD,
+ DM355_VIN_YIN_EN,
+ DM355_VIN_CINL_EN,
+ DM355_VIN_CINH_EN,
+};
+
+enum davinci_dm365_index {
+ /* MMC/SD 0 */
+ DM365_MMCSD0,
+
+ /* MMC/SD 1 */
+ DM365_SD1_CLK,
+ DM365_SD1_CMD,
+ DM365_SD1_DATA3,
+ DM365_SD1_DATA2,
+ DM365_SD1_DATA1,
+ DM365_SD1_DATA0,
+
+ /* I2C */
+ DM365_I2C_SDA,
+ DM365_I2C_SCL,
+
+ /* AEMIF */
+ DM365_AEMIF_AR_A14,
+ DM365_AEMIF_AR_BA0,
+ DM365_AEMIF_A3,
+ DM365_AEMIF_A7,
+ DM365_AEMIF_D15_8,
+ DM365_AEMIF_CE0,
+ DM365_AEMIF_CE1,
+ DM365_AEMIF_WE_OE,
+
+ /* ASP0 function */
+ DM365_MCBSP0_BDX,
+ DM365_MCBSP0_X,
+ DM365_MCBSP0_BFSX,
+ DM365_MCBSP0_BDR,
+ DM365_MCBSP0_R,
+ DM365_MCBSP0_BFSR,
+
+ /* SPI0 */
+ DM365_SPI0_SCLK,
+ DM365_SPI0_SDI,
+ DM365_SPI0_SDO,
+ DM365_SPI0_SDENA0,
+ DM365_SPI0_SDENA1,
+
+ /* UART */
+ DM365_UART0_RXD,
+ DM365_UART0_TXD,
+ DM365_UART1_RXD,
+ DM365_UART1_TXD,
+ DM365_UART1_RTS,
+ DM365_UART1_CTS,
+
+ /* EMAC */
+ DM365_EMAC_TX_EN,
+ DM365_EMAC_TX_CLK,
+ DM365_EMAC_COL,
+ DM365_EMAC_TXD3,
+ DM365_EMAC_TXD2,
+ DM365_EMAC_TXD1,
+ DM365_EMAC_TXD0,
+ DM365_EMAC_RXD3,
+ DM365_EMAC_RXD2,
+ DM365_EMAC_RXD1,
+ DM365_EMAC_RXD0,
+ DM365_EMAC_RX_CLK,
+ DM365_EMAC_RX_DV,
+ DM365_EMAC_RX_ER,
+ DM365_EMAC_CRS,
+ DM365_EMAC_MDIO,
+ DM365_EMAC_MDCLK,
+
+ /* Key Scan */
+ DM365_KEYSCAN,
+
+ /* PWM */
+ DM365_PWM0,
+ DM365_PWM0_G23,
+ DM365_PWM1,
+ DM365_PWM1_G25,
+ DM365_PWM2_G87,
+ DM365_PWM2_G88,
+ DM365_PWM2_G89,
+ DM365_PWM2_G90,
+ DM365_PWM3_G80,
+ DM365_PWM3_G81,
+ DM365_PWM3_G85,
+ DM365_PWM3_G86,
+
+ /* SPI1 */
+ DM365_SPI1_SCLK,
+ DM365_SPI1_SDO,
+ DM365_SPI1_SDI,
+ DM365_SPI1_SDENA0,
+ DM365_SPI1_SDENA1,
+
+ /* SPI2 */
+ DM365_SPI2_SCLK,
+ DM365_SPI2_SDO,
+ DM365_SPI2_SDI,
+ DM365_SPI2_SDENA0,
+ DM365_SPI2_SDENA1,
+
+ /* SPI3 */
+ DM365_SPI3_SCLK,
+ DM365_SPI3_SDO,
+ DM365_SPI3_SDI,
+ DM365_SPI3_SDENA0,
+ DM365_SPI3_SDENA1,
+
+ /* SPI4 */
+ DM365_SPI4_SCLK,
+ DM365_SPI4_SDO,
+ DM365_SPI4_SDI,
+ DM365_SPI4_SDENA0,
+ DM365_SPI4_SDENA1,
+
+ /* Clock */
+ DM365_CLKOUT0,
+ DM365_CLKOUT1,
+ DM365_CLKOUT2,
+
+ /* GPIO */
+ DM365_GPIO20,
+ DM365_GPIO30,
+ DM365_GPIO31,
+ DM365_GPIO32,
+ DM365_GPIO33,
+ DM365_GPIO40,
+ DM365_GPIO64_57,
+
+ /* Video */
+ DM365_VOUT_FIELD,
+ DM365_VOUT_FIELD_G81,
+ DM365_VOUT_HVSYNC,
+ DM365_VOUT_COUTL_EN,
+ DM365_VOUT_COUTH_EN,
+ DM365_VIN_CAM_WEN,
+ DM365_VIN_CAM_VD,
+ DM365_VIN_CAM_HD,
+ DM365_VIN_YIN4_7_EN,
+ DM365_VIN_YIN0_3_EN,
+
+ /* IRQ muxing */
+ DM365_INT_EDMA_CC,
+ DM365_INT_EDMA_TC0_ERR,
+ DM365_INT_EDMA_TC1_ERR,
+ DM365_INT_EDMA_TC2_ERR,
+ DM365_INT_EDMA_TC3_ERR,
+ DM365_INT_PRTCSS,
+ DM365_INT_EMAC_RXTHRESH,
+ DM365_INT_EMAC_RXPULSE,
+ DM365_INT_EMAC_TXPULSE,
+ DM365_INT_EMAC_MISCPULSE,
+ DM365_INT_IMX0_ENABLE,
+ DM365_INT_IMX0_DISABLE,
+ DM365_INT_HDVICP_ENABLE,
+ DM365_INT_HDVICP_DISABLE,
+ DM365_INT_IMX1_ENABLE,
+ DM365_INT_IMX1_DISABLE,
+ DM365_INT_NSF_ENABLE,
+ DM365_INT_NSF_DISABLE,
+
+ /* EDMA event muxing */
+ DM365_EVT2_ASP_TX,
+ DM365_EVT3_ASP_RX,
+ DM365_EVT2_VC_TX,
+ DM365_EVT3_VC_RX,
+ DM365_EVT26_MMC0_RX,
+};
+
+enum da830_index {
+ DA830_GPIO7_14,
+ DA830_RTCK,
+ DA830_GPIO7_15,
+ DA830_EMU_0,
+ DA830_EMB_SDCKE,
+ DA830_EMB_CLK_GLUE,
+ DA830_EMB_CLK,
+ DA830_NEMB_CS_0,
+ DA830_NEMB_CAS,
+ DA830_NEMB_RAS,
+ DA830_NEMB_WE,
+ DA830_EMB_BA_1,
+ DA830_EMB_BA_0,
+ DA830_EMB_A_0,
+ DA830_EMB_A_1,
+ DA830_EMB_A_2,
+ DA830_EMB_A_3,
+ DA830_EMB_A_4,
+ DA830_EMB_A_5,
+ DA830_GPIO7_0,
+ DA830_GPIO7_1,
+ DA830_GPIO7_2,
+ DA830_GPIO7_3,
+ DA830_GPIO7_4,
+ DA830_GPIO7_5,
+ DA830_GPIO7_6,
+ DA830_GPIO7_7,
+ DA830_EMB_A_6,
+ DA830_EMB_A_7,
+ DA830_EMB_A_8,
+ DA830_EMB_A_9,
+ DA830_EMB_A_10,
+ DA830_EMB_A_11,
+ DA830_EMB_A_12,
+ DA830_EMB_D_31,
+ DA830_GPIO7_8,
+ DA830_GPIO7_9,
+ DA830_GPIO7_10,
+ DA830_GPIO7_11,
+ DA830_GPIO7_12,
+ DA830_GPIO7_13,
+ DA830_GPIO3_13,
+ DA830_EMB_D_30,
+ DA830_EMB_D_29,
+ DA830_EMB_D_28,
+ DA830_EMB_D_27,
+ DA830_EMB_D_26,
+ DA830_EMB_D_25,
+ DA830_EMB_D_24,
+ DA830_EMB_D_23,
+ DA830_EMB_D_22,
+ DA830_EMB_D_21,
+ DA830_EMB_D_20,
+ DA830_EMB_D_19,
+ DA830_EMB_D_18,
+ DA830_EMB_D_17,
+ DA830_EMB_D_16,
+ DA830_NEMB_WE_DQM_3,
+ DA830_NEMB_WE_DQM_2,
+ DA830_EMB_D_0,
+ DA830_EMB_D_1,
+ DA830_EMB_D_2,
+ DA830_EMB_D_3,
+ DA830_EMB_D_4,
+ DA830_EMB_D_5,
+ DA830_EMB_D_6,
+ DA830_GPIO6_0,
+ DA830_GPIO6_1,
+ DA830_GPIO6_2,
+ DA830_GPIO6_3,
+ DA830_GPIO6_4,
+ DA830_GPIO6_5,
+ DA830_GPIO6_6,
+ DA830_EMB_D_7,
+ DA830_EMB_D_8,
+ DA830_EMB_D_9,
+ DA830_EMB_D_10,
+ DA830_EMB_D_11,
+ DA830_EMB_D_12,
+ DA830_EMB_D_13,
+ DA830_EMB_D_14,
+ DA830_GPIO6_7,
+ DA830_GPIO6_8,
+ DA830_GPIO6_9,
+ DA830_GPIO6_10,
+ DA830_GPIO6_11,
+ DA830_GPIO6_12,
+ DA830_GPIO6_13,
+ DA830_GPIO6_14,
+ DA830_EMB_D_15,
+ DA830_NEMB_WE_DQM_1,
+ DA830_NEMB_WE_DQM_0,
+ DA830_SPI0_SOMI_0,
+ DA830_SPI0_SIMO_0,
+ DA830_SPI0_CLK,
+ DA830_NSPI0_ENA,
+ DA830_NSPI0_SCS_0,
+ DA830_EQEP0I,
+ DA830_EQEP0S,
+ DA830_EQEP1I,
+ DA830_NUART0_CTS,
+ DA830_NUART0_RTS,
+ DA830_EQEP0A,
+ DA830_EQEP0B,
+ DA830_GPIO6_15,
+ DA830_GPIO5_14,
+ DA830_GPIO5_15,
+ DA830_GPIO5_0,
+ DA830_GPIO5_1,
+ DA830_GPIO5_2,
+ DA830_GPIO5_3,
+ DA830_GPIO5_4,
+ DA830_SPI1_SOMI_0,
+ DA830_SPI1_SIMO_0,
+ DA830_SPI1_CLK,
+ DA830_UART0_RXD,
+ DA830_UART0_TXD,
+ DA830_AXR1_10,
+ DA830_AXR1_11,
+ DA830_NSPI1_ENA,
+ DA830_I2C1_SCL,
+ DA830_I2C1_SDA,
+ DA830_EQEP1S,
+ DA830_I2C0_SDA,
+ DA830_I2C0_SCL,
+ DA830_UART2_RXD,
+ DA830_TM64P0_IN12,
+ DA830_TM64P0_OUT12,
+ DA830_GPIO5_5,
+ DA830_GPIO5_6,
+ DA830_GPIO5_7,
+ DA830_GPIO5_8,
+ DA830_GPIO5_9,
+ DA830_GPIO5_10,
+ DA830_GPIO5_11,
+ DA830_GPIO5_12,
+ DA830_NSPI1_SCS_0,
+ DA830_USB0_DRVVBUS,
+ DA830_AHCLKX0,
+ DA830_ACLKX0,
+ DA830_AFSX0,
+ DA830_AHCLKR0,
+ DA830_ACLKR0,
+ DA830_AFSR0,
+ DA830_UART2_TXD,
+ DA830_AHCLKX2,
+ DA830_ECAP0_APWM0,
+ DA830_RMII_MHZ_50_CLK,
+ DA830_ECAP1_APWM1,
+ DA830_USB_REFCLKIN,
+ DA830_GPIO5_13,
+ DA830_GPIO4_15,
+ DA830_GPIO2_11,
+ DA830_GPIO2_12,
+ DA830_GPIO2_13,
+ DA830_GPIO2_14,
+ DA830_GPIO2_15,
+ DA830_GPIO3_12,
+ DA830_AMUTE0,
+ DA830_AXR0_0,
+ DA830_AXR0_1,
+ DA830_AXR0_2,
+ DA830_AXR0_3,
+ DA830_AXR0_4,
+ DA830_AXR0_5,
+ DA830_AXR0_6,
+ DA830_RMII_TXD_0,
+ DA830_RMII_TXD_1,
+ DA830_RMII_TXEN,
+ DA830_RMII_CRS_DV,
+ DA830_RMII_RXD_0,
+ DA830_RMII_RXD_1,
+ DA830_RMII_RXER,
+ DA830_AFSR2,
+ DA830_ACLKX2,
+ DA830_AXR2_3,
+ DA830_AXR2_2,
+ DA830_AXR2_1,
+ DA830_AFSX2,
+ DA830_ACLKR2,
+ DA830_NRESETOUT,
+ DA830_GPIO3_0,
+ DA830_GPIO3_1,
+ DA830_GPIO3_2,
+ DA830_GPIO3_3,
+ DA830_GPIO3_4,
+ DA830_GPIO3_5,
+ DA830_GPIO3_6,
+ DA830_AXR0_7,
+ DA830_AXR0_8,
+ DA830_UART1_RXD,
+ DA830_UART1_TXD,
+ DA830_AXR0_11,
+ DA830_AHCLKX1,
+ DA830_ACLKX1,
+ DA830_AFSX1,
+ DA830_MDIO_CLK,
+ DA830_MDIO_D,
+ DA830_AXR0_9,
+ DA830_AXR0_10,
+ DA830_EPWM0B,
+ DA830_EPWM0A,
+ DA830_EPWMSYNCI,
+ DA830_AXR2_0,
+ DA830_EPWMSYNC0,
+ DA830_GPIO3_7,
+ DA830_GPIO3_8,
+ DA830_GPIO3_9,
+ DA830_GPIO3_10,
+ DA830_GPIO3_11,
+ DA830_GPIO3_14,
+ DA830_GPIO3_15,
+ DA830_GPIO4_10,
+ DA830_AHCLKR1,
+ DA830_ACLKR1,
+ DA830_AFSR1,
+ DA830_AMUTE1,
+ DA830_AXR1_0,
+ DA830_AXR1_1,
+ DA830_AXR1_2,
+ DA830_AXR1_3,
+ DA830_ECAP2_APWM2,
+ DA830_EHRPWMGLUETZ,
+ DA830_EQEP1A,
+ DA830_GPIO4_11,
+ DA830_GPIO4_12,
+ DA830_GPIO4_13,
+ DA830_GPIO4_14,
+ DA830_GPIO4_0,
+ DA830_GPIO4_1,
+ DA830_GPIO4_2,
+ DA830_GPIO4_3,
+ DA830_AXR1_4,
+ DA830_AXR1_5,
+ DA830_AXR1_6,
+ DA830_AXR1_7,
+ DA830_AXR1_8,
+ DA830_AXR1_9,
+ DA830_EMA_D_0,
+ DA830_EMA_D_1,
+ DA830_EQEP1B,
+ DA830_EPWM2B,
+ DA830_EPWM2A,
+ DA830_EPWM1B,
+ DA830_EPWM1A,
+ DA830_MMCSD_DAT_0,
+ DA830_MMCSD_DAT_1,
+ DA830_UHPI_HD_0,
+ DA830_UHPI_HD_1,
+ DA830_GPIO4_4,
+ DA830_GPIO4_5,
+ DA830_GPIO4_6,
+ DA830_GPIO4_7,
+ DA830_GPIO4_8,
+ DA830_GPIO4_9,
+ DA830_GPIO0_0,
+ DA830_GPIO0_1,
+ DA830_EMA_D_2,
+ DA830_EMA_D_3,
+ DA830_EMA_D_4,
+ DA830_EMA_D_5,
+ DA830_EMA_D_6,
+ DA830_EMA_D_7,
+ DA830_EMA_D_8,
+ DA830_EMA_D_9,
+ DA830_MMCSD_DAT_2,
+ DA830_MMCSD_DAT_3,
+ DA830_MMCSD_DAT_4,
+ DA830_MMCSD_DAT_5,
+ DA830_MMCSD_DAT_6,
+ DA830_MMCSD_DAT_7,
+ DA830_UHPI_HD_8,
+ DA830_UHPI_HD_9,
+ DA830_UHPI_HD_2,
+ DA830_UHPI_HD_3,
+ DA830_UHPI_HD_4,
+ DA830_UHPI_HD_5,
+ DA830_UHPI_HD_6,
+ DA830_UHPI_HD_7,
+ DA830_LCD_D_8,
+ DA830_LCD_D_9,
+ DA830_GPIO0_2,
+ DA830_GPIO0_3,
+ DA830_GPIO0_4,
+ DA830_GPIO0_5,
+ DA830_GPIO0_6,
+ DA830_GPIO0_7,
+ DA830_GPIO0_8,
+ DA830_GPIO0_9,
+ DA830_EMA_D_10,
+ DA830_EMA_D_11,
+ DA830_EMA_D_12,
+ DA830_EMA_D_13,
+ DA830_EMA_D_14,
+ DA830_EMA_D_15,
+ DA830_EMA_A_0,
+ DA830_EMA_A_1,
+ DA830_UHPI_HD_10,
+ DA830_UHPI_HD_11,
+ DA830_UHPI_HD_12,
+ DA830_UHPI_HD_13,
+ DA830_UHPI_HD_14,
+ DA830_UHPI_HD_15,
+ DA830_LCD_D_7,
+ DA830_MMCSD_CLK,
+ DA830_LCD_D_10,
+ DA830_LCD_D_11,
+ DA830_LCD_D_12,
+ DA830_LCD_D_13,
+ DA830_LCD_D_14,
+ DA830_LCD_D_15,
+ DA830_UHPI_HCNTL0,
+ DA830_GPIO0_10,
+ DA830_GPIO0_11,
+ DA830_GPIO0_12,
+ DA830_GPIO0_13,
+ DA830_GPIO0_14,
+ DA830_GPIO0_15,
+ DA830_GPIO1_0,
+ DA830_GPIO1_1,
+ DA830_EMA_A_2,
+ DA830_EMA_A_3,
+ DA830_EMA_A_4,
+ DA830_EMA_A_5,
+ DA830_EMA_A_6,
+ DA830_EMA_A_7,
+ DA830_EMA_A_8,
+ DA830_EMA_A_9,
+ DA830_MMCSD_CMD,
+ DA830_LCD_D_6,
+ DA830_LCD_D_3,
+ DA830_LCD_D_2,
+ DA830_LCD_D_1,
+ DA830_LCD_D_0,
+ DA830_LCD_PCLK,
+ DA830_LCD_HSYNC,
+ DA830_UHPI_HCNTL1,
+ DA830_GPIO1_2,
+ DA830_GPIO1_3,
+ DA830_GPIO1_4,
+ DA830_GPIO1_5,
+ DA830_GPIO1_6,
+ DA830_GPIO1_7,
+ DA830_GPIO1_8,
+ DA830_GPIO1_9,
+ DA830_EMA_A_10,
+ DA830_EMA_A_11,
+ DA830_EMA_A_12,
+ DA830_EMA_BA_1,
+ DA830_EMA_BA_0,
+ DA830_EMA_CLK,
+ DA830_EMA_SDCKE,
+ DA830_NEMA_CAS,
+ DA830_LCD_VSYNC,
+ DA830_NLCD_AC_ENB_CS,
+ DA830_LCD_MCLK,
+ DA830_LCD_D_5,
+ DA830_LCD_D_4,
+ DA830_OBSCLK,
+ DA830_NEMA_CS_4,
+ DA830_UHPI_HHWIL,
+ DA830_AHCLKR2,
+ DA830_GPIO1_10,
+ DA830_GPIO1_11,
+ DA830_GPIO1_12,
+ DA830_GPIO1_13,
+ DA830_GPIO1_14,
+ DA830_GPIO1_15,
+ DA830_GPIO2_0,
+ DA830_GPIO2_1,
+ DA830_NEMA_RAS,
+ DA830_NEMA_WE,
+ DA830_NEMA_CS_0,
+ DA830_NEMA_CS_2,
+ DA830_NEMA_CS_3,
+ DA830_NEMA_OE,
+ DA830_NEMA_WE_DQM_1,
+ DA830_NEMA_WE_DQM_0,
+ DA830_NEMA_CS_5,
+ DA830_UHPI_HRNW,
+ DA830_NUHPI_HAS,
+ DA830_NUHPI_HCS,
+ DA830_NUHPI_HDS1,
+ DA830_NUHPI_HDS2,
+ DA830_NUHPI_HINT,
+ DA830_AXR0_12,
+ DA830_AMUTE2,
+ DA830_AXR0_13,
+ DA830_AXR0_14,
+ DA830_AXR0_15,
+ DA830_GPIO2_2,
+ DA830_GPIO2_3,
+ DA830_GPIO2_4,
+ DA830_GPIO2_5,
+ DA830_GPIO2_6,
+ DA830_GPIO2_7,
+ DA830_GPIO2_8,
+ DA830_GPIO2_9,
+ DA830_EMA_WAIT_0,
+ DA830_NUHPI_HRDY,
+ DA830_GPIO2_10,
+};
+
+enum davinci_da850_index {
+ /* UART0 function */
+ DA850_NUART0_CTS,
+ DA850_NUART0_RTS,
+ DA850_UART0_RXD,
+ DA850_UART0_TXD,
+
+ /* UART1 function */
+ DA850_NUART1_CTS,
+ DA850_NUART1_RTS,
+ DA850_UART1_RXD,
+ DA850_UART1_TXD,
+
+ /* UART2 function */
+ DA850_NUART2_CTS,
+ DA850_NUART2_RTS,
+ DA850_UART2_RXD,
+ DA850_UART2_TXD,
+
+ /* I2C1 function */
+ DA850_I2C1_SCL,
+ DA850_I2C1_SDA,
+
+ /* I2C0 function */
+ DA850_I2C0_SDA,
+ DA850_I2C0_SCL,
+
+ /* EMAC function */
+ DA850_MII_TXEN,
+ DA850_MII_TXCLK,
+ DA850_MII_COL,
+ DA850_MII_TXD_3,
+ DA850_MII_TXD_2,
+ DA850_MII_TXD_1,
+ DA850_MII_TXD_0,
+ DA850_MII_RXER,
+ DA850_MII_CRS,
+ DA850_MII_RXCLK,
+ DA850_MII_RXDV,
+ DA850_MII_RXD_3,
+ DA850_MII_RXD_2,
+ DA850_MII_RXD_1,
+ DA850_MII_RXD_0,
+ DA850_MDIO_CLK,
+ DA850_MDIO_D,
+ DA850_RMII_TXD_0,
+ DA850_RMII_TXD_1,
+ DA850_RMII_TXEN,
+ DA850_RMII_CRS_DV,
+ DA850_RMII_RXD_0,
+ DA850_RMII_RXD_1,
+ DA850_RMII_RXER,
+ DA850_RMII_MHZ_50_CLK,
+
+ /* McASP function */
+ DA850_ACLKR,
+ DA850_ACLKX,
+ DA850_AFSR,
+ DA850_AFSX,
+ DA850_AHCLKR,
+ DA850_AHCLKX,
+ DA850_AMUTE,
+ DA850_AXR_15,
+ DA850_AXR_14,
+ DA850_AXR_13,
+ DA850_AXR_12,
+ DA850_AXR_11,
+ DA850_AXR_10,
+ DA850_AXR_9,
+ DA850_AXR_8,
+ DA850_AXR_7,
+ DA850_AXR_6,
+ DA850_AXR_5,
+ DA850_AXR_4,
+ DA850_AXR_3,
+ DA850_AXR_2,
+ DA850_AXR_1,
+ DA850_AXR_0,
+
+ /* LCD function */
+ DA850_LCD_D_7,
+ DA850_LCD_D_6,
+ DA850_LCD_D_5,
+ DA850_LCD_D_4,
+ DA850_LCD_D_3,
+ DA850_LCD_D_2,
+ DA850_LCD_D_1,
+ DA850_LCD_D_0,
+ DA850_LCD_D_15,
+ DA850_LCD_D_14,
+ DA850_LCD_D_13,
+ DA850_LCD_D_12,
+ DA850_LCD_D_11,
+ DA850_LCD_D_10,
+ DA850_LCD_D_9,
+ DA850_LCD_D_8,
+ DA850_LCD_PCLK,
+ DA850_LCD_HSYNC,
+ DA850_LCD_VSYNC,
+ DA850_NLCD_AC_ENB_CS,
+
+ /* MMC/SD0 function */
+ DA850_MMCSD0_DAT_0,
+ DA850_MMCSD0_DAT_1,
+ DA850_MMCSD0_DAT_2,
+ DA850_MMCSD0_DAT_3,
+ DA850_MMCSD0_CLK,
+ DA850_MMCSD0_CMD,
+
+ /* MMC/SD1 function */
+ DA850_MMCSD1_DAT_0,
+ DA850_MMCSD1_DAT_1,
+ DA850_MMCSD1_DAT_2,
+ DA850_MMCSD1_DAT_3,
+ DA850_MMCSD1_CLK,
+ DA850_MMCSD1_CMD,
+
+ /* EMIF2.5/EMIFA function */
+ DA850_EMA_D_7,
+ DA850_EMA_D_6,
+ DA850_EMA_D_5,
+ DA850_EMA_D_4,
+ DA850_EMA_D_3,
+ DA850_EMA_D_2,
+ DA850_EMA_D_1,
+ DA850_EMA_D_0,
+ DA850_EMA_A_1,
+ DA850_EMA_A_2,
+ DA850_NEMA_CS_3,
+ DA850_NEMA_CS_4,
+ DA850_NEMA_WE,
+ DA850_NEMA_OE,
+ DA850_EMA_D_15,
+ DA850_EMA_D_14,
+ DA850_EMA_D_13,
+ DA850_EMA_D_12,
+ DA850_EMA_D_11,
+ DA850_EMA_D_10,
+ DA850_EMA_D_9,
+ DA850_EMA_D_8,
+ DA850_EMA_A_0,
+ DA850_EMA_A_3,
+ DA850_EMA_A_4,
+ DA850_EMA_A_5,
+ DA850_EMA_A_6,
+ DA850_EMA_A_7,
+ DA850_EMA_A_8,
+ DA850_EMA_A_9,
+ DA850_EMA_A_10,
+ DA850_EMA_A_11,
+ DA850_EMA_A_12,
+ DA850_EMA_A_13,
+ DA850_EMA_A_14,
+ DA850_EMA_A_15,
+ DA850_EMA_A_16,
+ DA850_EMA_A_17,
+ DA850_EMA_A_18,
+ DA850_EMA_A_19,
+ DA850_EMA_A_20,
+ DA850_EMA_A_21,
+ DA850_EMA_A_22,
+ DA850_EMA_A_23,
+ DA850_EMA_BA_1,
+ DA850_EMA_CLK,
+ DA850_EMA_WAIT_1,
+ DA850_NEMA_CS_2,
+
+ /* GPIO function */
+ DA850_GPIO2_4,
+ DA850_GPIO2_6,
+ DA850_GPIO2_8,
+ DA850_GPIO2_15,
+ DA850_GPIO3_12,
+ DA850_GPIO3_13,
+ DA850_GPIO4_0,
+ DA850_GPIO4_1,
+ DA850_GPIO6_9,
+ DA850_GPIO6_10,
+ DA850_GPIO6_13,
+ DA850_RTC_ALARM,
+};
+
+enum davinci_tnetv107x_index {
+ TNETV107X_ASR_A00,
+ TNETV107X_GPIO32,
+ TNETV107X_ASR_A01,
+ TNETV107X_GPIO33,
+ TNETV107X_ASR_A02,
+ TNETV107X_GPIO34,
+ TNETV107X_ASR_A03,
+ TNETV107X_GPIO35,
+ TNETV107X_ASR_A04,
+ TNETV107X_GPIO36,
+ TNETV107X_ASR_A05,
+ TNETV107X_GPIO37,
+ TNETV107X_ASR_A06,
+ TNETV107X_GPIO38,
+ TNETV107X_ASR_A07,
+ TNETV107X_GPIO39,
+ TNETV107X_ASR_A08,
+ TNETV107X_GPIO40,
+ TNETV107X_ASR_A09,
+ TNETV107X_GPIO41,
+ TNETV107X_ASR_A10,
+ TNETV107X_GPIO42,
+ TNETV107X_ASR_A11,
+ TNETV107X_BOOT_STRP_0,
+ TNETV107X_ASR_A12,
+ TNETV107X_BOOT_STRP_1,
+ TNETV107X_ASR_A13,
+ TNETV107X_GPIO43,
+ TNETV107X_ASR_A14,
+ TNETV107X_GPIO44,
+ TNETV107X_ASR_A15,
+ TNETV107X_GPIO45,
+ TNETV107X_ASR_A16,
+ TNETV107X_GPIO46,
+ TNETV107X_ASR_A17,
+ TNETV107X_GPIO47,
+ TNETV107X_ASR_A18,
+ TNETV107X_GPIO48,
+ TNETV107X_SDIO1_DATA3_0,
+ TNETV107X_ASR_A19,
+ TNETV107X_GPIO49,
+ TNETV107X_SDIO1_DATA2_0,
+ TNETV107X_ASR_A20,
+ TNETV107X_GPIO50,
+ TNETV107X_SDIO1_DATA1_0,
+ TNETV107X_ASR_A21,
+ TNETV107X_GPIO51,
+ TNETV107X_SDIO1_DATA0_0,
+ TNETV107X_ASR_A22,
+ TNETV107X_GPIO52,
+ TNETV107X_SDIO1_CMD_0,
+ TNETV107X_ASR_A23,
+ TNETV107X_GPIO53,
+ TNETV107X_SDIO1_CLK_0,
+ TNETV107X_ASR_BA_1,
+ TNETV107X_GPIO54,
+ TNETV107X_SYS_PLL_CLK,
+ TNETV107X_ASR_CS0,
+ TNETV107X_ASR_CS1,
+ TNETV107X_ASR_CS2,
+ TNETV107X_TDM_PLL_CLK,
+ TNETV107X_ASR_CS3,
+ TNETV107X_ETH_PHY_CLK,
+ TNETV107X_ASR_D00,
+ TNETV107X_GPIO55,
+ TNETV107X_ASR_D01,
+ TNETV107X_GPIO56,
+ TNETV107X_ASR_D02,
+ TNETV107X_GPIO57,
+ TNETV107X_ASR_D03,
+ TNETV107X_GPIO58,
+ TNETV107X_ASR_D04,
+ TNETV107X_GPIO59_0,
+ TNETV107X_ASR_D05,
+ TNETV107X_GPIO60_0,
+ TNETV107X_ASR_D06,
+ TNETV107X_GPIO61_0,
+ TNETV107X_ASR_D07,
+ TNETV107X_GPIO62_0,
+ TNETV107X_ASR_D08,
+ TNETV107X_GPIO63_0,
+ TNETV107X_ASR_D09,
+ TNETV107X_GPIO64_0,
+ TNETV107X_ASR_D10,
+ TNETV107X_SDIO1_DATA3_1,
+ TNETV107X_ASR_D11,
+ TNETV107X_SDIO1_DATA2_1,
+ TNETV107X_ASR_D12,
+ TNETV107X_SDIO1_DATA1_1,
+ TNETV107X_ASR_D13,
+ TNETV107X_SDIO1_DATA0_1,
+ TNETV107X_ASR_D14,
+ TNETV107X_SDIO1_CMD_1,
+ TNETV107X_ASR_D15,
+ TNETV107X_SDIO1_CLK_1,
+ TNETV107X_ASR_OE,
+ TNETV107X_BOOT_STRP_2,
+ TNETV107X_ASR_RNW,
+ TNETV107X_GPIO29_0,
+ TNETV107X_ASR_WAIT,
+ TNETV107X_GPIO30_0,
+ TNETV107X_ASR_WE,
+ TNETV107X_BOOT_STRP_3,
+ TNETV107X_ASR_WE_DQM0,
+ TNETV107X_GPIO31,
+ TNETV107X_LCD_PD17_0,
+ TNETV107X_ASR_WE_DQM1,
+ TNETV107X_ASR_BA0_0,
+ TNETV107X_VLYNQ_CLK,
+ TNETV107X_GPIO14,
+ TNETV107X_LCD_PD19_0,
+ TNETV107X_VLYNQ_RXD0,
+ TNETV107X_GPIO15,
+ TNETV107X_LCD_PD20_0,
+ TNETV107X_VLYNQ_RXD1,
+ TNETV107X_GPIO16,
+ TNETV107X_LCD_PD21_0,
+ TNETV107X_VLYNQ_TXD0,
+ TNETV107X_GPIO17,
+ TNETV107X_LCD_PD22_0,
+ TNETV107X_VLYNQ_TXD1,
+ TNETV107X_GPIO18,
+ TNETV107X_LCD_PD23_0,
+ TNETV107X_SDIO0_CLK,
+ TNETV107X_GPIO19,
+ TNETV107X_SDIO0_CMD,
+ TNETV107X_GPIO20,
+ TNETV107X_SDIO0_DATA0,
+ TNETV107X_GPIO21,
+ TNETV107X_SDIO0_DATA1,
+ TNETV107X_GPIO22,
+ TNETV107X_SDIO0_DATA2,
+ TNETV107X_GPIO23,
+ TNETV107X_SDIO0_DATA3,
+ TNETV107X_GPIO24,
+ TNETV107X_EMU0,
+ TNETV107X_EMU1,
+ TNETV107X_RTCK,
+ TNETV107X_TRST_N,
+ TNETV107X_TCK,
+ TNETV107X_TDI,
+ TNETV107X_TDO,
+ TNETV107X_TMS,
+ TNETV107X_TDM1_CLK,
+ TNETV107X_TDM1_RX,
+ TNETV107X_TDM1_TX,
+ TNETV107X_TDM1_FS,
+ TNETV107X_KEYPAD_R0,
+ TNETV107X_KEYPAD_R1,
+ TNETV107X_KEYPAD_R2,
+ TNETV107X_KEYPAD_R3,
+ TNETV107X_KEYPAD_R4,
+ TNETV107X_KEYPAD_R5,
+ TNETV107X_KEYPAD_R6,
+ TNETV107X_GPIO12,
+ TNETV107X_KEYPAD_R7,
+ TNETV107X_GPIO10,
+ TNETV107X_KEYPAD_C0,
+ TNETV107X_KEYPAD_C1,
+ TNETV107X_KEYPAD_C2,
+ TNETV107X_KEYPAD_C3,
+ TNETV107X_KEYPAD_C4,
+ TNETV107X_KEYPAD_C5,
+ TNETV107X_KEYPAD_C6,
+ TNETV107X_GPIO13,
+ TNETV107X_TEST_CLK_IN,
+ TNETV107X_KEYPAD_C7,
+ TNETV107X_GPIO11,
+ TNETV107X_SSP0_0,
+ TNETV107X_SCC_DCLK,
+ TNETV107X_LCD_PD20_1,
+ TNETV107X_SSP0_1,
+ TNETV107X_SCC_CS_N,
+ TNETV107X_LCD_PD21_1,
+ TNETV107X_SSP0_2,
+ TNETV107X_SCC_D,
+ TNETV107X_LCD_PD22_1,
+ TNETV107X_SSP0_3,
+ TNETV107X_SCC_RESETN,
+ TNETV107X_LCD_PD23_1,
+ TNETV107X_SSP1_0,
+ TNETV107X_GPIO25,
+ TNETV107X_UART2_CTS,
+ TNETV107X_SSP1_1,
+ TNETV107X_GPIO26,
+ TNETV107X_UART2_RD,
+ TNETV107X_SSP1_2,
+ TNETV107X_GPIO27,
+ TNETV107X_UART2_RTS,
+ TNETV107X_SSP1_3,
+ TNETV107X_GPIO28,
+ TNETV107X_UART2_TD,
+ TNETV107X_UART0_CTS,
+ TNETV107X_UART0_RD,
+ TNETV107X_UART0_RTS,
+ TNETV107X_UART0_TD,
+ TNETV107X_UART1_RD,
+ TNETV107X_UART1_TD,
+ TNETV107X_LCD_AC_NCS,
+ TNETV107X_LCD_HSYNC_RNW,
+ TNETV107X_LCD_VSYNC_A0,
+ TNETV107X_LCD_MCLK,
+ TNETV107X_LCD_PD16_0,
+ TNETV107X_LCD_PCLK_E,
+ TNETV107X_LCD_PD00,
+ TNETV107X_LCD_PD01,
+ TNETV107X_LCD_PD02,
+ TNETV107X_LCD_PD03,
+ TNETV107X_LCD_PD04,
+ TNETV107X_LCD_PD05,
+ TNETV107X_LCD_PD06,
+ TNETV107X_LCD_PD07,
+ TNETV107X_LCD_PD08,
+ TNETV107X_GPIO59_1,
+ TNETV107X_LCD_PD09,
+ TNETV107X_GPIO60_1,
+ TNETV107X_LCD_PD10,
+ TNETV107X_ASR_BA0_1,
+ TNETV107X_GPIO61_1,
+ TNETV107X_LCD_PD11,
+ TNETV107X_GPIO62_1,
+ TNETV107X_LCD_PD12,
+ TNETV107X_GPIO63_1,
+ TNETV107X_LCD_PD13,
+ TNETV107X_GPIO64_1,
+ TNETV107X_LCD_PD14,
+ TNETV107X_GPIO29_1,
+ TNETV107X_LCD_PD15,
+ TNETV107X_GPIO30_1,
+ TNETV107X_EINT0,
+ TNETV107X_GPIO08,
+ TNETV107X_EINT1,
+ TNETV107X_GPIO09,
+ TNETV107X_GPIO00,
+ TNETV107X_LCD_PD20_2,
+ TNETV107X_TDM_CLK_IN_2,
+ TNETV107X_GPIO01,
+ TNETV107X_LCD_PD21_2,
+ TNETV107X_24M_CLK_OUT_1,
+ TNETV107X_GPIO02,
+ TNETV107X_LCD_PD22_2,
+ TNETV107X_GPIO03,
+ TNETV107X_LCD_PD23_2,
+ TNETV107X_GPIO04,
+ TNETV107X_LCD_PD16_1,
+ TNETV107X_USB0_RXERR,
+ TNETV107X_GPIO05,
+ TNETV107X_LCD_PD17_1,
+ TNETV107X_TDM_CLK_IN_1,
+ TNETV107X_GPIO06,
+ TNETV107X_LCD_PD18,
+ TNETV107X_24M_CLK_OUT_2,
+ TNETV107X_GPIO07,
+ TNETV107X_LCD_PD19_1,
+ TNETV107X_USB1_RXERR,
+ TNETV107X_ETH_PLL_CLK,
+ TNETV107X_MDIO,
+ TNETV107X_MDC,
+ TNETV107X_AIC_MUTE_STAT_N,
+ TNETV107X_TDM0_CLK,
+ TNETV107X_AIC_HNS_EN_N,
+ TNETV107X_TDM0_FS,
+ TNETV107X_AIC_HDS_EN_STAT_N,
+ TNETV107X_TDM0_TX,
+ TNETV107X_AIC_HNF_EN_STAT_N,
+ TNETV107X_TDM0_RX,
+};
+
+#define PINMUX(x) (4 * (x))
+
+#ifdef CONFIG_DAVINCI_MUX
+/* setup pin muxing */
+extern int davinci_cfg_reg(unsigned long reg_cfg);
+extern int davinci_cfg_reg_list(const short pins[]);
+#else
+/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
+static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+static inline int davinci_cfg_reg_list(const short pins[])
+{
+ return 0;
+}
+#endif
+
+#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
new file mode 100644
index 00000000000..1cf555aef89
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -0,0 +1,90 @@
+/*
+ * mach-davinci/nand.h
+ *
+ * Copyright © 2006 Texas Instruments.
+ *
+ * Ported to 2.6.23 Copyright © 2008 by
+ * Sander Huijsen <Shuijsen@optelecom-nkf.com>
+ * Troy Kisky <troy.kisky@boundarydevices.com>
+ * Dirk Behme <Dirk.Behme@gmail.com>
+ *
+ * --------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_DAVINCI_NAND_H
+#define __ARCH_ARM_DAVINCI_NAND_H
+
+#include <linux/mtd/nand.h>
+
+#define NANDFCR_OFFSET 0x60
+#define NANDFSR_OFFSET 0x64
+#define NANDF1ECC_OFFSET 0x70
+
+/* 4-bit ECC syndrome registers */
+#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
+#define NAND_4BIT_ECC1_OFFSET 0xc0
+#define NAND_4BIT_ECC2_OFFSET 0xc4
+#define NAND_4BIT_ECC3_OFFSET 0xc8
+#define NAND_4BIT_ECC4_OFFSET 0xcc
+#define NAND_ERR_ADD1_OFFSET 0xd0
+#define NAND_ERR_ADD2_OFFSET 0xd4
+#define NAND_ERR_ERRVAL1_OFFSET 0xd8
+#define NAND_ERR_ERRVAL2_OFFSET 0xdc
+
+/* NOTE: boards don't need to use these address bits
+ * for ALE/CLE unless they support booting from NAND.
+ * They're used unless platform data overrides them.
+ */
+#define MASK_ALE 0x08
+#define MASK_CLE 0x10
+
+struct davinci_nand_pdata { /* platform_data */
+ uint32_t mask_ale;
+ uint32_t mask_cle;
+
+ /* for packages using two chipselects */
+ uint32_t mask_chipsel;
+
+ /* board's default static partition info */
+ struct mtd_partition *parts;
+ unsigned nr_parts;
+
+ /* none == NAND_ECC_NONE (strongly *not* advised!!)
+ * soft == NAND_ECC_SOFT
+ * else == NAND_ECC_HW, according to ecc_bits
+ *
+ * All DaVinci-family chips support 1-bit hardware ECC.
+ * Newer ones also support 4-bit ECC, but are awkward
+ * using it with large page chips.
+ */
+ nand_ecc_modes_t ecc_mode;
+ u8 ecc_bits;
+
+ /* e.g. NAND_BUSWIDTH_16 */
+ unsigned options;
+ /* e.g. NAND_BBT_USE_FLASH */
+ unsigned bbt_options;
+
+ /* Main and mirror bbt descriptor overrides */
+ struct nand_bbt_descr *bbt_td;
+ struct nand_bbt_descr *bbt_md;
+
+ /* Access timings */
+ struct davinci_aemif_timing *timing;
+};
+
+#endif /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
new file mode 100644
index 00000000000..37b19bf35a8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -0,0 +1,54 @@
+/*
+ * TI DaVinci platform support for power management.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _MACH_DAVINCI_PM_H
+#define _MACH_DAVINCI_PM_H
+
+/*
+ * Caution: Assembly code in sleep.S makes assumtion on the order
+ * of the members of this structure.
+ */
+struct davinci_pm_config {
+ void __iomem *ddr2_ctlr_base;
+ void __iomem *ddrpsc_reg_base;
+ int ddrpsc_num;
+ void __iomem *ddrpll_reg_base;
+ void __iomem *deepsleep_reg;
+ void __iomem *cpupll_reg_base;
+ /*
+ * Note on SLEEPCOUNT:
+ * The SLEEPCOUNT feature is mainly intended for cases in which
+ * the internal oscillator is used. The internal oscillator is
+ * fully disabled in deep sleep mode. When you exist deep sleep
+ * mode, the oscillator will be turned on and will generate very
+ * small oscillations which will not be detected by the deep sleep
+ * counter. Eventually those oscillations will grow to an amplitude
+ * large enough to start incrementing the deep sleep counter.
+ * In this case recommendation from hardware engineers is that the
+ * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
+ * must be detected before the clock is passed to the rest of the
+ * system.
+ * In the case that the internal oscillator is not used and the
+ * clock is generated externally, the SLEEPCOUNT value can be very
+ * small since the clock input is assumed to be stable before SoC
+ * is taken out of deepsleep mode. A value of 128 would be more than
+ * adequate.
+ */
+ int sleepcount;
+};
+
+extern unsigned int davinci_cpu_suspend_sz;
+extern void davinci_cpu_suspend(struct davinci_pm_config *);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
new file mode 100644
index 00000000000..8bc3fc25617
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -0,0 +1,260 @@
+/*
+ * DaVinci Power & Sleep Controller (PSC) defines
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_ARCH_PSC_H
+#define __ASM_ARCH_PSC_H
+
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN 0
+#define DAVINCI_GPSC_DSPDOMAIN 1
+
+#define DAVINCI_LPSC_VPSSMSTR 0
+#define DAVINCI_LPSC_VPSSSLV 1
+#define DAVINCI_LPSC_TPCC 2
+#define DAVINCI_LPSC_TPTC0 3
+#define DAVINCI_LPSC_TPTC1 4
+#define DAVINCI_LPSC_EMAC 5
+#define DAVINCI_LPSC_EMAC_WRAPPER 6
+#define DAVINCI_LPSC_USB 9
+#define DAVINCI_LPSC_ATA 10
+#define DAVINCI_LPSC_VLYNQ 11
+#define DAVINCI_LPSC_UHPI 12
+#define DAVINCI_LPSC_DDR_EMIF 13
+#define DAVINCI_LPSC_AEMIF 14
+#define DAVINCI_LPSC_MMC_SD 15
+#define DAVINCI_LPSC_McBSP 17
+#define DAVINCI_LPSC_I2C 18
+#define DAVINCI_LPSC_UART0 19
+#define DAVINCI_LPSC_UART1 20
+#define DAVINCI_LPSC_UART2 21
+#define DAVINCI_LPSC_SPI 22
+#define DAVINCI_LPSC_PWM0 23
+#define DAVINCI_LPSC_PWM1 24
+#define DAVINCI_LPSC_PWM2 25
+#define DAVINCI_LPSC_GPIO 26
+#define DAVINCI_LPSC_TIMER0 27
+#define DAVINCI_LPSC_TIMER1 28
+#define DAVINCI_LPSC_TIMER2 29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
+#define DAVINCI_LPSC_ARM 31
+#define DAVINCI_LPSC_SCR2 32
+#define DAVINCI_LPSC_SCR3 33
+#define DAVINCI_LPSC_SCR4 34
+#define DAVINCI_LPSC_CROSSBAR 35
+#define DAVINCI_LPSC_CFG27 36
+#define DAVINCI_LPSC_CFG3 37
+#define DAVINCI_LPSC_CFG5 38
+#define DAVINCI_LPSC_GEM 39
+#define DAVINCI_LPSC_IMCOP 40
+
+#define DM355_LPSC_TIMER3 5
+#define DM355_LPSC_SPI1 6
+#define DM355_LPSC_MMC_SD1 7
+#define DM355_LPSC_McBSP1 8
+#define DM355_LPSC_PWM3 10
+#define DM355_LPSC_SPI2 11
+#define DM355_LPSC_RTO 12
+#define DM355_LPSC_VPSS_DAC 41
+
+/* DM365 */
+#define DM365_LPSC_TIMER3 5
+#define DM365_LPSC_SPI1 6
+#define DM365_LPSC_MMC_SD1 7
+#define DM365_LPSC_McBSP1 8
+#define DM365_LPSC_PWM3 10
+#define DM365_LPSC_SPI2 11
+#define DM365_LPSC_RTO 12
+#define DM365_LPSC_TIMER4 17
+#define DM365_LPSC_SPI0 22
+#define DM365_LPSC_SPI3 38
+#define DM365_LPSC_SPI4 39
+#define DM365_LPSC_EMAC 40
+#define DM365_LPSC_VOICE_CODEC 44
+#define DM365_LPSC_DAC_CLK 46
+#define DM365_LPSC_VPSSMSTR 47
+#define DM365_LPSC_MJCP 50
+
+/*
+ * LPSC Assignments
+ */
+#define DM646X_LPSC_ARM 0
+#define DM646X_LPSC_C64X_CPU 1
+#define DM646X_LPSC_HDVICP0 2
+#define DM646X_LPSC_HDVICP1 3
+#define DM646X_LPSC_TPCC 4
+#define DM646X_LPSC_TPTC0 5
+#define DM646X_LPSC_TPTC1 6
+#define DM646X_LPSC_TPTC2 7
+#define DM646X_LPSC_TPTC3 8
+#define DM646X_LPSC_PCI 13
+#define DM646X_LPSC_EMAC 14
+#define DM646X_LPSC_VDCE 15
+#define DM646X_LPSC_VPSSMSTR 16
+#define DM646X_LPSC_VPSSSLV 17
+#define DM646X_LPSC_TSIF0 18
+#define DM646X_LPSC_TSIF1 19
+#define DM646X_LPSC_DDR_EMIF 20
+#define DM646X_LPSC_AEMIF 21
+#define DM646X_LPSC_McASP0 22
+#define DM646X_LPSC_McASP1 23
+#define DM646X_LPSC_CRGEN0 24
+#define DM646X_LPSC_CRGEN1 25
+#define DM646X_LPSC_UART0 26
+#define DM646X_LPSC_UART1 27
+#define DM646X_LPSC_UART2 28
+#define DM646X_LPSC_PWM0 29
+#define DM646X_LPSC_PWM1 30
+#define DM646X_LPSC_I2C 31
+#define DM646X_LPSC_SPI 32
+#define DM646X_LPSC_GPIO 33
+#define DM646X_LPSC_TIMER0 34
+#define DM646X_LPSC_TIMER1 35
+#define DM646X_LPSC_ARM_INTC 45
+
+/* PSC0 defines */
+#define DA8XX_LPSC0_TPCC 0
+#define DA8XX_LPSC0_TPTC0 1
+#define DA8XX_LPSC0_TPTC1 2
+#define DA8XX_LPSC0_EMIF25 3
+#define DA8XX_LPSC0_SPI0 4
+#define DA8XX_LPSC0_MMC_SD 5
+#define DA8XX_LPSC0_AINTC 6
+#define DA8XX_LPSC0_ARM_RAM_ROM 7
+#define DA8XX_LPSC0_SECU_MGR 8
+#define DA8XX_LPSC0_UART0 9
+#define DA8XX_LPSC0_SCR0_SS 10
+#define DA8XX_LPSC0_SCR1_SS 11
+#define DA8XX_LPSC0_SCR2_SS 12
+#define DA8XX_LPSC0_PRUSS 13
+#define DA8XX_LPSC0_ARM 14
+#define DA8XX_LPSC0_GEM 15
+
+/* PSC1 defines */
+#define DA850_LPSC1_TPCC1 0
+#define DA8XX_LPSC1_USB20 1
+#define DA8XX_LPSC1_USB11 2
+#define DA8XX_LPSC1_GPIO 3
+#define DA8XX_LPSC1_UHPI 4
+#define DA8XX_LPSC1_CPGMAC 5
+#define DA8XX_LPSC1_EMIF3C 6
+#define DA8XX_LPSC1_McASP0 7
+#define DA830_LPSC1_McASP1 8
+#define DA850_LPSC1_SATA 8
+#define DA830_LPSC1_McASP2 9
+#define DA8XX_LPSC1_SPI1 10
+#define DA8XX_LPSC1_I2C 11
+#define DA8XX_LPSC1_UART1 12
+#define DA8XX_LPSC1_UART2 13
+#define DA8XX_LPSC1_LCDC 16
+#define DA8XX_LPSC1_PWM 17
+#define DA850_LPSC1_MMC_SD1 18
+#define DA8XX_LPSC1_ECAP 20
+#define DA830_LPSC1_EQEP 21
+#define DA850_LPSC1_TPTC2 21
+#define DA8XX_LPSC1_SCR_P0_SS 24
+#define DA8XX_LPSC1_SCR_P1_SS 25
+#define DA8XX_LPSC1_CR_P3_SS 26
+#define DA8XX_LPSC1_L3_CBA_RAM 31
+
+/* TNETV107X LPSC Assignments */
+#define TNETV107X_LPSC_ARM 0
+#define TNETV107X_LPSC_GEM 1
+#define TNETV107X_LPSC_DDR2_PHY 2
+#define TNETV107X_LPSC_TPCC 3
+#define TNETV107X_LPSC_TPTC0 4
+#define TNETV107X_LPSC_TPTC1 5
+#define TNETV107X_LPSC_RAM 6
+#define TNETV107X_LPSC_MBX_LITE 7
+#define TNETV107X_LPSC_LCD 8
+#define TNETV107X_LPSC_ETHSS 9
+#define TNETV107X_LPSC_AEMIF 10
+#define TNETV107X_LPSC_CHIP_CFG 11
+#define TNETV107X_LPSC_TSC 12
+#define TNETV107X_LPSC_ROM 13
+#define TNETV107X_LPSC_UART2 14
+#define TNETV107X_LPSC_PKTSEC 15
+#define TNETV107X_LPSC_SECCTL 16
+#define TNETV107X_LPSC_KEYMGR 17
+#define TNETV107X_LPSC_KEYPAD 18
+#define TNETV107X_LPSC_GPIO 19
+#define TNETV107X_LPSC_MDIO 20
+#define TNETV107X_LPSC_SDIO0 21
+#define TNETV107X_LPSC_UART0 22
+#define TNETV107X_LPSC_UART1 23
+#define TNETV107X_LPSC_TIMER0 24
+#define TNETV107X_LPSC_TIMER1 25
+#define TNETV107X_LPSC_WDT_ARM 26
+#define TNETV107X_LPSC_WDT_DSP 27
+#define TNETV107X_LPSC_SSP 28
+#define TNETV107X_LPSC_TDM0 29
+#define TNETV107X_LPSC_VLYNQ 30
+#define TNETV107X_LPSC_MCDMA 31
+#define TNETV107X_LPSC_USB0 32
+#define TNETV107X_LPSC_TDM1 33
+#define TNETV107X_LPSC_DEBUGSS 34
+#define TNETV107X_LPSC_ETHSS_RGMII 35
+#define TNETV107X_LPSC_SYSTEM 36
+#define TNETV107X_LPSC_IMCOP 37
+#define TNETV107X_LPSC_SPARE 38
+#define TNETV107X_LPSC_SDIO1 39
+#define TNETV107X_LPSC_USB1 40
+#define TNETV107X_LPSC_USBSS 41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
+#define TNETV107X_LPSC_MAX 44
+
+/* PSC register offsets */
+#define EPCPR 0x070
+#define PTCMD 0x120
+#define PTSTAT 0x128
+#define PDSTAT 0x200
+#define PDCTL 0x300
+#define MDSTAT 0x800
+#define MDCTL 0xA00
+
+/* PSC module states */
+#define PSC_STATE_SWRSTDISABLE 0
+#define PSC_STATE_SYNCRST 1
+#define PSC_STATE_DISABLE 2
+#define PSC_STATE_ENABLE 3
+
+#define MDSTAT_STATE_MASK 0x3f
+#define PDSTAT_STATE_MASK 0x1f
+#define MDCTL_FORCE BIT(31)
+#define PDCTL_NEXT BIT(1)
+#define PDCTL_EPCGOOD BIT(8)
+
+#ifndef __ASSEMBLER__
+
+extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
+extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
+ unsigned int id, bool enable, u32 flags);
+
+#endif
+
+#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
new file mode 100644
index 00000000000..e347d88fef9
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -0,0 +1,58 @@
+/*
+ * DaVinci serial device definitions
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <asm/memory.h>
+
+#include <mach/hardware.h>
+
+/*
+ * Stolen area that contains debug uart physical and virtual addresses. These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ * We define it as a relative offset from start of usable RAM.
+ */
+#define DAVINCI_UART_INFO_OFS 0x3ff8
+
+#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
+#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
+#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
+
+#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
+#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
+#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
+
+#define TNETV107X_UART0_BASE 0x08108100
+#define TNETV107X_UART1_BASE 0x08088400
+#define TNETV107X_UART2_BASE 0x08108300
+
+#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
+#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
+#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
+
+/* DaVinci UART register offsets */
+#define UART_DAVINCI_PWREMU 0x0c
+#define UART_DM646X_SCR 0x10
+#define UART_DM646X_SCR_TX_WATERMARK 0x08
+
+#ifndef __ASSEMBLY__
+struct davinci_uart_config {
+ /* Bit field of UARTs present; bit 0 --> UART1 */
+ unsigned int enabled_uarts;
+};
+
+extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
new file mode 100644
index 00000000000..7af305b3786
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_DAVINCI_SPI_H
+#define __ARCH_ARM_DAVINCI_SPI_H
+
+#include <mach/edma.h>
+
+#define SPI_INTERN_CS 0xFF
+
+enum {
+ SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+ SPI_VERSION_2, /* For DA8xx */
+};
+
+/**
+ * davinci_spi_platform_data - Platform data for SPI master device on DaVinci
+ *
+ * @version: version of the SPI IP. Different DaVinci devices have slightly
+ * varying versions of the same IP.
+ * @num_chipselect: number of chipselects supported by this SPI master
+ * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
+ * controller withn the SoC. Possible values are 0 and 1.
+ * @chip_sel: list of GPIOs which can act as chip-selects for the SPI.
+ * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
+ * to populate if all chip-selects are internal.
+ * @cshold_bug: set this to true if the SPI controller on your chip requires
+ * a write to CSHOLD bit in between transfers (like in DM355).
+ * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
+ * device on the bus.
+ */
+struct davinci_spi_platform_data {
+ u8 version;
+ u8 num_chipselect;
+ u8 intr_line;
+ u8 *chip_sel;
+ bool cshold_bug;
+ enum dma_event_q dma_event_q;
+};
+
+/**
+ * davinci_spi_config - Per-chip-select configuration for SPI slave devices
+ *
+ * @wdelay: amount of delay between transmissions. Measured in number of
+ * SPI module clocks.
+ * @odd_parity: polarity of parity flag at the end of transmit data stream.
+ * 0 - odd parity, 1 - even parity.
+ * @parity_enable: enable transmission of parity at end of each transmit
+ * data stream.
+ * @io_type: type of IO transfer. Choose between polled, interrupt and DMA.
+ * @timer_disable: disable chip-select timers (setup and hold)
+ * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured
+ * in number of SPI clocks.
+ * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in
+ * number of SPI clocks.
+ */
+struct davinci_spi_config {
+ u8 wdelay;
+ u8 odd_parity;
+ u8 parity_enable;
+#define SPI_IO_TYPE_INTR 0
+#define SPI_IO_TYPE_POLL 1
+#define SPI_IO_TYPE_DMA 2
+ u8 io_type;
+ u8 timer_disable;
+ u8 c2tdelay;
+ u8 t2cdelay;
+ u8 t2edelay;
+ u8 c2edelay;
+};
+
+#endif /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
new file mode 100644
index 00000000000..111f7cc71e0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -0,0 +1,27 @@
+/*
+ * mach/sram.h - DaVinci simple SRAM allocator
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_SRAM_H
+#define __MACH_SRAM_H
+
+/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
+#define SRAM_GRANULARITY 512
+
+/*
+ * SRAM allocations return a CPU virtual address, or NULL on error.
+ * If a DMA address is requested and the SRAM supports DMA, its
+ * mapped address is also returned.
+ *
+ * Errors include SRAM memory not being available, and requesting
+ * DMA mapped SRAM on systems which don't allow that.
+ */
+extern void *sram_alloc(size_t len, dma_addr_t *dma);
+extern void sram_free(void *addr, size_t len);
+
+#endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
new file mode 100644
index 00000000000..fcb7a015aba
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -0,0 +1,21 @@
+/*
+ * DaVinci system defines
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/common.h>
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 00000000000..1c971d8d8ba
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,35 @@
+/*
+ * Local header file for DaVinci time code.
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
+#define __ARCH_ARM_MACH_DAVINCI_TIME_H
+
+#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
+#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
+#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
+
+enum {
+ T0_BOT,
+ T0_TOP,
+ T1_BOT,
+ T1_TOP,
+ NUM_TIMERS
+};
+
+#define IS_TIMER1(id) (id & 0x2)
+#define IS_TIMER0(id) (!IS_TIMER1(id))
+#define IS_TIMER_TOP(id) ((id & 0x1))
+#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
+
+#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
+
+extern struct davinci_timer_instance davinci_timer_instance[];
+
+#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
new file mode 100644
index 00000000000..9b885298f10
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/timex.h
@@ -0,0 +1,22 @@
+/*
+ * DaVinci timer defines
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
+ * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
+ * linux/jiffies.h) are not used directly in code. Currently none of the
+ * code relevant to DaVinci platform depends on these values directly.
+ */
+#define CLOCK_TICK_RATE 27000000
+
+#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
new file mode 100644
index 00000000000..83e5926f3c4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -0,0 +1,61 @@
+/*
+ * Texas Instruments TNETV107X SoC Specific Defines
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
+#define __ASM_ARCH_DAVINCI_TNETV107X_H
+
+#include <asm/sizes.h>
+
+#define TNETV107X_DDR_BASE 0x80000000
+
+/*
+ * Fixed mapping for early init starts here. If low-level debug is enabled,
+ * this area also gets mapped via io_pg_offset and io_phys by the boot code.
+ * To fit in with the io_pg_offset calculation, the io base address selected
+ * here _must_ be a multiple of 2^20.
+ */
+#define TNETV107X_IO_BASE 0x08000000
+#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
+
+#define TNETV107X_N_GPIO 65
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/mfd/ti_ssp.h>
+
+#include <mach/mmc.h>
+#include <mach/nand.h>
+#include <mach/serial.h>
+
+struct tnetv107x_device_info {
+ struct davinci_uart_config *serial_config;
+ struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
+ struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
+ struct matrix_keypad_platform_data *keypad_config;
+ struct ti_ssp_data *ssp_config;
+};
+
+extern struct platform_device tnetv107x_wdt_device;
+extern struct platform_device tnetv107x_serial_device;
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void __init tnetv107x_irq_init(void);
+void tnetv107x_restart(char mode, const char *cmd);
+
+#endif
+
+#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
new file mode 100644
index 00000000000..9dc7cf9664f
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -0,0 +1,106 @@
+/*
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Original copyrights follow.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/serial.h>
+
+u32 *uart;
+
+/* PORT_16C550A, in polled non-fifo mode */
+static void putc(char c)
+{
+ while (!(uart[UART_LSR] & UART_LSR_THRE))
+ barrier();
+ uart[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+ while (!(uart[UART_LSR] & UART_LSR_THRE))
+ barrier();
+}
+
+static inline void set_uart_info(u32 phys, void * __iomem virt)
+{
+ /*
+ * Get address of some.bss variable and round it down
+ * a la CONFIG_AUTO_ZRELADDR.
+ */
+ u32 ram_start = (u32)&uart & 0xf8000000;
+ u32 *uart_info = (u32 *)(ram_start + DAVINCI_UART_INFO_OFS);
+
+ uart = (u32 *)phys;
+ uart_info[0] = phys;
+ uart_info[1] = (u32)virt;
+}
+
+#define _DEBUG_LL_ENTRY(machine, phys, virt) \
+ if (machine_is_##machine()) { \
+ set_uart_info(phys, virt); \
+ break; \
+ }
+
+#define DEBUG_LL_DAVINCI(machine, port) \
+ _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE, \
+ IO_ADDRESS(DAVINCI_UART##port##_BASE))
+
+#define DEBUG_LL_DA8XX(machine, port) \
+ _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE, \
+ IO_ADDRESS(DA8XX_UART##port##_BASE))
+
+#define DEBUG_LL_TNETV107X(machine, port) \
+ _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE, \
+ TNETV107X_UART##port##_VIRT)
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+ /*
+ * Initialize the port based on the machine ID from the bootloader.
+ * Note that we're using macros here instead of switch statement
+ * as machine_is functions are optimized out for the boards that
+ * are not selected.
+ */
+ do {
+ /* Davinci boards */
+ DEBUG_LL_DAVINCI(davinci_evm, 0);
+ DEBUG_LL_DAVINCI(sffsdr, 0);
+ DEBUG_LL_DAVINCI(neuros_osd2, 0);
+ DEBUG_LL_DAVINCI(davinci_dm355_evm, 0);
+ DEBUG_LL_DAVINCI(dm355_leopard, 0);
+ DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0);
+ DEBUG_LL_DAVINCI(davinci_dm365_evm, 0);
+
+ /* DA8xx boards */
+ DEBUG_LL_DA8XX(davinci_da830_evm, 2);
+ DEBUG_LL_DA8XX(davinci_da850_evm, 2);
+ DEBUG_LL_DA8XX(mityomapl138, 1);
+ DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
+
+ /* TNETV107x boards */
+ DEBUG_LL_TNETV107X(tnetv107x, 1);
+ } while (0);
+}
+
+#define arch_decomp_setup() __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h
new file mode 100644
index 00000000000..e0bc4abe69c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/usb.h
@@ -0,0 +1,59 @@
+/*
+ * USB related definitions
+ *
+ * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_USB_H
+#define __ASM_ARCH_USB_H
+
+/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
+#define CFGCHIP2_PHYCLKGD (1 << 17)
+#define CFGCHIP2_VBUSSENSE (1 << 16)
+#define CFGCHIP2_RESET (1 << 15)
+#define CFGCHIP2_OTGMODE (3 << 13)
+#define CFGCHIP2_NO_OVERRIDE (0 << 13)
+#define CFGCHIP2_FORCE_HOST (1 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
+#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
+#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
+#define CFGCHIP2_PHYPWRDN (1 << 10)
+#define CFGCHIP2_OTGPWRDN (1 << 9)
+#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_USB1SUSPENDM (1 << 7)
+#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
+#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
+#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
+#define CFGCHIP2_REFFREQ (0xf << 0)
+#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
+#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
+#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
+
+struct da8xx_ohci_root_hub;
+
+typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
+ unsigned port);
+
+/* Passed as the platform data to the OHCI driver */
+struct da8xx_ohci_root_hub {
+ /* Switch the port power on/off */
+ int (*set_power)(unsigned port, int on);
+ /* Read the port power status */
+ int (*get_power)(unsigned port);
+ /* Read the port over-current indicator */
+ int (*get_oci)(unsigned port);
+ /* Over-current indicator change notification (pass NULL to disable) */
+ int (*ocic_notify)(da8xx_ocic_handler_t handler);
+
+ /* Time from power on to power good (in 2 ms units) */
+ u8 potpgt;
+};
+
+void davinci_setup_usb(unsigned mA, unsigned potpgt_ms);
+
+#endif /* ifndef __ASM_ARCH_USB_H */